A control logic circuit and SAR ADC

Abstract

The present invention discloses a control logic circuit and a SAR ADC, which are used to solve the problems of timing waste and conversion process errors in the control logic circuit of the SAR ADC. The control logic circuit includes a signal generating module, an HLU module and a signal conversion module. The signal generating module converts the input clock signal to obtain a sampling signal, a control clock signal and a synchronous clock signal; the HLU module generates a target bit control signal based on a comparison completion signal or a synchronous clock signal; and the signal conversion module samples the comparison result signal under the control of the target bit control signal to obtain a valid bit signal. Since the target bit control signal can be generated by the comparison completion signal, the comparison time of each bit signal can be adaptively adjusted, thereby reducing timing waste. In addition, the target bit control signal can also be generated by the synchronous clock signal, thereby reducing the probability of errors in the conversion process when the comparison completion signal cannot be output.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a control logic circuit and a SAR ADC. Background Art

[0002] An analog-to-digital converter (ADC) is a device used to convert analog signals, which are continuous in time and amplitude, into digital signals, which are discrete in time and amplitude. Real-world analog signals, such as temperature, pressure, sound, or images, need to be converted into digital signals that are easier to store, process, and transmit. Therefore, the ADC serves as a bridge between the analog and digital worlds. With the rapid development of integrated circuits, new ADC design concepts and manufacturing technologies have emerged continuously, resulting in a wide variety of ADCs with different structures and performance characteristics designed to meet diverse detection and control needs. ADCs can be divided into four types based on their characteristics: parallel ADCs, pipeline ADCs, oversampling ADCs, and successive approximation ADCs. Each type has its own advantages and disadvantages, as well as suitable application scenarios.

[0003] Among numerous ADC architectures, the Successive Approximation Register (SAR) ADC uses a high-speed, high-precision comparator to compare the analog input with the output of the previous analog-to-digital conversion result after passing through a digital-to-analog converter (DAC). This comparator sequentially obtains each bit, from the most significant bit (MSB) to the least significant bit (LSB), gradually approximating the input analog signal. SAR ADCs have a simple structure, and most of their circuitry can be implemented digitally. They are highly compatible with advanced CMOS (Complementary Metal-Oxide-Semiconductor) processes. Compared to other ADC types, they offer advantages such as smaller chip area and higher energy efficiency, making them a mainstream architecture for ADC implementations using advanced processes.

[0004] In the prior art, the main structure of a SAR ADC typically consists of a sampling switch, a capacitive digital-to-analog converter (CDAC), a comparator, and a control logic circuit. The control logic circuit of a SAR ADC is generally either purely synchronous or purely asynchronous. However, the fixed time allocation in synchronous control logic leads to timing waste, thereby reducing ADC performance. In asynchronous control logic, the presence of metastable states can cause errors in the conversion process.

[0005] In summary, the control logic circuit of the SAR ADC in the prior art has the problems of timing waste and errors in the conversion process. Summary of the Invention

[0006] The present invention provides a control logic circuit and a SAR ADC, which are used to solve the problems of timing waste and conversion process errors in the control logic circuit of the SAR ADC in the prior art.

[0007] In a first aspect, the present invention provides a control logic circuit for use with a SAR ADC, the circuit comprising:

[0008] The signal generating module is used to convert the input clock signal to obtain the sampling signal, the control clock signal and the synchronization clock signal;

[0009] An HLU module is configured to generate a target bit control signal based on a comparison completion signal or the synchronization clock signal;

[0010] A signal conversion module, configured to sample the comparison result signal under the control of the target bit control signal to obtain a valid bit signal;

[0011] The comparison completion signal and the comparison result signal are generated by a comparator in the SAR ADC.

[0012] In the above-mentioned control logic circuit, the signal generation module is used to convert the input clock signal to obtain a sampling signal, a control clock signal, and a synchronous clock signal respectively; the HLU module is used to generate a target bit control signal based on the comparison completion signal or the synchronous clock signal generated by the comparator; and the signal conversion module is used to sample the comparison result signal generated by the comparator under the control of the target bit control signal to obtain a valid bit signal. Since the target bit control signal for the control signal conversion is generated by the comparison completion signal or the synchronous clock signal, the comparison time of each bit signal can be adaptively adjusted, thereby reducing the timing waste in the synchronous control logic circuit. In addition, when the synchronous clock signal arrives first, the target bit control signal is generated by the synchronous clock signal, thereby reducing the probability of errors in the conversion process when the comparison completion signal cannot be output.

[0013] In a possible implementation, the signal generating module includes a sampling signal generating unit, a control clock signal generating unit, and a multi-stage synchronous clock signal generating unit;

[0014] The sampling signal generating unit is configured to sample the input clock signal based on a preset clock cycle to obtain the sampling signal;

[0015] The control clock signal generating unit is configured to perform a logic operation on the input clock signal and the sampling signal to obtain the control clock signal;

[0016] The synchronous clock signal generating unit at each stage is used to output the synchronous clock signal based on the input clock signal.

[0017] In the aforementioned signal generation module, the sampling signal generation unit generates a sampling signal that controls the on / off switching of the sampling switch; the control clock signal generation unit generates a control clock signal that enables or resets the comparator; and the synchronous clock signal generation unit comprises multiple stages, each of which outputs a synchronous clock signal based on the input clock signal. Based on the input clock signal, the signal generation module generates various control signals, which in turn control the operating states of certain circuits.

[0018] In a possible implementation, the HLU module includes HLU units corresponding one-to-one to the synchronous clock signal generating units;

[0019] The HLU unit at each level is used to generate the target bit control signal based on the comparison completion signal when the rising edge of the comparison completion signal is earlier than the rising edge of the synchronization clock signal, and to generate the target bit control signal based on the synchronization clock signal when the rising edge of the comparison completion signal is later than the rising edge of the synchronization clock signal.

[0020] The HLU module includes HLU units, each of which is used to generate a target bit control signal based on a comparison completion signal or a synchronous clock signal. Because the target bit control signal isn't generated solely upon the rising edge of either the synchronous clock signal or the comparison completion signal, but rather based on the signal with the earliest rising edge, adaptive adjustment of the comparison time eliminates timing waste in the control logic circuit and allows the CDAC more time for signal establishment. This improves the overall signal-to-noise ratio of the SAR ADC within certain clock frequency constraints. Furthermore, it reduces the likelihood of conversion errors caused by metastable states.

[0021] In a possible implementation, the sampling signal generating unit includes a first NOT gate, a second NOT gate, and k first D flip-flops, where k is a positive integer;

[0022] The input end of the first NOT gate is connected to the output end of the HLU unit of the last stage, and the output end of the first NOT gate is connected to the D end of the first D flip-flop;

[0023] The input end of the second NOT gate is connected to the Q end of the last of the first D flip-flops, and the output end of the second NOT gate serves as the output end of the sampling signal generating unit, for outputting the sampling signal;

[0024] The CLK terminal of each first D flip-flop serves as the input terminal of the sampling signal generating unit, and is used to input the input clock signal. The R terminal of each first D flip-flop is connected to the input terminal of the first NOT gate, and the D terminal of the subsequent first D flip-flop is connected to the Q terminal of the previous first D flip-flop.

[0025] The sampling signal generating unit is used to sample the input clock signal based on a preset clock cycle to obtain a sampling signal. The sampling signal controls the on or off state of the sampling switch, thereby controlling whether the circuit performs a sampling operation.

[0026] In a possible implementation, the control clock signal generating unit includes a first OR gate;

[0027] The first input end of the first OR gate is used to input the input clock signal, the second input end of the first OR gate is used to input the sampling signal, and the output end of the first OR gate is used to output the control clock signal.

[0028] The control clock signal generating unit disclosed in the present invention is used to perform logic operations on an input clock signal and a sampling signal to obtain a control clock signal. The control clock signal controls the enabling or resetting of a comparator, thereby controlling whether the circuit enters a comparison working state.

[0029] In a possible implementation, each stage of the synchronous clock signal generating unit includes a second D flip-flop;

[0030] The D terminal of the second D flip-flop of the first stage is connected to the input terminal of the second NOT gate, the D terminal of the second D flip-flop of the next stage is connected to the Q terminal of the second D flip-flop of the previous stage, and the Q terminal of the second D flip-flop of the last stage is connected to the R terminal of the second D flip-flop of the other stage and the input terminal of the first NOT gate. The CLK terminal of the second D flip-flop of each stage is used to input the input clock signal, and the Q terminal of the second D flip-flop of each stage serves as the output terminal of the synchronization bit controller signal generating unit of this stage, and is used to output the synchronization clock signal of this stage.

[0031] In the above scheme, each level of synchronous clock signal generating unit converts the input clock signal into a synchronous clock signal through a D flip-flop. The synchronous clock signal serves as the input of the HLU module, so that the HLU module outputs the target bit control signal.

[0032] In a possible implementation, each of the HLU units includes a third NOT gate, a second OR gate, a third OR gate, and a third D flip-flop;

[0033] The input end of the first NOT gate is connected to the D end of the second D flip-flop corresponding to the HLU unit, and the output end of the first NOT gate is connected to the first input end of the second OR gate;

[0034] The second input terminal of the second OR gate is connected to the Q terminal of the second D flip-flop and the second input terminal of the third OR gate, and the output terminal of the third OR gate is connected to the R terminal of the third D flip-flop;

[0035] The CLK terminal of the third D flip-flop is used to input the comparison completion signal, the D terminal of the third D flip-flop is used to input the power supply voltage, and the Q terminal of the third D flip-flop is connected to the first input terminal of the third OR gate;

[0036] The output end of the third OR gate serves as the output end of the HLU unit, and is used to output the target bit control signal.

[0037] In the above scheme, the HLU unit is configured to output a target bit control signal based on the comparison completion signal when the rising edge of the comparison completion signal precedes the rising edge of the synchronous clock signal; and to output the target bit control signal based on the synchronous clock signal when the rising edge of the comparison completion signal lags behind the rising edge of the synchronous clock signal. Outputting the target bit control signal based on the comparison completion signal reduces timing waste, while outputting the target bit control signal based on the synchronous clock signal reduces errors during the conversion process caused by metastable states.

[0038] In a possible implementation, the HLU unit further includes a delay device;

[0039] The input end of the delay device is used to input the input clock signal, and the output end of the delay device is connected to the input end of the third NOT gate.

[0040] In the above scheme, the delay device is used to prevent the third D flip-flop from erroneously sampling the rising edge of the comparison completion signal of the previous bit, thereby generating an erroneous target bit control signal. Moreover, the delay device has a simple structure, is easy to implement, and has no effect on other circuits.

[0041] In a possible implementation, the signal conversion module includes a fourth D flip-flop corresponding one-to-one to the HLU unit;

[0042] For each group of HLU units and fourth D flip-flops, the CLK terminal of the fourth D flip-flop is connected to the output terminal of the HLU unit, the D terminal of the fourth D flip-flop is used to input the comparison result signal, and the Q terminal of the fourth D flip-flop is used to output the most significant bit signal.

[0043] The control logic circuit described above adaptively allocates time for each comparison and settling step of the SAR ADC, avoiding wasted timing while optimizing the CDAC settling process. On the one hand, the voltage difference at the CDAC output during high-bit comparison is larger, allowing the comparator to make a quick judgment and leaving a longer remaining time. On the other hand, during high-bit comparison, the reference voltage terminal VREF requires a larger capacitance, requiring a longer settling time. Therefore, this control logic circuit provides longer settling time for high-bit CDAC switching, achieving more reasonable timing allocation. Furthermore, if the comparator experiences metastable conditions, this control logic circuit uses a synchronous clock signal to generate the next target bit control signal, forcibly interrupting the conversion of that bit without affecting subsequent conversion processes, effectively improving the performance of the SAR ADC.

[0044] In a second aspect, the present invention further provides a SAR ADC, comprising a sampling switch, a capacitive digital-to-analog converter (CDAC), a comparator, and any of the control logic circuits described above, wherein:

[0045] The sampling switch is used to open or close the path between the signal input terminal and the CDAC sampling terminal under the control of the sampling signal output by the control logic circuit;

[0046] The CDAC is used to sample the input signal when the sampling switch is closed;

[0047] The comparator is used to compare the first voltage signal and the second voltage signal maintained on the CDAC under the control of the control clock signal output by the logic control circuit, and output a comparison completion signal and a comparison result signal.

[0048] For the technical effects that may be achieved by the SAR ADC disclosed in the second aspect, please refer to the above description of the technical effects that may be achieved by the first aspect or various possible solutions in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 A schematic structural diagram of a SAR ADC provided by the present invention;

[0051] Figure 2 A schematic structural diagram of a CDAC provided by the present invention;

[0052] Figure 3 A schematic structural diagram of a comparator provided by the present invention;

[0053] Figure 4 A circuit diagram of a comparator provided by the present invention;

[0054] Figure 5 A structural diagram of a synchronous control logic circuit provided for related technology;

[0055] Figure 6 A working timing diagram of a synchronous control logic circuit provided for related technology;

[0056] Figure 7 A schematic diagram of the structure of an asynchronous control logic circuit provided in the related art;

[0057] Figure 8 A working timing diagram of an asynchronous control logic circuit provided for related technology;

[0058] Figure 9 A schematic structural diagram of a control logic circuit provided by the present invention;

[0059] Figure 10 A schematic structural diagram of a signal generating module provided by the present invention;

[0060] Figure 11A schematic structural diagram of a sampling signal generating unit provided by the present invention;

[0061] Figure 12 A schematic structural diagram of a control clock signal generating unit provided by the present invention;

[0062] Figure 13 A schematic structural diagram of a synchronous clock signal generating unit provided by the present invention;

[0063] Figure 14 A circuit diagram of another signal generating module provided by the present invention;

[0064] Figure 15 A circuit diagram of an HLU module provided by the present invention;

[0065] Figure 16 A working timing diagram of a control logic circuit provided by the present invention;

[0066] Figure 17 A schematic structural diagram of a control logic circuit provided by the present invention;

[0067] Figure 18 A schematic structural diagram of an HLU module provided by the present invention;

[0068] Figure 19 A schematic structural diagram of another HLU module provided by the present invention;

[0069] Figure 20 Another working timing diagram of the control logic circuit provided by the present invention;

[0070] Figure 21 Another working timing diagram of the control logic circuit provided by the present invention;

[0071] Figure 22 Another working timing diagram of the control logic circuit provided by the present invention;

[0072] Figure 23 This is a structural diagram of a signal conversion module provided by the present invention. DETAILED DESCRIPTION

[0073] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only some, not all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0074] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0075] With the rapid development of integrated circuits, new ADC design concepts and manufacturing technologies are constantly emerging. A wide variety of ADCs with different structures and performances are designed to meet diverse detection and control needs. Among the various ADC architectures, SARADCs offer a simple structure, most of which can be implemented digitally. They are highly compatible with advanced CMOS processes and offer advantages such as smaller chip area and higher energy efficiency compared to other ADC types. They are a mainstream architecture for ADC implementations using advanced processes.

[0076] Figure 1 The schematic diagram of the structure of the SAR ADC with n-bit resolution is shown in FIG. 1 , where n is a positive integer. Figure 1 As shown, the main structure of the SAR ADC generally includes: a sampling switch 11 , a CDAC 12 , a comparator 13 and a control logic circuit 14 .

[0077] The sampling switch 11 includes a first sampling switch K1 and a second sampling switch K2. The sampling switch 11 is configured to close when a rising edge of the sampling signal clks generated by the control logic circuit 14 arrives, and sample the signal at the first input signal terminal VinP and the signal at the second input signal terminal VinN onto the CDAC 12. The sampling switch 11 is configured to open when a falling edge of the sampling signal clks generated by the control logic circuit 14 arrives, and sampling ends.

[0078] like Figure 2As shown, the CDAC 12 includes a first capacitor array 121 consisting of n+1 capacitors and n three-selection switches, and a second capacitor array 122 consisting of n+1 capacitors and n three-selection switches, where n is a positive integer. The bottom plate of each of the n capacitors in the first capacitor array 121 is connected to one end of each three-selection switch in a one-to-one correspondence, and the selection end of each three-selection switch is connected to the reference voltage terminal VREF, the ground terminal GND, and the common mode voltage VCM respectively. The top plates of each of the n capacitors in the first capacitor array 121 are connected to each other to form a first common terminal 211. The first input signal terminal VinP is connected to the first common terminal 211 through the first sampling switch K1. The first common terminal 211 is also connected to the positive input terminal of the comparator 13. One end of another capacitor C in the first capacitor array 121 is connected to the positive input terminal of the comparator 13. The first common terminal 211 is connected to the first common terminal 211, and the other end of the other capacitor C is connected to the common-mode voltage VCM; the lower plate of each of the n capacitors in the second capacitor array 122 is respectively connected to one end of each three-selection switch in a one-to-one correspondence, and the selection end of each three-selection switch is respectively connected to the reference voltage terminal VREF, the ground terminal GND and the common-mode voltage VCM. The upper plates of each of the n capacitors in the second capacitor array 122 are interconnected to form a second common terminal 212. The second input signal terminal VinN is connected to the second common terminal 212 through the second sampling switch K2. The second common terminal 212 is also connected to the inverting input terminal of the comparator 13. One end of another capacitor C in the second capacitor array 122 is connected to the second common terminal 212, and the other end of the other capacitor C is connected to the common-mode voltage VCM.

[0079] Combine Figure 1 and Figure 2 During the sampling process, the first sampling switch K1 is closed, and the first input signal vinP is sampled onto the first capacitor array 121; the second sampling switch K2 is closed, and the second input signal vinN is sampled onto the second capacitor array 122; and, during the comparison process, the first voltage signal vip maintained on the first capacitor array 121 is input to the positive input terminal of the comparator 13, and the second voltage signal vin maintained on the second capacitor array 122 is input to the negative input terminal of the comparator 13.

[0080] like Figure 3 As shown, the comparator 13 may include a latch circuit 131, a memory 132 and an XOR gate 133. The comparator 13 is generally a dynamic comparator, which is used to compare the first voltage signal vip inputted by the first voltage signal input terminal Vip and the second voltage signal vin inputted by the second voltage signal input terminal Vin, and output a comparison result signal comp and a comparison completion signal valid.

[0081] like Figure 4As shown, the latch circuit 131 may include a first NMOS transistor G1, a second NMOS transistor G2, a third NMOS transistor G3, an invertor INV1, an invertor INV2, a first PMOS transistor G4, a second PMOS transistor G5, a third PMOS transistor G6 and a fourth PMOS transistor G7, wherein the control end of the first NMOS transistor G1 is used to input a control clock signal clkc, the first end of the first NMOS transistor G1 is connected to the power supply voltage end VDD for inputting a power supply voltage, the second end of the first NMOS transistor G1 is respectively connected to the first end of the second NMOS transistor G2 and the first end of the third NMOS transistor G3, the control end of the second NMOS transistor G2 is connected to the second voltage signal input end Vin, the second end of the second NMOS transistor G2 is respectively connected to the input end of the invertor INV2, the second end of the first PMOS transistor G4, the second PMOS transistor G5 and the fourth PMOS transistor G6. The control end of the third PMOS transistor G5 is connected to the second end of the third PMOS transistor G6, the control end of the third NMOS transistor G3 is connected to the first voltage signal input terminal Vip, the second end of the third NMOS transistor G3 is respectively connected to the input end of the inverter INV1, the second end of the second PMOS transistor G5, the control end of the first PMOS transistor G4, and the second end of the fourth PMOS transistor G7, the first end of the first PMOS transistor G4, the first end of the second PMOS transistor G5, the first end of the third PMOS transistor G6, and the first end of the fourth PMOS transistor G7 are commonly connected to the ground terminal GND, the control end of the third PMOS transistor G6 and the control end of the fourth PMOS transistor G7 are both used to input the control clock signal clkc, the output end of the inverter INV2 serves as the output end of the second voltage output signal Von, and the output end of the inverter INV1 serves as the output end of the first voltage output signal Vop.

[0082] The latch circuit 131 is used to, when the first voltage signal vip and the second voltage signal vin are input, the NOT gate INV1 outputs the first voltage output signal Vop, and outputs the first voltage output signal Vop to the first input terminal of the memory 132 and the first input terminal of the XOR gate 133 respectively, and the NOT gate INV2 outputs the second voltage output signal Von, and outputs the second voltage output signal Von to the second input terminal of the memory 132 and the second input terminal of the XOR gate 133 respectively.

[0083] The memory 132 may include a first NAND gate Y1 and a second NAND gate Y2, wherein the first input terminal of the first NAND gate Y1 is connected to the output terminal of the invertor INV1 for inputting the first voltage output signal Vop, the second input terminal of the first NAND gate Y1 is connected to the output terminal of the second NAND gate Y2, the second input terminal of the second NAND gate Y2 is connected to the output terminal of the invertor INV2 for inputting the second voltage output signal Von, the first input terminal of the second NAND gate Y2 is connected to the output terminal of the first NAND gate Y, and the output terminal of the second NAND gate Y2 serves as the output terminal of the comparison result signal comp; the memory 132 is configured to output the comparison result signal comp when the first input terminal of the first NAND gate Y1 receives the first voltage output signal Vop and the second input terminal of the second NAND gate Y2 receives the second voltage output signal Von.

[0084] The XOR gate 133 may include an XOR gate Q, wherein the first input terminal of the XOR gate Q is connected to the output terminal of the NOT gate INV1 for inputting the first voltage output signal Vop, the second input terminal of the XOR gate Q is connected to the output terminal of the NOT gate INV2 for inputting the second voltage output signal Von, and the output terminal of the XOR gate Q is used to output a comparison completion signal valid; when the first input terminal of the XOR gate Q receives the first voltage output signal Vop and the second input terminal receives the second voltage output signal Von, the comparison completion signal valid is output.

[0085] In related technologies, the control logic circuit 14 can be a synchronous control logic circuit or an asynchronous control logic circuit.

[0086] like Figure 5 As shown in the figure, it is the circuit structure diagram of the synchronous control logic circuit. Figure 6 As shown in the figure, it is the working sequence diagram of the synchronous control logic circuit. Figures 1 to 5 For example, a synchronous SAR ADC usually uses a high-frequency input clock signal clkin (clock period is Tclkin) to control the working timing of the SAR ADC, and its control logic circuit 14 uses k clock periods to generate a sampling signal clks, such as Figure 5As shown, the sampling signal clks is generated by k D flip-flops in 501, where k is a positive integer. When the sampling signal clks is at a high level, the signal at the first input signal terminal VinP and the signal at the second input signal terminal VinN are sampled onto the CDAC 12 through the sampling switch 11; when the sampling signal clks jumps to a low level, the sampling process ends, and the CDAC 12 and the comparator 13 begin the conversion process under the control of the control clock signal clkc (the waveform during operation is consistent with the input clock signal clkin). When clkc is at a low level, the comparator 13 is enabled, and it obtains the comparison result signal comp based on the signal size at the input terminal; when clkc jumps to a high level, the comparator 13 enters the reset state, and the shift register in the control logic circuit 14 generates the synchronization bit control signal clk <n-1>, the synchronization bit control signal clk <n-1>The comparison result signal comp is sampled on the rising edge of the sync bit control signal clk, and the most significant bit signal D[n-1] is obtained. <n-1>The valid bit signal D[n-1] is generated by n D flip-flops in 502, and n is a positive integer. At the same time, the synchronization bit control signal clk <n-1>The most significant bit signal D[n-1] is output to CDAC12, connecting the most significant bit capacitor (2^(n-1)C) in CDAC12 to the reference voltage terminal VREF or ground terminal GND. After a period of settling, the analog voltage required for the next conversion step is obtained on the capacitor of CDAC12. When the control clock signal clkc goes low, the comparison of the next bit begins. This process is repeated until all n-bit significant bit signals D[n-1:0] are obtained.

[0087] The synchronous control logic circuit allocates an equal amount of time (Tclkin) to each conversion step. Furthermore, the comparison time tcmp for each bit and the setup time tsetup for CDAC 12 are both fixed at (1 / 2)Tclkin. Due to this fixed time allocation, if comparator 13 receives the comparison result signal comp but the synchronous bit control signal has not yet arrived, the ADC will not perform any operations, resulting in wasted timing.

[0088] like Figure 7 As shown in the figure, it is the circuit structure diagram of the asynchronous control logic circuit. Figure 8 As shown in the figure, it is the working sequence diagram of the asynchronous control logic circuit. Figures 1 to 3 、 Figures 6 and 7 For example, the input clock signal clkin of the asynchronous SAR ADC has the same frequency as the sampling signal clks, that is, clkin=clks. When the sampling signal clks is at a high level, the signal of the first input signal terminal VinP and the signal of the second input signal terminal VinN are sampled to the CDAC 12 through the sampling switch 11; when the sampling signal clks jumps to a low level, the sampling process ends, the control clock signal clkc jumps to a low level, the comparator 13 is enabled, and the signal size of the input terminal is judged to obtain the comparison result signal comp. When the difference between the first voltage output signal Vop and the second voltage output signal Von of the latch circuit 131 in the comparator 13 is large, the comparison completion signal valid output by the exclusive OR gate 133 jumps to a high level, indicating that the comparison is completed. The control logic circuit 14 generates the asynchronous bit control signal clk according to the rising edge of the comparison completion signal valid. <n-1>, asynchronous bit control signal clk <n-1>The comparison result signal comp is sampled on the rising edge of , and the most significant bit signal D[n-1], the most significant bit signal D[n-1] and the asynchronous bit control signal clk are obtained. <n-1>Output to CDAC1 2 to control the next bit setup process. After the comparison completion signal valid jumps to a high level, the control clock signal clkc also jumps to a high level, and the comparator 13 enters the reset state. The first voltage output signal Vop and the second voltage output signal Von are reset to a high level, eventually causing the comparison completion signal valid to return to a low level. The control clock signal clkc also jumps to a low level, and the next comparison begins. This process repeats until all n-bit valid bit signals D[n-1:0] are obtained.

[0089] The asynchronous control logic circuit adaptively adjusts the conversion time allocated to each bit based on the time it takes for comparator 13 to complete the comparison, avoiding timing waste in the synchronous control logic circuit. However, when the difference between the first voltage signal vip and the second voltage signal vin input to comparator 13 is small, comparator 13 cannot quickly determine the signal magnitude relationship. The output voltage difference of latch 131 is small, and the first voltage output signal Vop and the second voltage output signal Von take a long time to separate. This causes the comparison completion signal valid to jump to a high level, resulting in a metastable state. This metastable state prolongs the conversion time for that bit, significantly compressing the subsequent analysis time of the valid bit signal D[n-1:0]. This results in the ADC being unable to obtain all valid bit signals between two samplings, causing serious errors in the entire conversion process.

[0090] For example, Figure 7 The ADC experiences metastability when parsing the valid bit signal D[1]. The comparison time is too long, resulting in insufficient comparison time for the valid bit signal D[0] (the least significant bit, LSB). Consequently, the LSB is not obtained, and the conversion is incomplete. If the metastability occurs at a higher bit, more serious consequences may result. Furthermore, in the asynchronous control logic circuit, although the comparison time tcmp for each bit is adaptively adjusted, the CDAC setup time tsetup for each bit remains fixed, and the problem of incomplete CDAC setup still exists.

[0091] In summary, existing SAR ADC structures, whether synchronous or asynchronous control logic circuits, have certain defects in timing control: in synchronous logic control circuits, the fixed time allocation will lead to timing waste, thereby reducing ADC performance; in asynchronous logic control circuits, the existence of metastable phenomena will cause errors in the conversion process.

[0092] Based on this, the present invention provides a control logic circuit to solve the problems of timing waste and conversion process errors in the control logic circuit of SAR ADC; in addition, it can also optimize the CDAC establishment process, thereby improving the overall performance of SAR ADC.

[0093] The solution provided by the embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0094] Specifically, an embodiment of the present invention provides a control logic circuit, such as Figure 9 As shown in Figure 2, it is applied to SAR ADC, including:

[0095] The signal generating module 141 is used to convert the input clock signal clkin to obtain the sampling signal clks, the control clock signal clkc and the synchronous clock signal f <n-1:0>;

[0096] The HLU module 142 is configured to generate a signal based on the comparison completion signal valid or the synchronization clock signal f <n-1:0>, generate the target bit control signal clk <n-1:0>;

[0097] Signal conversion module 143, used to control the signal clk at the target position <n-1:0>Under the control of , the comparison result signal comp is sampled to obtain the valid bit signal D[n-1:0];

[0098] The comparison completion signal valid and the comparison result signal comp are generated by the comparator in the SAR ADC. The control logic circuit disclosed in the present invention, the signal generating module 141 is used to convert the input clock signal clkin to obtain the sampling signal clks, the control clock signal clkc and the synchronization clock signal f respectively. <n-1:0>HLU module 142 is used based on the comparison completion signal valid or synchronous clock signal f generated by the comparator 13 <n-1:0>, generate the target bit control signal clk <n-1:0>; The signal conversion module 143 is used to control the signal clk at the target position <n-1:0>Under the control of , the comparison result signal comp generated by the comparator 13 is sampled to obtain the valid bit signal D[n-1:0]. <n-1:0>The comparison completion signal valid or the synchronous clock signal f <n-1:0>Control generated, that is, when the comparison completion signal valid arrives first, the target bit control signal clk <n-1:0>The comparison completion signal valid is generated, which can reduce the timing waste in the synchronous control logic circuit. <n-1:0>When it arrives first, the target bit control signal clk <n-1:0>By the synchronous clock signal f <n-1:0>Generate, thereby can reduce the probability of error in the conversion process when the comparison completion signal valid cannot be output.

[0099] It should be noted that the control logic circuit provided in the embodiment of the present invention can be used for the SAR ADC structure with upper plate sampling, and can also be applied to the SAR ADC structure with lower plate sampling, as well as other SAR ADC structures using CDAC. Figure 1 The structure shown, but Figure 1 The structures shown do not constitute limitations of the present invention.

[0100] In an optional embodiment, as Figure 10 As shown, the signal generating module 141 may include a sampling signal generating unit 1411, a control clock signal generating unit 1412 and a multi-level synchronous clock signal generating unit 1413;

[0101] The sampling signal generating unit 1411 is configured to sample the input clock signal clkin based on a preset clock period Tclkin to obtain a sampling signal clks;

[0102] The control clock signal generating unit 1412 is configured to perform a logic operation on the input clock signal clkin and the sampling signal clks to obtain a control clock signal clkc;

[0103] Each stage synchronous clock signal generating unit 1413 is used to output a synchronous clock signal f based on the input clock signal clkin. <n-1:0>.

[0104] In the signal generating module 141 disclosed in the present invention, the sampling signal generating unit 1411 is used to generate the sampling signal clks for controlling the sampling switch 11 to be turned on or off; the control clock signal generating unit 1412 is used to generate the control clock signal clkc for controlling the comparator 13 to be enabled or reset; the synchronous clock signal generating unit 1413 has n stages, where n is a positive integer, and is used to output the synchronous clock signal f <n-1:0>The signal generation module 141 generates various control signals based on the input clock signal clkin, thereby controlling the working state of some circuits.

[0105] like Figure 11 and Figure 14 As shown, the sampling signal generating unit 1411 includes a first NOT gate INV3, a second NOT gate INV4 and k first D flip-flops D11, D12, ..., D1k, where k is a positive integer;

[0106] The input end of the first inverter INV3 is connected to the output end of the last-stage HLU unit 1413 , and the output end of the first inverter INV1 is connected to the D end of the first D flip-flop D11 ;

[0107] The input end of the second inverter INV4 is connected to the Q end of the last first D flip-flop D1k, and the output end of the second inverter INV4 serves as the output end of the sampling signal generating unit 1411, for outputting the sampling signal clks;

[0108] The CLK terminal of each first D flip-flop D11, D12, ..., D1k serves as an input terminal of the sampling signal generating unit 1411, for inputting the input clock signal clkin. The R terminal of each first D flip-flop D11, D12, ..., D1k is connected to the input terminal of the first invertor INV3, and the D terminal of the subsequent first D flip-flop is connected to the Q terminal of the previous first D flip-flop.

[0109] For example, the D terminal of the first D flip-flop D12 is connected to the Q terminal of the first D flip-flop D11 , and the D terminal of the first D flip-flop D13 is connected to the Q terminal of the first D flip-flop D12 .

[0110] The sampling signal generating unit 1411 disclosed in the present invention is used to sample the input clock signal clkin based on a preset clock period Tclkin to obtain a sampling signal clks. The sampling signal clks controls the on or off of the sampling switch 11, thereby controlling whether the circuit performs a sampling operation.

[0111] In an optional embodiment, as Figure 12 and Figure 14 As shown, the control clock signal generating unit 1412 includes a first OR gate OR1;

[0112] A first input terminal of the first OR gate OR1 is used to input the input clock signal clkin, a second input terminal of the first OR gate OR1 is used to input the sampling signal clks, and an output terminal of the first OR gate OR1 is used to output the control clock signal clkc.

[0113] The control clock signal generating unit 1412 disclosed in the present invention is used to perform a logic operation on the input clock signal clkin and the sampling signal clks to obtain the control clock signal clkc. The control clock signal clkc controls the enable or reset of the comparator 13, thereby controlling whether the circuit enters the comparison working state.

[0114] In an optional embodiment, as Figure 13 and Figure 14 As shown, each stage synchronous clock signal generating unit 1413 includes a second D flip-flop D21, D22, ..., D2n;

[0115] The D terminal of the first-stage second D flip-flop D21 is connected to the input terminal of the second inverter INV4, the D terminal of the second D flip-flop of the next stage is connected to the Q terminal of the second D flip-flop of the previous stage, and the Q terminal of the last-stage second D flip-flop D2n is connected to the R terminals of the second D flip-flops D21, D22, ..., D2(n-1) of the other stages and the input terminal of the first inverter INV3. The CLK terminal of the second D flip-flops D21, D22, ..., D2n of each stage is used to input the input clock signal clkin, and the Q terminal of the second D flip-flops D21, D22, ..., D2n of each stage serves as the output terminal of the synchronization bit controller signal generating unit 1413 of this stage, used to output the synchronization clock signal f of this stage. <n-1:0>.

[0116] The synchronous clock signal generating unit 1413 disclosed in the present invention has n stages, where n is a positive integer, and is used to output a synchronous clock signal f based on the input clock signal clkin. <n-1:0>, synchronous clock signal f <n-1:0>As input to the HLU module 142.

[0117] In an optional embodiment, the HLU module 142 may include an HLU unit 1421 corresponding to the synchronous clock signal generating unit 1413, such as Figure 15 As shown;

[0118] Each level of HLU unit 1421 is used to compare the completion signal valid before the rising edge of the synchronization clock signal f <n-1:0>At the rising edge of , based on the comparison completion signal valid, the target bit control signal clk is generated. <n-1:0>, the rising edge of the comparison completion signal valid is later than the synchronous clock signal f <n-1:0>When the rising edge of the synchronous clock signal f <n-1:0>, generate the target bit control signal clk <n-1:0>.

[0119] The overall working sequence diagram of the control logic circuit 14 disclosed in the present invention is as follows: Figure 16 As shown below, the generation process of the most significant bit signal D[n-1] is taken as an example, combined with Figure 17 , the working principle of the control logic circuit of the present invention is introduced in detail. The input clock signal clkin is a high-frequency clock with a clock period of Tclkin, and k clock periods are used to generate the sampling signal clks. When clks is at a high level, the sampling switch 11 is turned on, and the signal of the first input signal terminal VinP and the signal of the second input signal terminal VinN are sampled onto the CDAC 12; after the sampling signal clks jumps to a low level, the sampling switch 11 is disconnected, the sampling process ends, and the CDAC 12 and the comparator 13 start the conversion process under the action of the control clock signal clkc. When the control clock signal clkc is at a low level, the dynamic comparator 13 is enabled, judges the signal size of the input terminal and obtains the comparison result signal comp, and at the same time, the comparison completion signal valid jumps to a high level. After the comparator 13 has obtained the comparison result signal comp and the comparison completion signal valid and the synchronous clock signal f <n-1>When the rising edge of the comparison completion signal valid does not arrive, the HLU module 142 in the control logic circuit 14 generates the target bit control signal clk according to the rising edge of the comparison completion signal valid. <n-1>, the target bit control signal clk <n-1>The rising edge of the comparison result signal comp is sampled and the most significant bit signal D[n-1] is obtained. At the same time, the target bit control signal clk <n-1>The most significant bit signal D[n-1] is output to CDAC 12, directing the most significant bit capacitor (2^(n-1)C) in CDAC 12 to connect to reference voltage VREF or ground GND. After a period of settling, clkc = clkin = 0, and the next bit comparison begins. This process repeats until all n-bit significant bit signals D[n-1:0] are obtained.

[0120] The HLU module 142 disclosed in the present invention includes n-level HLU units 1421, each level of HLU unit 1421 is used to compare the completion signal valid or the synchronization clock signal f <n-1:0>, generate the target bit control signal clk <n-1:0>Since the target bit control signal clk <n-1:0>The generation of is not just waiting for the synchronous clock signal f <n-1:0>The comparison time tcmp is adaptively adjusted, so as not to waste the timing of the control logic circuit 14, and to allow the CDAC 12 to have more time for signal establishment. Under certain clock frequency constraints, the overall signal-to-noise ratio of the SAR ADC can be improved. On the other hand, the probability of errors in the conversion process caused by the existence of metastable phenomena can be reduced.

[0121] In an optional embodiment, as Figure 18 As shown, each HLU unit 1421 includes a third NOT gate INV5, a second OR gate OR2, a third OR gate OR3 and a third D flip-flop D3;

[0122] An input end of the third NOT gate INV5 is connected to the D ends of the second D flip-flops D21, D22, ..., D2n corresponding to the HLU unit 1421, and an output end of the third NOT gate INV5 is connected to the first input end of the second OR gate OR2;

[0123] A second input terminal of the second OR gate OR2 is connected to the Q terminals of the second D flip-flops D21, D22, ..., D2n and a second input terminal of the third OR gate OR3, and an output terminal of the third OR gate OR3 is connected to the R terminal of the third D flip-flop D3;

[0124] The CLK terminal of the third D flip-flop D3 is used to input the comparison completion signal valid, the D terminal of the third D flip-flop D3 is used to input the power supply voltage VDD, and the Q terminal of the third D flip-flop D3 is connected to the first input terminal of the third OR gate OR3;

[0125] The output terminal of the third OR gate OR3 is used as the output terminal of the HLU unit 1421 to output the target bit control signal clk <n-1:0>.

[0126] The HLU unit 1421 disclosed in the present invention is used to compare the completion signal valid before the rising edge of the synchronization clock signal f <n-1:0>At the rising edge of , based on the comparison completion signal valid, the input signal A and the input signal B are converted into the output signal X, and the output signal X is the target bit control signal clk <n-1:0>; The rising edge of the comparison completion signal valid is later than the synchronous clock signal f <n-1:0>When the rising edge of the synchronous clock signal f <n-1:0>, converting input signal A and input signal B into output signal X, output signal X is the target bit control signal clk <n-1:0>.

[0127] It should be noted that, in order to ensure that the control logic circuit does not have ESD (ElectroStaticDischarge) problems, the third D flip-flop D3 can be connected to the power supply voltage terminal VDD through a resistor or a tieh unit that provides a stable high level.

[0128] In an optional embodiment, the HLU unit may further include a delay device, such as Figure 19 As shown;

[0129] The input of the delay device is used to input the synchronous clock signal f <n-1:0>, the output end of the delay device delay is connected to the input end of the third inverter INV5.

[0130] Next, the second highest target bit control signal clk <n-2>As an example, according to the generation process of Figures 20 to 22 , the working principle of the HLU unit 1421 of the present invention is introduced in detail.

[0131] When the comparator 13 quickly completes the comparison, the working sequence of the HLU unit 1421 is as follows: Figure 20 As shown. The input signal of HLU unit A=f <n-1>and B = f <n-2>Both are synchronous clock signals. The conversion process of the bit occurs between the two rising edges of the input signal A and the input signal B (A=1 and B=0). In this interval, when the control signal clkc is high, the reference voltage VREF drives the CDAC to establish. When the control signal clkc is low, the comparator 13 performs comparison. Between the rising edge of the delayed signal A_delay of the input signal A and the rising edge of the input signal B, that is, when the output terminal Y=B+(A_delay)' of the second OR gate OR2 is low, the third D flip-flop can sample the rising edge of the comparison completion signal valid, causing the output terminal Q to jump to a high level, and the output signal X=B+Q also jumps to a high level, thus generating the target bit control signal clk. <n-2>Outside this period, the output terminal Y of the second OR gate OR2 is always at a high level, resetting the third D flip-flop to a low level, ensuring that the rising edges of the comparison completion signal valid generated in each bit comparison process will not affect each other.

[0132] When the voltage difference of the comparator 13 input is very small and causes metastable state, the comparison completion signal valid has no rising edge during the conversion process of the bit, and its timing is as follows: Figure 21 At this time, the HLU unit 1421 is based on the synchronous clock signal B=f <n-2>To generate the target bit control signal clk <n-2>, that is, when the comparator 13 is in metastable state, clk <n-2> ＝f <n-2>Therefore, the control logic circuit of the present invention can terminate the comparison process and obtain the comparison result in time when the rising edge of the synchronous clock has not arrived, thereby avoiding errors that may be caused by metastable states.

[0133] The delay in the HLU unit 1421 is to prevent the previous comparison completion signal valid from affecting the next conversion. Figure 22 As shown, after the control clock signal clkc is at a high level, it takes a period of time (trst_delay) to reset the first voltage output signal Vop and the second voltage output signal Von at the output of the comparator to a high level. During this period, due to the extremely fast operation speed of the SAR ADC, the comparison completion signal valid may still generate a rising edge. If there is no delay in the HLU unit 1421, then the output terminal Y of the second OR gate OR2 is Y=B+A'. In the interval of Y=0, the third D flip-flop may mistakenly sample the rising edge of the comparison completion signal valid of the previous bit, thereby generating an erroneous target bit control signal clk <n-2>The target bit control signal clk <n-2>The rising edge of tdelay will sample the previous bit's comparison result, causing conversion errors. Adding a delay after the input signal A can shorten the interval where the output of the second OR gate OR2, Y = 0. As long as the set delay time tdelay is greater than trst_delay, the influence of the previous bit's comparison completion signal valid on the current bit can be avoided.

[0134] The delay device disclosed in the present invention is used to prevent the third D flip-flop from incorrectly sampling the rising edge of the comparison completion signal valid of the previous bit, thereby generating an erroneous target bit control signal clk. <n-2>Although the HLU unit 1421 disclosed in the present invention can also use the conditions of A=1, B=0, and clkc=0 to more accurately define Y=0, i.e., the valid interval of the valid rising edge, considering that the control clock signal clkc is a high-frequency clock, complex logic will increase the parasitic load of the control clock signal clkc, thereby affecting the normal operation of the comparator 13. In contrast, the delay circuit has a simple structure, is easy to implement, and has no impact on other circuits.

[0135] In an optional embodiment, as Figure 23 As shown, the signal conversion module 143 includes fourth D flip-flops D41, D42, ..., D4n corresponding to the HLU units 1421 one by one;

[0136] For each group of HLU units 1421 and fourth D flip-flops D41, D42, ..., D4n, the CLK terminals of the fourth D flip-flops D41, D42, ..., D4n are connected to the output terminals of the HLU units 1421, the D terminals of the fourth D flip-flops D41, D42, ..., D4n are used to input the comparison result signal comp, and the Q terminals of the fourth D flip-flops D41, D42, ..., D4n are used to output the valid bit signal D[n-1:0].

[0137] The signal conversion module 143 disclosed in the present invention is used to control the signal clk at the target position. <n-1:0>Under the control of , the comparison result signal comp is sampled to obtain the valid bit signal D[n-1:0].

[0138] It should be noted that the CDAC switch logic in the figure is a CDAC logic switch, corresponding to Figure 1 and Figure 2 The three-choice switch in .

[0139] Based on the same concept, embodiments of the present invention further provide a SAR ADC, comprising a sampling switch, a CDAC, a comparator, and any of the aforementioned control logic circuits. The principles underlying the problem solved by this SAR ADC are similar to those of the aforementioned control logic circuits. Therefore, the implementation of this SAR ADC can refer to the implementation of the aforementioned control logic circuits, and any repetitions will be omitted here.

[0140] Specifically, the sampling switch is used to open or close the path between the signal input terminal and the CDAC sampling terminal under the control of the sampling signal output by the control logic circuit;

[0141] CDAC, used to sample the input signal when the sampling switch is closed;

[0142] The comparator is used to compare the first voltage signal and the second voltage signal maintained on the CDAC under the control of the control clock signal output by the logic control circuit, and output a comparison completion signal and a comparison result signal.

[0143] Those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations. < / n-2>

Claims

1. A control logic circuit, characterized in that: The circuit is applied to a successive approximation register (SAR) analog-to-digital converter (ADC), and includes: The signal generating module is used to convert the input clock signal to obtain the sampling signal, the control clock signal and the synchronization clock signal; The HLU module includes multiple stages of HLU units; each stage of the HLU unit is configured to generate a target bit control signal based on the comparison completion signal when the rising edge of the comparison completion signal is earlier than the rising edge of the synchronization clock signal, and to generate a target bit control signal based on the synchronization clock signal when the rising edge of the comparison completion signal is later than the rising edge of the synchronization clock signal; a signal conversion module, configured to sample the comparison result signal under the control of the target bit control signal to obtain a valid bit signal; wherein the comparison completion signal and the comparison result signal are generated by a comparator in the successive approximation register (SAR) analog-to-digital converter (ADC); Each of the HLU units includes a third NOT gate, a second OR gate, a third OR gate, and a third D flip-flop; An input end of the first NOT gate is connected to a D end of a second D flip-flop corresponding to the HLU unit, and an output end of the first NOT gate is connected to a first input end of the second OR gate; The second input terminal of the second OR gate is connected to the Q terminal of the second D flip-flop and the second input terminal of the third OR gate, and the output terminal of the third OR gate is connected to the R terminal of the third D flip-flop; The CLK terminal of the third D flip-flop is used to input the comparison completion signal, the D terminal of the third D flip-flop is used to input the power supply voltage, and the Q terminal of the third D flip-flop is connected to the first input terminal of the third OR gate; The output end of the third OR gate serves as the output end of the HLU unit, and is used to output the target bit control signal.

2. The circuit according to claim 1, wherein The signal generating module includes a sampling signal generating unit, a control clock signal generating unit and a multi-level synchronous clock signal generating unit, wherein the multi-level synchronous clock signal generating unit corresponds to the multi-level HLU unit in a one-to-one manner; The sampling signal generating unit is configured to sample the input clock signal based on a preset clock cycle to obtain the sampling signal; The control clock signal generating unit is configured to perform a logic operation on the input clock signal and the sampling signal to obtain the control clock signal; The synchronous clock signal generating unit at each stage is used to output the synchronous clock signal based on the input clock signal.

3. The circuit according to claim 2, wherein: The sampling signal generating unit includes a first NOT gate, a second NOT gate and k first D flip-flops, where k is a positive integer; The input end of the first NOT gate is connected to the output end of the HLU unit of the last stage, and the output end of the first NOT gate is connected to the D end of the first D flip-flop; The input end of the second NOT gate is connected to the Q end of the last of the first D flip-flops, and the output end of the second NOT gate serves as the output end of the sampling signal generating unit, for outputting the sampling signal; The CLK terminal of each first D flip-flop serves as the input terminal of the sampling signal generating unit, and is used to input the input clock signal. The R terminal of each first D flip-flop is connected to the input terminal of the first NOT gate, and the D terminal of the subsequent first D flip-flop is connected to the Q terminal of the previous first D flip-flop.

4. The circuit according to any one of claims 2 to 3, wherein: The control clock signal generating unit includes a first OR gate; The first input end of the first OR gate is used to input the input clock signal, the second input end of the first OR gate is used to input the sampling signal, and the output end of the first OR gate is used to output the control clock signal.

5. The circuit according to claim 3, wherein: Each stage of the synchronous clock signal generating unit includes a second D flip-flop; The D terminal of the second D flip-flop of the first stage is connected to the input terminal of the second NOT gate, the D terminal of the second D flip-flop of the next stage is connected to the Q terminal of the second D flip-flop of the previous stage, and the Q terminal of the second D flip-flop of the last stage is connected to the R terminal of the second D flip-flop of the other stage and the input terminal of the first NOT gate. The CLK terminal of the second D flip-flop of each stage is used to input the input clock signal, and the Q terminal of the second D flip-flop of each stage serves as the output terminal of the synchronous clock signal generating unit of this stage, and is used to output the synchronous clock signal of this stage.

6. The circuit according to claim 1, wherein The HLU unit also includes a delay device; The input end of the delay device is used to input the synchronous clock signal, and the output end of the delay device is connected to the input end of the third NOT gate.

7. The circuit according to claim 6, wherein: The signal conversion module includes a fourth D flip-flop corresponding one-to-one to the HLU unit; For each group of HLU units and fourth D flip-flops, the CLK terminal of the fourth D flip-flop is connected to the output terminal of the HLU unit, the D terminal of the fourth D flip-flop is used to input the comparison result signal, and the Q terminal of the fourth D flip-flop is used to output the valid bit signal.

8. A successive approximation register (SAR) analog-to-digital converter (ADC), characterized in that: The device comprises a sampling switch, a capacitive digital-to-analog converter (CDAC), a comparator, and a control logic circuit as claimed in any one of claims 1 to 7, wherein: The sampling switch is used to open or close the path between the signal input terminal and the CDAC sampling terminal under the control of the sampling signal output by the control logic circuit; The CDAC is used to sample the input signal when the sampling switch is closed; The comparator is used to compare the first voltage signal and the second voltage signal maintained on the CDAC under the control of the control clock signal output by the control logic circuit, and output a comparison completion signal and a comparison result signal.

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