High-speed settling time adaptive circuit and data transmission method for mobile industry processor interface

Abstract

The present invention provides a high-speed stable time adaptive circuit and a data transmission method for a mobile industry processor interface. The method includes a detection controller for receiving a local clock signal, using the local clock signal to synchronize and detect a low-frequency signal, and sending a high-speed start signal when a high-speed entry timing signal is detected; and also includes a high-speed stable timer for receiving a local clock signal and a high-speed start signal sent by the detection controller; the high-speed stable timer includes a fixed timer and a floating timer, and the fixed timer uses the local clock signal to perform fixed time timing after receiving the high-speed start signal, and outputs a timing start signal to the floating timer after the fixed time arrives, and the floating timer uses the high-speed clock signal to perform timing after receiving the timing start signal. The present invention also provides a data transmission method for a mobile industry processor interface implemented by the above circuit. The present invention can improve the accuracy of high-speed stable time timing.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, in particular to a high-speed stable time adaptive circuit and a data transmission method of a mobile industry processor interface implemented by using the circuit. Background Art

[0002] Most existing electronic devices are equipped with cameras, displays, etc., which need to be connected to processors for data exchange. At present, electronic devices widely use the Mobile Industry Processor Interface (MIPI) as the Camera Serial Interface (CSI) and Display Serial Interface (DSI).

[0003] The Mobile Industry Processor Interface is a development standard initiated by the MIPI Alliance for mobile application processors. The standard defines that each interface consists of a pair of clock signal lines and several pairs of data signal lines. Each pair of signal lines is divided into two signal lines, Dp and Dn, and has two electrical transmission modes: low-frequency mode (LP, Low Power) and high-speed mode (HS, High-Speed).

[0004] See also Figure 1 The transmitting end 10 of the mobile industry processor interface is provided with a low-frequency signal sending module and a differential signal transmitter (HS-TX) 11, and the receiving end 20 is provided with a low-frequency signal receiving module and a terminal resistor 21 (RT), and a differential signal receiver (HS-RX) 22. The differential signal receiver 22 can receive the high-speed signal sent by the differential signal transmitter 11.

[0005] The circuit states supported by the mobile industry processor interface include 6 states, namely LP-00, LP-01, LP-10, LP-11, HS-0 and HS-1, as shown in Table 1. In high-speed mode, the receiver uses the high-speed clock (HS-0 and HS-1 are interleaved) on the clock signal line to sample the high-speed data on the data signal line with the same rate to achieve high-speed data reception.

[0006] Table 1 Six circuit states of mobile industry processor interface

[0007]

[0008]

[0009] from Figure 1It can be seen that both the transmitting end 10 and the receiving end 20 have corresponding low-frequency circuits and high-speed circuits, and are provided with corresponding enabling switches. When the mobile industry processor interface is used for data transmission, a low-frequency mode is entered when a small amount of control data or no data is transmitted (such as the image blanking period), and the high-speed circuit is turned off to save power consumption; when a large amount of data transmission is required, the high-speed circuit is turned on and the high-speed mode is entered to achieve high-speed data transmission.

[0010] See also Figure 2 In the low-frequency mode, the signal level amplitude transmitted by the transmitter 10 is relatively large, for example, the highest level can reach 1.2V. In the high-speed mode, a differential signal is used for signal transmission between the transmitter 10 and the receiver 20, and the difference between the high and low levels of the signal is only 200mV.

[0011] See also Figure 3 Before entering the high-speed mode, the transmitter 10 first sends a preset high-speed entry timing signal through a low-frequency circuit. Usually, the high-speed entry timing signal includes three signals, LP-11, LP-01, and LP-00, in order to inform the receiver 20 that it is about to enter the high-speed mode. Then, after the transmitter 10 sends the HS-0 signal again for a period of time, the clock signal line will output a high-speed clock signal, and the data signal line will first send the synchronization sequence of the high-speed mode (usually 00011101) before starting to transmit valid data bit by bit.

[0012] In high-speed mode, the low-frequency circuits are kept in the LP-00 state. When exiting the high-speed mode, the clock signal line and the data signal line will maintain the Trail state of HS-0 or HS-1 for a period of time. The level in this state is opposite to the level signal in the high-speed state before entering the Trail state, and then switch to the LP-11 state to end the high-speed transmission. To ensure that the data of the data signal line can be fully sampled, the clock signal line must enter the high-speed mode before the data signal line and exit the high-speed transmission mode later than the data signal line, ensuring that the data signal line always has the corresponding high-speed clock signal hs_clock when transmitting data at high speed.

[0013] like Figure 1As shown, the receiving end 20 is provided with a terminal resistor 21 and a differential signal receiver 22, and is also provided with two corresponding enable switches. When the low-frequency circuit of the receiving end 20 receives the high-speed entry timing signal sent by the transmitting end 10, the corresponding enable switch is turned on, and the terminal resistor 21 and the differential signal receiver 22 are turned on. Then, the high-speed data output by the differential signal receiver of the data signal line is sampled using the clock signal line that has entered the high-speed mode and the high-speed clock signal hs_clock output by the differential signal receiver 22 circuit. The subsequent circuit will perform sequence detection on the data output by the differential signal receiver 22. When the synchronization sequence is detected, the data received after the synchronization sequence can be locked, and the data after the synchronization sequence can be determined to be the valid data actually transmitted.

[0014] However, in the actual circuit, the receiving end 20 generates certain circuit noise when the terminal resistor 21 and the differential signal receiver 22 are turned on, resulting in that the signal output by the differential signal transmitter 11 of the transmitting end 10 cannot be stably received by the differential signal receiver 22 at the initial stage. In addition, if the differential signal receiver 22 is turned on in the LP-00 stage instead of the HS-0 stage, since there is no voltage difference between the input signals Dp and Dn, the output signal cannot be determined to be 0 or 1. During this period, the high-speed data value received is uncontrollable, which may eventually result in the 00011101 sequence being received in advance before the real synchronization sequence arrives. This sequence is actually generated by circuit noise, which in turn causes errors in the received data.

[0015] Therefore, in order to ensure the accuracy of data reception, the MIPI protocol stipulates various circuit timing parameters when the interface enters the high-speed mode from the low-frequency mode. It is necessary to ignore the data value output by the differential signal receiver 22 before the high-speed stabilization time (HS Settle Time) to prevent sampling of circuit noise. The analog circuit (including the terminal resistor 21 and the differential signal receiver 22) must also be stable before the high-speed stabilization time. Therefore, the timing requirements are as follows: Figure 4 And as shown in Table 2 below.

[0016] Table 2 MIPI receiver timing parameters

[0017]

[0018] Among them, UI is Unit Interval, that is, the high-speed data transmission period. For example, if the data transmission rate of the data signal line is 1Gbps, the high-speed data transmission period is 1ns (nanosecond). Under different transmission rates, the value range of THS-SETTLE is different, which also causes the receiving end 20 to adjust THS-SETTLE according to the actual high-speed data transmission period in order to correctly receive the high-speed transmission data.

[0019] In Table 2, TD-TERM-EN indicates that the low-frequency circuit at the receiving end must open the terminal resistor 21 and the differential signal receiver 22 within a certain period of time after detecting the LP-00 signal. The purpose is to ensure that the receiving end 20 is stable before THS-SETTLE (that is, the high-speed stabilization time). The receiving end 20 must Figure 4 After THS-SETTLE in the differential signal receiver 22, the synchronization sequence detection is started for the high-speed data output, to ensure that the subsequent circuit detects the correct synchronization sequence and then receives the real valid data.

[0020] As for the realization of high-speed stabilization time, the common practice at present is to design the high-speed stabilization time into a register-configurable timing circuit in the circuit of the receiving end 20, and configure the timing circuit count value of the receiving end 20 through software in combination with the time parameters of the transmitting end 10 and the corresponding high-speed data transmission rate when using it, so as to realize the adaptation of the high-speed stabilization time. This practice is to configure the register by application software to adapt the high-speed stabilization time, but this solution leads to the fact that there is no way to realize the seamless switching of the high-speed stabilization time when the interface device of the mobile industry processor changes or the high-speed data transmission rate changes. It is necessary to stop the data transmission, reconfigure the high-speed stabilization time of the receiving end, and restart it to realize normal data transmission, which affects the convenience of use.

[0021] Another existing solution is to use a higher-frequency local clock signal to measure the high-speed data transmission cycle, and then combine it with the MIPI protocol timing parameter requirements to further use the circuit to calculate the high-speed stabilization time. However, the value of the high-speed data transmission cycle detected by this solution has certain errors and delays. The higher-frequency local clock signal used for the high-speed data transmission cycle detection circuit will also introduce an additional clock cycle detection circuit, which increases the circuit area and power consumption of the electronic device. If the MIPI high-speed data transmission cycle is below 0.5ns, a higher-frequency local clock signal of at least 2GHz is required to measure the high-speed data transmission cycle, resulting in high production costs for the electronic equipment. Summary of the invention

[0022] The first object of the present invention is to provide a high-speed settling time adaptive circuit which has a simple structure and can be flexibly adapted to calculate the high-speed settling time.

[0023] The second object of the present invention is to provide a data transmission method for a mobile industry processor interface that implements the above-mentioned high-speed stabilization time adaptive circuit.

[0024] To achieve the first purpose of the present invention, the high-speed stable time adaptive circuit provided by the present invention includes a detection controller, which is used to receive a local clock signal, and use the local clock signal to synchronize and detect the low-frequency signal, and send a high-speed start signal when a high-speed entry timing signal is detected; it also includes a high-speed stable timer, which receives the local clock signal and receives the high-speed start signal sent by the detection controller; wherein the high-speed stable timer includes a fixed timer and a floating timer, after receiving the high-speed start signal, the fixed timer applies the local clock signal to perform fixed time timing, and after the fixed time is reached, outputs a timing start signal to the floating timer, and after receiving the timing start signal, the floating timer applies the high-speed clock signal to perform timing.

[0025] It can be seen from the above scheme that by setting a fixed timer and a floating timer to calculate the fixed time and the floating time respectively, the timing of the high-speed stable time can be simplified, and the floating time is timed using a high-speed clock signal, which can ensure the accuracy of the floating time timing. Even if the high-speed data transmission rate changes, since the high-speed clock signal also changes synchronously, the floating time calculated by the floating timer also changes accordingly, and can adapt to different high-speed data transmission rates.

[0026] In addition, since the hardware circuit only has a fixed timer and a floating timer, the circuit area is not large and the power consumption is small, which will not lead to a significant increase in the production cost of the circuit and is conducive to the miniaturization of electronic equipment.

[0027] A preferred solution is that the floating timer is also used to output a conversion enable signal to the serial-to-parallel conversion module after the floating time is reached.

[0028] It can be seen that the serial-to-parallel conversion module is only started after the floating timer ends, and the serial-to-parallel conversion of the data is performed, avoiding the problem of performing the serial-to-parallel conversion of the data too early and resulting in the conversion of invalid data.

[0029] A further solution is that the floating time measured by the floating timer is an even multiple of the high-speed data transmission cycle.

[0030] This is beneficial to the timing of the floating timer and the hardware circuit design of the floating timer is simpler.

[0031] A further solution is that the floating timer includes at least one trigger, each trigger receives a high-speed clock signal, and a signal reset terminal of the trigger receives a timing start signal.

[0032] It can be seen that the trigger is triggered by a high-speed clock signal. Every time a rising edge of the high-speed clock signal is received, a trigger will be triggered, thereby achieving the purpose of delaying by an integer multiple of the high-speed clock cycle.

[0033] A further solution is that the number of triggers is more than two, and the multiple triggers are cascaded in sequence, and the trigger of the previous stage outputs a status signal to the trigger of the next stage.

[0034] It can be seen that by cascading multiple triggers, the delay calculation of the floating time being an integer multiple of the high-speed data transmission cycle (an even multiple of the high-speed data transmission cycle) is realized, and the circuit structure of the floating time timer is very simple, which reduces the production cost of the high-speed stable time adaptive circuit.

[0035] A further solution is that the state output terminal of the last-stage trigger outputs a conversion enable signal.

[0036] In this way, when the last level trigger is triggered, the floating timer immediately outputs a conversion enable signal, so that the serial-to-parallel conversion module is turned on and performs serial-to-parallel conversion on the received data.

[0037] To achieve the above-mentioned second purpose, the data transmission method of the mobile industry processor interface provided by the present invention includes a transmitting end sending a low-frequency signal to a receiving end, and the receiving end uses a local clock signal to synchronize and detect the low-frequency signal, and sends a high-speed start signal when a high-speed entry timing signal is detected; the receiving end is provided with a high-speed stable timer, which performs timing after receiving the high-speed start signal; wherein the high-speed stable timer includes a fixed timer and a floating timer, and the fixed timer applies the local clock signal to perform fixed-time timing after receiving the high-speed start signal, and outputs a timing start signal to the floating timer after the fixed time arrives, and the floating timer applies the high-speed clock signal to perform timing after receiving the timing start signal; the floating timer outputs a conversion enable signal to the serial-to-parallel conversion module after the floating time arrives, and the receiving end receives the high-speed data and applies the serial-to-parallel conversion module to perform serial-to-parallel conversion on the high-speed data.

[0038] Furthermore, when the detection controller at the receiving end detects the LP-11 signal, that is, the interface signal is switched to the low-frequency mode, the high-speed stabilization timer and each start signal are directly turned off.

[0039] A preferred solution is that the floating time measured by the floating timer is an even multiple of the high-speed data transmission period.

[0040] A further solution is that the high-speed start signal includes a terminal resistance start signal and a differential signal receiver start signal.

[0041] It can be seen that after the receiving end detects the high-speed entry timing signal, it immediately enables the terminal resistor and the differential signal receiver, so that the differential signal receiver is ready to start receiving the preset synchronization sequence signal.

[0042] A further solution is that the differential signal receiver start signal is output to the differential signal receiver; after the differential signal receiver receives the differential signal receiver start signal, the differential signal receiver outputs data to the serial-to-parallel conversion module.

[0043] It can be seen that the differential signal receiver can output data to the serial-to-parallel conversion module in a timely manner. The serial-to-parallel conversion module performs the serial-to-parallel conversion operation only after receiving the conversion enable signal, thereby avoiding serial-to-parallel conversion of invalid data. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a structural block diagram of the existing mobile industry processor interface.

[0045] Figure 2 It is the electrical transmission characteristic diagram of the existing mobile industry processor interface.

[0046] Figure 3 It is a schematic diagram of the conversion between low-frequency mode and high-speed mode of the existing mobile industry processor interface.

[0047] Figure 4 It is a signal timing diagram of the receiving end of the existing mobile industry processor interface.

[0048] Figure 5 It is a structural block diagram of a mobile industry processor interface transmitter and receiver using an embodiment of the high-speed stabilization time adaptive circuit of the present invention.

[0049] Figure 6 It is a structural block diagram of an embodiment of a high-speed stabilization time adaptive circuit of the present invention.

[0050] Figure 7 It is a structural block diagram of a floating timer in an embodiment of a high-speed stable time adaptive circuit of the present invention.

[0051] Figure 8 It is a flow chart of an embodiment of a data transmission method of a mobile industry processor interface of the present invention.

[0052] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0053] The high-speed stabilization time adaptive circuit of the present invention is applied to an electronic device. Preferably, the electronic device is an electronic device provided with a mobile industry processor interface. The data transmission method of the mobile industry processor interface of the present invention applies the above-mentioned high-speed stabilization time adaptive circuit to perform adaptive adjustment of the high-speed stabilization time. Therefore, the present invention is based on the time parameters specified by the MIPI protocol, and realizes automatic hardware adaptation of the high-speed stabilization time through circuit design. Regardless of the scenario where the high-speed data transmission rate is fixed or the high-speed data transmission rate changes, the hardware can be automatically adapted to normally receive high-speed data without the need for multiple software configurations.

[0054] High-speed settling time adaptive circuit embodiment:

[0055] See also Figure 5 For the clock signal line, the mobile industry processor interface circuit includes a transmitter 30 and a receiver 40. The transmitter 30 sends a clock signal to the receiver 40, and the receiver 40 sends the received clock signal to the detection controller (LP Detect&HS Control) 51. The detection controller 51 can detect low-frequency signals and control high-speed signals. The detection controller 51 can receive local clock signals and use local clock signals to detect low-frequency signals, thereby generating control signals for high-speed circuits. Because the physical layer does not generate any clock signals before the clock signal line starts to transmit the clock signal, it is necessary to detect the low-frequency signal, so a local clock signal needs to be provided to meet the detection requirements for the low-frequency signal.

[0056] A differential signal transmitter 31 for the clock signal is provided at the transmitting end 30, and a terminal resistor 41 and a differential signal receiver 42 for the clock signal are provided at the receiving end 40. The detection controller 51 can generate a high-speed start signal, such as a terminal resistor start signal term_en and a differential signal receiver start signal hs_en, which are respectively used to control the start and shut down of the terminal resistor 41 and the differential signal receiver 42. For example, when the detection controller 51 receives a high-speed entry timing signal, that is, after detecting the LP-11, LP-01, and LP-00 sequences in sequence, the terminal resistor start signal term_en and the differential signal receiver start signal hs_en will be enabled to turn on the terminal resistor 41 and the differential signal receiver 42, and the differential signal receiver 42 will convert the received high-speed differential clock signal into a single-ended high-speed clock signal hs-clock.

[0057] For the data signal line, the mobile industry processor interface circuit includes a transmitter 30 and a receiver 40. The transmitter 30 sends a data signal to the receiver 40. In addition, the low-frequency data signal received by the receiver 40 is sent to a high-speed stable time adaptive circuit. The high-speed stable time adaptive circuit includes a detection controller 52 and a high-speed stable timer 60. The detection controller 52 can receive the low-frequency signal and detect the low-frequency signal. At the same time, the detection controller 52 can also receive a local clock signal and use the local clock signal to detect the low-frequency signal.

[0058] A differential signal transmitter 32 for data signals is provided at the transmitting end 30, and a terminal resistor 43 and a differential signal receiver 44 for data signals are provided at the receiving end 40. The detection controller 52 can enable the terminal resistor start signal term_en and the differential signal receiver start signal hs_en, which are respectively used to control the start and shut down of the terminal resistor 43 and the differential signal receiver 44. For example, when the detection controller 52 receives a high-speed entry timing signal, that is, after detecting the LP-11, LP-01, and LP-00 sequences in sequence, the terminal resistor start signal term_en and the differential signal receiver start signal hs_en will be enabled to turn on the terminal resistor 43 and the differential signal receiver 44.

[0059] For the data signal, the receiving end 40 is also provided with a serial-to-parallel conversion module 55, which is used to sample and convert the serial high-speed data signal into 8-bit parallel data, and the high-speed stable timer 60 is used to output a conversion enable signal s2p_en to the serial-to-parallel conversion module 55. In addition, the serial-to-parallel conversion module 55 also receives the high-speed clock signal hs-clock generated by the differential signal receiver 42, and uses the high-speed clock signal hs-clock as a reference clock signal to sample the data. The high-speed data signal output by the differential signal receiver 44 is collected by the serial-to-parallel conversion module 55 and serial-to-parallel converted, and the converted parallel data is output to the data processor 56.

[0060] Generally, both the differential signal receiver start signal hs_en and the conversion enable signal s2p_en can be used to realize the timing of the high-speed stabilization time, that is, before the high-speed stabilization time arrives, the differential signal receiver start signal hs_en and the conversion enable signal s2p_en can be kept off to realize the function of ignoring the high-speed data at this time. However, considering that the differential signal receiver 44 also needs a certain time to stabilize after being turned on, the present embodiment uses the conversion enable signal s2p_en to realize the timing of the high-speed stabilization time.

[0061] Since the terminal resistor 43 and the differential signal receiver 44 will generate circuit noise for a period of time before they can stabilize after being turned on, and if the differential signal receiver 44 is turned on in the LP-00 stage, the output level signal is uncertain, therefore, the conversion enable signal s2p_en needs to be kept in a closed state during this period, that is, the serial-to-parallel conversion module 55 is not started, and the output value of the differential signal receiver 44 can be ignored. To ensure that the high-speed stable time adaptive circuit is in a stable state and no noise is generated when the conversion enable signal s2p_en is enabled, the terminal resistor start signal term_en and the differential signal receiver start signal hs_en can be immediately set after detecting the high-speed entry timing signal, that is, the sequence of LP-11, LP-01, and LP-00, to ensure that there is enough time for stabilization, and at the same time start the high-speed stable timer 60 to start timing. After the high-speed stable timer 60 ends, the conversion enable signal s2p_en is set, and the serial-to-parallel conversion module 55 starts and starts to receive high-speed data from the differential signal receiver 44.

[0062] According to the protocol of the mobile industry processor interface, it is sufficient to ensure that the THS-SETTLE value is within the specified range of [85ns+6*UI, 145ns+10*UI]. Therefore, when designing the timing of the high-speed stabilization time, the high-speed stabilization time is divided into two parts, fixed time and floating time, and the timing is performed separately. For details, see Figure 6 A fixed timer (Constant Timer) 61 and a floating timer (UI Timer) 62 are set in the high-speed stable timer 60, wherein the fixed timer 61 is responsible for the timing of the constant time part, that is, the part from 85ns to 145ns, and a local clock signal with a fixed frequency can be used as a reference clock signal for timing; the floating timer 62 is responsible for the timing of the variable part, that is, the part from 6*UI to 10*UI, and the high-speed clock signal hs_clock output by the clock signal line can be directly used as a reference clock signal for timing.

[0063] In the high-speed stable time adaptive circuit, the detection controller 52 uses the local clock signal to first synchronize and detect the low-frequency signal of the receiving end 40. When the high-speed entry timing signal, i.e., the sequence of LP-11, LP-01, and LP-00, is detected, it indicates that the transmitting end 30 needs to start data transmission in high-speed mode. At this time, the high-speed timing start signal hs_sta needs to be set. When the LP-11 signal is subsequently detected, it indicates exiting the high-speed state and immediately canceling the high-speed timing start signal hs_sta. In this embodiment, the terminal resistance start signal term_en and the differential signal receiver start signal hs_en can be directly associated with the high-speed timing start signal hs_sta and perform switch control operations on the terminal resistance 43 and the differential signal receiver 44. Therefore, the high-speed timing start signal hs_sta issued by the detection controller 52 can also be directly used as the terminal resistance start signal term_en and the differential signal receiver start signal hs_en.

[0064] After detecting the high-speed entry timing signal, the detection controller 52 outputs a high-speed timing start signal hs_sta to the fixed timer 61. The fixed timer 61 immediately starts the timing operation. The timing value of the fixed timer 61 is between 85ns and 145ns. The minimum timing unit is the local clock signal period received by the fixed timer. For example, if the frequency of the local clock signal is 200MHz, the minimum timing unit is 5ns.

[0065] When the fixed time is reached, the fixed timer 61 sets the timing start signal const_timeout output to the floating timer 62, and clears the fixed timer when the high-speed timing start signal hs_sta is canceled, and the start signal const_timeout of the floating timer is canceled synchronously, the floating counter is reset, and the output conversion enable signal s2p_en is cleared. The timing formula of the fixed timer 61 is as follows:

[0066]

[0067] In formula 1, T constant is a fixed time timing value, the value range is [85ns, 145ns], T LP-dly It represents the delay of the low frequency signal from the transmitting end 30 to the receiving end 40, T local-period is the clock period of the local clock signal, M LP-sync-cycle Indicates the number of beats of the low-frequency signal synchronized with the local clock signal in the detection controller 52. If two beats are synchronized, then M LP-sync-cycle The value of is 2, and the final calculated N constant-cycle That is, it is the timing cycle value that the fixed timer 61 needs to achieve using the local clock signal.

[0068] Because the mobile industry processor interface protocol stipulates that the minimum width of the low-frequency signal is 50ns, in order to ensure that the detection controller 52 can accurately sample the low-frequency signal, the frequency of the local clock signal must be higher than 1s / 50ns, that is, higher than 20MHz. LP-dly 1ns, T local-period is 5ns (i.e., the frequency of the local clock signal is 200MHz), and the number of beats that the detection controller 52 uses the local clock signal to synchronize the low-frequency signal is 2 beats. According to formula 1, N can be calculated. constant-cycle The value of is [14.8, 28.8]. Considering the circuit design error, this embodiment takes the middle integer value 21 as the counting period of the fixed timer 61 to obtain the safest and most stable result.

[0069] After the fixed timer 61 completes the timing of the fixed time, the generated timing start signal const_timeout will be set and drive the floating timer 62 to start timing. The reference clock signal used by the floating timer 62 is the high-speed clock signal hs_clock. Each cycle of the high-speed clock signal hs_clock corresponds to 2*UI, so the timing of 6*UI to 10*UI can directly correspond to the rising edge counting of the high-speed clock signal hs-clock for 3 to 5 cycles. Considering that the local clock signal and the high-speed clock signal hs-clock are asynchronous clock signals, the high-speed clock signal hs_clock counts 3 to 5 cycles. It can be directly realized by using the high-speed clock signal hs_clock to sample the timing start signal const_timeout driven by the local clock signal for 4 beats, and the last beat is directly output as the conversion enable signal s2p_en. In addition to playing the role of delaying the floating timing, it can also realize the synchronous processing of asynchronous signals.

[0070] See also Figure 7 , four triggers 66, 67, 68, 69 are arranged in the floating timer 62, and the four triggers 66, 67, 68, 69 are cascaded in sequence, and the trigger of the previous stage outputs a state signal to the trigger of the next stage, for example, the state output terminal Q of the first stage trigger 66 outputs a state signal to the data input terminal D of the second stage trigger 67. The clock signal terminal CK of each trigger 66, 67, 68, 69 receives a high-speed clock signal, and the data input terminal D of the first stage trigger 66 is fixedly connected to a high level. The state output terminal, i.e., the Q terminal, of the last stage trigger 69 outputs a conversion enable signal s2p_en.

[0071] In addition, the signal reset terminals RN of the four triggers 66, 67, 68, and 69 all receive the timing start signal const_timeout. When the fixed timer 61 sets the timing start signal const_timeout, the four triggers 66, 67, 68, and 69 are triggered and start working. Figure 7 It can be seen that when the first rising edge of the high-speed clock signal arrives, the first-stage trigger 66 outputs a high-level signal. At this time, the input terminal D of the second-stage trigger 67 receives a high-level signal. When the second rising edge of the high-speed clock signal arrives, the second-stage trigger 67 outputs a high-level signal, and so on. When the fourth rising edge of the high-speed clock signal arrives, the fourth-stage trigger 69 outputs a high-level signal, that is, the conversion enable signal s2p_en is set, thereby completing the timing of the entire high-speed stabilization time and starting to receive high-speed data.

[0072] When the timing start signal const_timeout is cancelled, that is, the timing start signal const_timeout is reset, the signals output by the four triggers 66, 67, 68, and 69 are all reset. Therefore, the conversion enable signal s2p_en is also reset, exiting the high-speed state, stopping the reception of high-speed data, and waiting for the next low-speed mode switch.

[0073] It can be seen that the present embodiment uses a high-speed stable timer 60 to calculate the high-speed stable time. The high-speed stable timer 60 uses a fixed timer 61 and a floating timer 62 to respectively calculate the fixed time and the floating time. Since the floating timer 62 uses a high-speed clock signal as a timing reference, the floating timer 62 can accurately calculate the floating time for different high-speed data transmission cycles. Therefore, the present embodiment can adapt to the high-speed stable time calculation under a variety of different high-speed data transmission cycles.

[0074] In this way, this embodiment does not need to introduce an additional higher frequency local clock signal to first calculate the current high-speed data transmission period, thereby reducing the power consumption of the high-speed settling time adaptive circuit and reducing the production cost of the electronic device.

[0075] Data transmission method embodiment of mobile industry processor interface:

[0076] Combine the following Figure 8 The data transmission method of the mobile industry processor interface is introduced. First, step S11 is executed, in the low frequency mode, the transmitting end sends a low frequency signal to the receiving end. At this time, the receiving end synchronizes and detects the received low frequency signal, that is, step S12 is executed.

[0077] When the transmitting end enters the high-frequency mode, a high-speed entry timing signal is sent. Therefore, the receiving end needs to execute step S13 to determine whether the high-speed entry timing signal is received. If not, continue to monitor. If the high-speed entry timing signal is received, step S14 is executed, and the detection controller of the receiving end sends a high-speed start signal, that is, the terminal resistance start signal term_en and the differential signal receiver start signal hs_en are enabled to turn on the terminal resistors 41, 43 and the differential signal receivers 42, 44. At this time, the differential signal receiver 42 outputs a high-speed clock signal to the serial-to-parallel conversion module 55. However, since the conversion enable signal s2p_en is not set, the serial-to-parallel conversion module 55 does not perform serial-to-parallel conversion on the received data.

[0078] When the detection controller 52 detects the high-speed entry timing signal, that is, the sequence of LP-11, LP-01, and LP-00, it indicates that the transmitter needs to start data transmission in high-speed mode. At this time, the high-speed timing start signal hs_sta is set, and the fixed timer 61 executes step S15 to start timing the fixed time, and executes step S16 to determine whether the fixed time has been reached. If not, continue to wait. If the fixed time has been reached, execute step S17, and the fixed timer outputs a timing start signal to the floating timer.

[0079] After receiving the timing start signal, the floating timer starts timing the floating time, applies the high-speed clock signal as the reference clock signal for timing, and executes step S18 to determine whether the floating time has been reached. If reached, step S19 is executed, and the floating timer outputs a conversion enable signal to the serial-to-parallel conversion module. The serial-to-parallel conversion module executes step S20 to perform serial-to-parallel conversion on the received high-speed data signal and output it to the subsequent data processor.

[0080] This embodiment uses a fixed timer and a floating timer to respectively measure the fixed time and the floating time, which can improve the timing flexibility and accuracy of the high-speed stable time.

[0081] Finally, it should be emphasized that the present invention is not limited to the above-mentioned embodiments. For example, changes in the timing value of a fixed time, or changes in the internal structure of a floating timer, etc., should also be included in the scope of protection of the claims of the present invention.

Claims

1. A high-speed settling time adaptive circuit, include: A detection controller receives a local clock signal, uses the local clock signal to synchronize and detect the low-frequency signal, and sends a high-speed start signal when a high-speed entry timing signal is detected; Features: A high-speed stable timer receives the local clock signal and receives the high-speed start signal sent by the detection controller; Among them, the high-speed stable timer includes a fixed timer and a floating timer. After receiving the high-speed start signal, the fixed timer applies the local clock signal to perform fixed time timing, and after the fixed time is reached, outputs a timing start signal to the floating timer. After receiving the timing start signal, the floating timer applies the high-speed clock signal to perform timing.

2. The high-speed settling time adaptive circuit according to claim 1, Features: The floating timer is also used to output a conversion enable signal to the serial-to-parallel conversion module after the floating time is reached.

3. The high-speed settling time adaptive circuit according to claim 2, Features: The floating time counted by the floating timer is an even multiple of the high-speed data transmission period.

4. The high-speed settling time adaptive circuit according to claim 3, Features: The floating timer includes at least one trigger, each of the triggers receives the high-speed clock signal, and a signal reset terminal of the trigger receives the timing start signal.

5. The high-speed settling time adaptive circuit according to claim 4, Features: The number of the triggers is more than two, and the multiple triggers are cascaded in sequence, and the trigger of the previous stage outputs a state signal to the trigger of the next stage.

6. The high-speed settling time adaptive circuit according to claim 5, Features: The state output terminal of the trigger at the last stage outputs the conversion enable signal.

7. A data transmission method for a mobile industry processor interface, include: The transmitter sends a low-frequency signal to the receiver; Features: The receiving end synchronizes and detects the low-frequency signal using a local clock signal, and sends a high-speed start signal when a high-speed entry timing signal is detected; The receiving end is provided with a high-speed stable timer, which starts timing after receiving the high-speed start signal; The high-speed stable timer includes a fixed timer and a floating timer. After receiving the high-speed start signal, the fixed timer uses the local clock signal to count the fixed time, and after the fixed time arrives, the floating timer outputs a timing start signal. After receiving the timing start signal, the floating timer uses the high-speed clock signal to count. The floating timer outputs a conversion enable signal to the serial-to-parallel conversion module after the floating time is reached. The receiving end receives the high-speed data and applies the serial-to-parallel conversion module to perform serial-to-parallel conversion on the high-speed data.

8. The data transmission method of the mobile industry processor interface according to claim 7, Features: The floating time counted by the floating timer is an even multiple of the high-speed data transmission period.

9. The data transmission method of the mobile industry processor interface according to claim 7 or 8, Features: The high-speed start signal includes a terminal resistance start signal and a differential signal receiver start signal.

10. The data transmission method of the mobile industry processor interface according to claim 9, Features: The differential signal receiver starts outputting a signal to the differential signal receiver; After receiving the differential signal receiver start signal, the differential signal receiver outputs data to the serial-to-parallel conversion module.

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