Potential control circuit, driving circuit and image sensor

Abstract

The present invention provides a potential control circuit, including a voltage dividing unit, a comparator, an oscillator and a charge pump, which monitors the size of the power supply voltage in real time. If the power supply voltage becomes higher, the charge pump works, and the reset voltage is pumped up by the charge pump. If the power supply voltage becomes lower, the charge pump stops working, and the reset voltage slowly decreases due to the presence of a large holding capacitor at the output end of the charge pump, so that the reset voltage can follow the change of the working voltage, thereby avoiding the problem of image smear and small signal nonlinearity. The present invention also provides a driving circuit and an image sensor.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a potential control circuit, a drive circuit and an image sensor. Background Art

[0002] CMOS image sensors (CIS) have been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. With the increasing requirements of various applications, the quality of CIS images is becoming more and more important, and the most important factor affecting image quality is pixel characteristics. The pixel unit needs to be within a specific operating voltage range under certain timing control to achieve optimal performance, including noise and dynamic range. For example, the voltage of the reset operation should be greater than a certain value of the pixel supply voltage to ensure that the pixel does not have ghosting or small signal conversion nonlinear problems. However, during the actual operation of CIS, the power supply voltage of the pixel will change, so that the reset operation voltage cannot be guaranteed to be greater than a certain value of the pixel supply voltage, resulting in the above defects and affecting the image effect.

[0003] Therefore, it is necessary to provide a new potential control circuit, a driving circuit and an image sensor to solve the above problems existing in the prior art. Summary of the invention

[0004] The object of the present invention is to provide a potential control circuit, a driving circuit and an image sensor to avoid image smear and small signal nonlinearity problems.

[0005] To achieve the above-mentioned purpose, the potential control circuit of the present invention includes a voltage divider unit, a comparator, an oscillator and a charge pump. The first input end of the voltage divider unit is connected to the working voltage, the first output end of the voltage divider unit is connected to the non-phase input end of the comparator, and is used to input the working voltage into the non-phase input end of the comparator after voltage division, the second input end of the voltage divider unit is connected to the output end of the charge pump, the second output end of the voltage divider unit is connected to the inverting input end of the comparator, and is used to input the output voltage of the charge pump into the inverting input end of the comparator after voltage division, the output end of the comparator is connected to the input end of the oscillator, the output end of the oscillator is connected to the input end of the charge pump, and the output end of the charge pump is used to output a reset voltage.

[0006] The potential control circuit has the beneficial effect that: the first input end of the voltage divider unit is connected to the working voltage, the first output end of the voltage divider unit is connected to the non-inverting input end of the comparator, and is used to divide the working voltage and input it into the non-inverting input end of the comparator; the second input end of the voltage divider unit is connected to the output end of the charge pump, the second output end of the voltage divider unit is connected to the inverting input end of the comparator, and is used to divide the output voltage of the charge pump and input it into the inverting input end of the comparator; the output end of the comparator is connected to the input end of the oscillator, the output end of the oscillator is connected to the input end of the charge pump, the output end of the charge pump is used to output a reset voltage, and the size of the power supply voltage is monitored in real time. If the power supply voltage becomes higher and the charge pump works, the reset voltage is pumped up by the charge pump; if the power supply voltage becomes lower and the charge pump stops working, the reset voltage slowly decreases due to the presence of a large holding capacitor at the output end of the charge pump, so that the reset voltage can follow the change of the working voltage, thereby avoiding the problem of image smear and small signal nonlinearity.

[0007] Optionally, the voltage divider unit includes a first voltage divider sub-unit, the first voltage divider sub-unit includes a first resistor and a second resistor, one end of the first resistor is connected to the working voltage, the other end of the first resistor is connected to one end of the second resistor and the non-phase input end of the comparator, and the other end of the second resistor is grounded.

[0008] Optionally, the voltage divider unit also includes a second voltage divider sub-unit, the second voltage divider sub-unit includes a third resistor and a fourth resistor, one end of the third resistor is connected to the output end of the charge pump, the other end of the third resistor is connected to one end of the fourth resistor and the inverting input end of the comparator, and the other end of the fourth resistor is grounded.

[0009] The present invention also provides a driving circuit, comprising:

[0010] The potential control circuit;

[0011] The row decoding driving unit is connected to the potential control circuit.

[0012] The beneficial effect of the driving circuit is that the driving circuit includes the potential control circuit and the row decoding driving unit, and can avoid image smear and small signal nonlinearity problems.

[0013] The present invention also provides an image sensor, comprising:

[0014] Pixel array unit, used to output pixel signals after light sensing

[0015] The driving circuit is connected to the pixel array unit and is used to drive the pixel array unit;

[0016] A reference unit, for generating a ramp signal;

[0017] an analog-to-digital conversion unit, connected to the reference unit and the pixel array unit, and configured to convert the pixel signal into a digital signal and output the digital signal;

[0018] An output signal processing unit connected to the analog-to-digital conversion unit to convert the digital signal into an image and output the image;

[0019] A timing control unit is connected to the driving circuit, the reference unit, the analog-to-digital conversion unit and the output signal processing unit, and is used to send a clock signal to the driving circuit, the reference unit, the analog-to-digital conversion unit and the output signal processing unit.

[0020] The image sensor has the beneficial effect that: the image sensor includes the driving circuit, which can avoid image smear and small signal nonlinearity problems.

[0021] Optionally, the pixel array unit includes at least one pixel unit, and the pixel unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a photosensitive diode. The drain of the first NMOS tube and the drain of the second NMOS tube are connected to an operating voltage, the gate of the first NMOS tube is used to receive a first control signal, the source of the first NMOS tube is connected to the drain of the third NMOS tube and the gate of the second NMOS tube, the gate of the third NMOS tube is used to receive a second control signal, the source of the third NMOS tube is connected to the cathode of the photosensitive diode, the anode of the photosensitive diode is grounded, the source of the second NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is used to receive the third control signal, and the source of the fourth NMOS tube is connected to the analog-to-digital conversion unit to transmit the pixel signal to the analog-to-digital conversion unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a circuit diagram of an image sensor of the present invention;

[0023] Figure 2 is a circuit diagram of a pixel unit in some embodiments of the present invention;

[0024] Figure 3 is a timing diagram of a pixel unit in some embodiments of the present invention;

[0025] Figure 4 is a schematic diagram of a potential control circuit in some embodiments of the present invention;

[0026] Figure 5FIG. 1 is a reset voltage following timing diagram in some embodiments of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0028] In view of the problems existing in the prior art, an embodiment of the present invention provides an image sensor. Figure 1 The image sensor 100 includes a pixel array unit 101, a driving circuit 102, a reference unit 103, an analog-to-digital conversion unit 104, an output signal processing unit 105, and a timing control unit 106.

[0029] Reference Figure 1 The pixel array unit 101 is used to output pixel signals after light exposure; the driving circuit 102 is connected to the pixel array unit 101 to drive the pixel array unit 101; the reference unit 103 is used to generate a ramp signal; the analog-to-digital conversion unit 104 is connected to the reference unit 103 and the pixel array unit 101 to convert the pixel signal into a digital signal and output it; the output signal processing unit 105 is connected to the analog-to-digital conversion unit 104 to convert the digital signal into an image and output it; the timing control unit 106 is connected to the driving circuit 102, the reference unit 103, the analog-to-digital conversion unit 104 and the output signal processing unit 105 to send a clock signal to the driving circuit 102, the reference unit 103, the analog-to-digital conversion unit 104 and the output signal processing unit 105. The pixel array unit 101 includes at least one pixel unit 1011, and the analog-to-digital conversion unit 104 includes at least one analog-to-digital converter (ADC) 1041. The reference unit 103 , the output signal processing unit 105 , and the timing control unit 106 are all well-known technologies in the art and will not be described in detail herein.

[0030] Figure 2 FIG. 1 is a circuit diagram of a pixel unit in some embodiments of the present invention. Figure 2 The pixel unit 1011 includes a first NMOS tube 10111, a second NMOS tube 10112, a third NMOS tube 10113, a fourth NMOS tube 10114 and a photosensitive diode 10115. The drain of the first NMOS tube 10111 and the drain of the second NMOS tube 10112 are connected to the working voltage PIXVDD. The gate of the first NMOS tube 10111 is used to receive the first control signal RX. The source of the first NMOS tube 10111 is connected to the drain of the third NMOS tube 10113 and the gate of the second NMOS tube 10112. The gate of the third NMOS tube 10113 is used to receive the second control signal TX, the source of the third NMOS tube 10113 is connected to the cathode of the photosensitive diode 10115, the anode of the photosensitive diode 10115 is grounded GND, the source of the second NMOS tube 10112 is connected to the drain of the fourth NMOS tube 10114, the gate of the fourth NMOS tube 10114 is used to receive the third control signal SEL, and the source of the fourth NMOS tube 10114 is connected to the analog-to-digital conversion unit (not shown in the figure) to transmit the pixel signal to the analog-to-digital conversion unit. The circuit of the pixel unit is not specifically limited in the present invention, and can be as follows Figure 2 The circuit shown may also be other circuits as long as they can achieve the corresponding functions.

[0031] Reference Figure 2 The connection point between the source of the first NMOS tube 10111, the gate of the second NMOS tube 10112 and the drain of the third NMOS tube 10113 is a floating node FD.

[0032] Figure 3 FIG. 1 is a timing diagram of a pixel unit in some embodiments of the present invention. Figure 2 and Figure 3 , Rst represents the reset phase of the pixel unit 1011; Exp represents the exposure phase of the pixel unit 1011; Read represents the signal reading phase of the pixel unit 1011; SEL represents the third control signal applied to the gate of the fourth NMOS tube; RX represents the first control signal applied to the gate of the first NMOS tube 10111; TX represents the second control signal applied to the gate of the third NMOS tube 10113.

[0033] Reference Figure 2 and Figure 3When the pixel unit is in the reset stage, the third control signal SEL maintains a low level, the first control signal RX maintains a high level, and the second control signal TX changes from a high level to a low level. The first control signal RX and the second control signal TX are both at a high level, the first NMOS tube 10111 and the third NMOS tube 10113 are both turned on, and the potential of the floating node FD is pulled up to the working voltage PIXVDD to complete the reset.

[0034] Reference Figure 2 and Figure 3 , after the first control signal RX and the second control signal TX are both changed from high level to low level, the pixel unit enters the exposure stage from the reset stage, the third control signal SEL maintains a low level, the first control signal RX maintains a low level, and the second control signal TX maintains a low level. The first control signal RX and the second control signal TX are both low levels, the first NMOS tube 10111 and the third NMOS tube 10113 are both turned off, and the photodiode 10115 senses light and generates photoelectrons proportional to the light intensity.

[0035] Reference Figure 2 and Figure 3 , after the third control signal SEL changes from a low level to a high level, the fourth NMOS tube 10114 is turned on, and the pixel unit enters the signal reading stage from the exposure stage. The first control signal RX first changes from a low level to a high level to reset the floating node FD. At this time, the second NMOS tube 10112 is controlled by the potential of the floating node FD, and the first integral potential VRST is output by the source of the fourth NMOS tube 10114, and then the first control signal RX changes from a high level to a low level; the second control signal TX changes from a low level to a high level, and the photoelectrons in the photodiode 10115 are transferred to the floating node FD. At this time, the second NMOS tube 10112 is controlled by the potential of the floating node FD, and the second integral potential VSIG is output by the source of the fourth NMOS tube 10114, and then the second control signal TX changes from a high level to a low level.

[0036] In some embodiments, VRST and VSIG are converted into digital quantities by the analog-to-digital conversion unit and subtracted to obtain the digital quantity actually corresponding to the electrons on the photodiode. If the analog-to-digital conversion unit is 12 bits, the digital quantity of the reference voltage of the analog-to-digital conversion unit is V ’ REF , the output DOUT of the analog-to-digital conversion unit = (VRST-VSIG) × 2 12 / V ’REF .

[0037] In some embodiments, if the first control signal RX is at a high level and the potential is not high enough, the first NMOS tube is not fully turned on, and the potential of the floating node FD is not in a completely linear follow-up relationship with the potential of the gate of the first NMOS tube, which will cause nonlinearity in VRST-VSIG. Especially for small signals, VRST and VSIG are close, and nonlinearity will cause the details of dark scenes in the image to be lost. When shooting moving objects, the signals at different times will be uneven, resulting in a ghosting phenomenon in the image.

[0038] Reference Figure 1 The driving circuit 102 includes a potential control circuit 1021 and a row decoding driving unit 1022, and the potential control circuit 1021 is connected to the row decoding driving unit 1022. The row decoding driving unit 1022 is used to generate a pixel operation timing signal of each row according to the row address information, and then the voltage output by the potential control circuit 1021 drives each pixel unit 1011 in the pixel array unit 101.

[0039] Figure 4 Schematic diagram of potential control circuit in some embodiments of the present invention. Figure 4 The potential control circuit 1021 includes a voltage divider unit 10211, a comparator 10212, an oscillator 10213 and a charge pump 10214. The first input end of the voltage divider unit 10211 is connected to the working voltage PIXVDD, the first output end of the voltage divider unit 10211 is connected to the positive input end of the comparator 10212, and is used to divide the working voltage PIXVDD and input it to the positive input end of the comparator 10212. The second input end of the voltage divider unit 10211 is connected to the positive input end of the comparator 10212. The output end of the charge pump 10214, the second output end of the voltage divider unit 10211 is connected to the inverting input end of the comparator 10212, and is used to divide the output voltage of the charge pump 10214 and input it into the inverting input end of the comparator 10212. The output end of the comparator 10212 is connected to the input end of the oscillator 10213, and the output end of the oscillator 10213 is connected to the input end of the charge pump 10214. The output end of the charge pump 10214 is used to output a reset voltage VRXH.

[0040] Reference Figure 4The voltage divider unit 10211 includes a first voltage divider subunit 102111 and a second voltage divider subunit 102112, the first voltage divider subunit includes a first resistor Rp1 and a second resistor Rp2, one end of the first resistor Rp1 is connected to the working voltage VDD, the other end of the first resistor Rp1 is connected to one end of the second resistor Rp2 and the non-inverting input end of the comparator, the other end of the second resistor Rp2 is grounded GND, the second voltage divider subunit includes a third resistor Rc1 and a fourth resistor Rc2, one end of the third resistor Rc1 is connected to the output end of the charge pump, the other end of the third resistor Rc1 is connected to one end of the fourth resistor Rc2 and the inverting input end of the comparator, and the other end of the fourth resistor Rc2 is grounded GND.

[0041] Reference Figure 4 , the voltage obtained by dividing the working voltage PIXVDD by the first resistor Rp1 and the second resistor Rp2 is VPT, the voltage obtained by dividing the reset voltage VRXH by the third resistor Rc1 and the fourth resistor Rc2 is VCT, the output signal of the comparator is CMO, and the output signal of the oscillator is CLK, wherein,

[0042] VCT=VRXH×Rc2 / (Rc1+Rc2), VPT=PIXVDD×Rp2 / (Rp1+Rp2).

[0043] Reference Figure 4 When the working voltage PIXVDD is higher than the reset voltage VRXH, VPT>VCT, the output signal CMO of the comparator is at a high level, causing the oscillator to start oscillating, and the oscillator outputs a signal CLK to the charge pump. The charge pump works normally to gradually pump up the voltage, thereby causing the reset voltage VRXH output by the charge pump to gradually increase. The increase in VRXH causes VCT to increase proportionally.

[0044] Reference Figure 4 When the working voltage PIXVDD is less than the reset voltage VRXH, VCT>VPT, the output signal CMO of the comparator is at a low level, causing the oscillator to stop working, the oscillator has no clock output, and the charge pump stops working. However, due to the presence of a large holding capacitor at the output end of the charge pump, the reset voltage VRXH begins to slowly decrease until the reset voltage VRXH is lower than the preset value, and the charge pump starts to work again.

[0045] Figure 5 FIG. 1 is a reset voltage following timing diagram in some embodiments of the present invention. Figure 5, the regulation process of the potential control circuit includes Region 1, Region 2, and Region 3. The target potential of the reset voltage VRXH is VRXH_M. In Region 1, when the actual potential of the reset voltage VRXH is less than the preset value VRXH_L, at this time VCT < VPT, the time period from t0 to t1 is the detection and judgment process of the comparator and the establishment process of the charge pump. During this period, the reset voltage VRXH will reach the lowest potential VL. Thereafter, it enters Region 2, and the charge pump will pump up the potential of the reset voltage VRXH. When the actual potential of the reset voltage VRXH is greater than the preset value VRXH_L, at this time VCT > VPT. At the moment t1, the comparator starts to compare and judge. Until the moment t2, the charge pump stops working. The time period from t1 to t2 can be regarded as the delay of the comparator's comparison and judgment. The reset voltage VRXH will reach the highest potential VH. Thereafter, in Region 3, since the charge pump stops working, the reset voltage VRXH will slowly fall back, and at the moment t3, it reaches the lowest potential VL again. Repeating this process, the reset voltage VRXH is always maintained at a certain value higher than the working voltage PIXVDD, thereby avoiding problems such as image smear and small-signal non-linearity.

[0046] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A potential control circuit, characterized in that: It comprises a voltage dividing unit, a comparator, an oscillator and a charge pump, wherein the first input end of the voltage dividing unit is connected to the working voltage, the first output end of the voltage dividing unit is connected to the non-phase input end of the comparator, and is used to input the working voltage into the non-phase input end of the comparator after voltage division, the second input end of the voltage dividing unit is connected to the output end of the charge pump, the second output end of the voltage dividing unit is connected to the inverting input end of the comparator, and is used to input the output voltage of the charge pump into the inverting input end of the comparator after voltage division, the output end of the comparator is connected to the input end of the oscillator, the output end of the oscillator is connected to the input end of the charge pump, and the output end of the charge pump is used to output a reset voltage; Among them, the voltage divider unit includes a first voltage divider sub-unit and a second voltage divider sub-unit; the first voltage divider sub-unit includes a first resistor and a second resistor, one end of the first resistor is connected to the working voltage, the other end of the first resistor is connected to one end of the second resistor and the non-phase input end of the comparator, and the other end of the second resistor is grounded; the second voltage divider sub-unit includes a third resistor and a fourth resistor, one end of the third resistor is connected to the output end of the charge pump, the other end of the third resistor is connected to one end of the fourth resistor and the inverting input end of the comparator, and the other end of the fourth resistor is grounded.

2. A driving circuit, characterized in that: include: The potential control circuit as claimed in claim 1; The row decoding driving unit is connected to the potential control circuit.

3. An image sensor, characterized in that: include: A pixel array unit, used for outputting pixel signals after light sensing; The driving circuit according to claim 2, connected to the pixel array unit, and used to drive the pixel array unit; A reference unit, for generating a ramp signal; an analog-to-digital conversion unit, connected to the reference unit and the pixel array unit, and configured to convert the pixel signal into a digital signal and output the digital signal; An output signal processing unit connected to the analog-to-digital conversion unit to convert the digital signal into an image and output the image; A timing control unit is connected to the driving circuit, the reference unit, the analog-to-digital conversion unit and the output signal processing unit, and is used to send a clock signal to the driving circuit, the reference unit, the analog-to-digital conversion unit and the output signal processing unit.

4. The image sensor according to claim 3, characterized in that: The pixel array unit includes at least one pixel unit, and the pixel unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a photosensitive diode. The drain of the first NMOS tube and the drain of the second NMOS tube are connected to an operating voltage, the gate of the first NMOS tube is used to receive a first control signal, the source of the first NMOS tube is connected to the drain of the third NMOS tube and the gate of the second NMOS tube, the gate of the third NMOS tube is used to receive a second control signal, the source of the third NMOS tube is connected to the cathode of the photosensitive diode, the anode of the photosensitive diode is grounded, the source of the second NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is used to receive a third control signal, and the source of the fourth NMOS tube is connected to the analog-to-digital conversion unit to transmit the pixel signal to the analog-to-digital conversion unit.

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