A floating point ambiguity fixing method, orbit solution method and clock error solution method

Abstract

The embodiment of the present application provides a floating point ambiguity fixing method, an orbit solution method and a clock error solution method to improve the timeliness and accuracy of ambiguity fixation. The floating point ambiguity fixing method includes: obtaining the floating point ambiguity of at least one epoch, and at least one epoch includes a target epoch; iteratively rounding the floating point ambiguity according to an iterative algorithm to obtain the target integer ambiguity of the target epoch; wherein each iterative rounding process includes: rounding the floating point ambiguity with reference to the uncalibrated phase delay UPD as a constraint condition to determine the integer ambiguity; establishing a UPD estimation equation based on the floating point ambiguity and the integer ambiguity obtained in each iteration, calculating the UPD, and determining the solution result of the UPD; performing data verification on the solution result of the UPD, and if the data verification passes, the integer ambiguity corresponding to the solution result of the UPD is used as the target integer ambiguity after the target epoch is fixed.

Description

Technical Field

[0001] The present application relates to the field of wireless communications, and in particular to a floating point ambiguity fixing method, an orbit solving method, and a clock error solving method. Background Art

[0002] Ambiguity fixation is a key step in achieving high-precision processing of phase observations. Correct fixation of integer ambiguities can effectively improve the accuracy of orbit fixation and clock error solution. Therefore, how to achieve correct fixation of ambiguities is a research hotspot in the field of satellite navigation and positioning.

[0003] The prior art proposes a double-difference ambiguity fixation method in orbit fixation and clock error resolution. This method eliminates the initial phase deviation and hardware delay at the receiver and satellite ends respectively through double-difference processing of the satellite and the receiver, and constrains the ambiguity fixation condition to the non-difference observation equation based on the mapping relationship between the double-difference ambiguity and the non-difference ambiguity, and obtains a fixed solution for the parameters, thereby fixing the double-difference ambiguity parameters to integers.

[0004] However, in order to achieve a higher ambiguity fixing rate, the above method needs to sort all possible double-difference ambiguities and search for the easiest independent double-difference ambiguities to fix. Therefore, the double-difference ambiguity fixing method has a complex algorithm, large amount of calculation and is relatively time-consuming, and is not suitable for ambiguity fixing in real-time orbit solution and real-time clock difference solution. Summary of the invention

[0005] The embodiments of the present application provide a floating-point ambiguity fixing method, an orbit solution method and a clock difference solution method, which can be applied to ambiguity fixation in real-time orbit solution and real-time clock difference solution, and improve the timeliness and accuracy of ambiguity fixation.

[0006] In a first aspect, an embodiment of the present application provides a floating point ambiguity fixing method, the method comprising:

[0007] obtaining floating point ambiguities for at least one epoch, the at least one epoch including a target epoch;

[0008] Iteratively round the floating point ambiguity according to the iterative algorithm to obtain the target integer ambiguity of the target epoch;

[0009] Among them, each iterative rounding process includes:

[0010] Taking the reference uncalibrated phase delay UPD as a constraint, the floating point ambiguity is rounded to determine the integer ambiguity, wherein, in the first iteration, the reference UPD is a preset UPD initial value or the UPD determined in the iterative rounding process of the previous target epoch, and in the Nth iteration, the reference UPD is the UPD solved in the N-1th rounding process, and N is an integer greater than or equal to 2;

[0011] According to the floating point ambiguity and the integer ambiguity obtained in each iteration, the UPD estimation equation is established, the UPD is calculated, and the solution of the UPD is determined;

[0012] The UPD solution result is subjected to data verification. If the data verification passes, the integer ambiguity corresponding to the UPD solution result is used as the target integer ambiguity after the target epoch is fixed.

[0013] In a second aspect, an embodiment of the present application provides a trajectory solution method, the method comprising:

[0014] Acquire observation data of at least one epoch, the at least one epoch including a target epoch;

[0015] Preprocess the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filter data, wherein the narrow-lane filter data is used to perform orbit filter resolution on the narrow-lane ambiguity data;

[0016] Based on the widelane floating point ambiguity and the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application, determine the target widelane integer ambiguity corresponding to the target epoch and the solution result of the widelane UPD;

[0017] Determine narrow lane floating point ambiguity based on narrow lane filter data and wide lane integer ambiguity;

[0018] Based on the narrow lane floating point ambiguity and the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application, determine the target narrow lane integer ambiguity corresponding to the target epoch and the solution result of the narrow lane UPD;

[0019] The wide lane floating point ambiguity, target wide lane integer ambiguity, solution results of wide lane UPD, narrow lane floating point ambiguity, target narrow lane integer ambiguity and solution results of narrow lane UPD are used as constraints to constrain the floating point orbit variance and determine the orbit solution result with fixed ambiguity.

[0020] In a third aspect, an embodiment of the present application provides a clock error solution method, the method comprising:

[0021] Acquire observation data of at least one epoch, the at least one epoch including a target epoch;

[0022] Preprocess the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filter data, wherein the narrow-lane filter data is used to perform clock error filtering on the narrow-lane ambiguity data;

[0023] Based on the widelane floating point ambiguity and the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application, determine the target widelane integer ambiguity corresponding to the target epoch and the solution result of the widelane UPD;

[0024] Determine narrow lane floating point ambiguity based on narrow lane filter data and wide lane integer ambiguity;

[0025] Based on the narrow lane floating point ambiguity and the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application, determine the target narrow lane integer ambiguity corresponding to the target epoch and the solution result of the narrow lane UPD;

[0026] The solution results of wide lane floating point ambiguity, target wide lane integer ambiguity, wide lane UPD, narrow lane floating point ambiguity, target narrow lane integer ambiguity and narrow lane UPD are used as constraints to constrain the floating point clock error variance and determine the clock error solution result with fixed ambiguity.

[0027] In a fourth aspect, an embodiment of the present application provides a floating point ambiguity fixing device, the device comprising:

[0028] an acquisition unit, configured to acquire a floating point ambiguity of at least one epoch, the at least one epoch including a target epoch;

[0029] A processing unit, configured to iteratively round the floating point ambiguity according to an iterative algorithm to obtain a target integer ambiguity of a target epoch;

[0030] Among them, each iterative rounding process includes:

[0031] Taking the reference uncalibrated phase delay UPD as a constraint condition, the floating point ambiguity is rounded to determine the integer ambiguity, wherein, in the first iteration process, the reference UPD is a preset UPD initial value or the UPD determined in the iterative rounding process of the previous target epoch, and in the Nth iteration process, the reference UPD is the UPD solved in the N-1th iteration rounding process, and N is an integer greater than or equal to 2;

[0032] According to the floating point ambiguity and the integer ambiguity obtained in each iteration, the UPD estimation equation is established, the UPD is calculated, and the solution of the UPD is determined;

[0033] The UPD solution result is subjected to data verification. If the data verification passes, the integer ambiguity corresponding to the UPD solution result is used as the target integer ambiguity after the target epoch is fixed.

[0034] In a fifth aspect, an embodiment of the present application provides a trajectory solving device, the device comprising:

[0035] an acquisition unit, configured to acquire observation data of at least one epoch, wherein the at least one epoch includes a target epoch;

[0036] An extraction unit is used to pre-process the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filter data, wherein the narrow-lane filter data is used to perform orbit filter resolution on the narrow-lane ambiguity data;

[0037] A first processing unit is configured to determine a solution result of a target widelane integer ambiguity and a widelane UPD corresponding to a target epoch based on the widelane floating point ambiguity and the floating point ambiguity fixing method provided by the first aspect of the embodiment of the present application;

[0038] A determination unit, configured to determine narrow lane floating point ambiguities based on narrow lane filter data and wide lane integer ambiguities;

[0039] A second processing unit is configured to determine a solution result of a target narrow lane integer ambiguity and a narrow lane UPD corresponding to a target epoch based on the narrow lane floating point ambiguity and the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application;

[0040] The solution unit is used to use the solution results of wide lane floating point ambiguity, target wide lane integer ambiguity, wide lane UPD, narrow lane floating point ambiguity, target narrow lane integer ambiguity and narrow lane UPD as constraints, constrain the floating point orbit variance, and determine the orbit solution result with fixed ambiguity.

[0041] In a sixth aspect, an embodiment of the present application provides a clock error solving device, the device comprising:

[0042] an acquisition unit, configured to acquire observation data of at least one epoch, wherein the at least one epoch includes a target epoch;

[0043] An extraction unit is used to pre-process the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filter data, wherein the narrow-lane filter data is used to perform clock error filtering on the narrow-lane ambiguity data;

[0044] A first processing unit is configured to determine a solution result of a target widelane integer ambiguity and a widelane UPD corresponding to a target epoch based on the widelane floating point ambiguity and the floating point ambiguity fixing method provided by the first aspect of the embodiment of the present application;

[0045] A determination unit, configured to determine narrow lane floating point ambiguities based on narrow lane filter data and wide lane integer ambiguities;

[0046] A second processing unit is configured to determine a solution result of a target narrow lane integer ambiguity and a narrow lane UPD corresponding to a target epoch based on the narrow lane floating point ambiguity and the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application;

[0047] The solving unit is used to use the solution results of wide lane floating point ambiguity, target wide lane integer ambiguity, wide lane UPD, narrow lane floating point ambiguity, target narrow lane integer ambiguity and narrow lane UPD as constraints, constrain the floating point clock error variance, and determine the clock error solution result with fixed ambiguity.

[0048] In a seventh aspect, an embodiment of the present application provides an electronic device, the device comprising:

[0049] A processor, and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application, the orbit solution method provided in the second aspect, and the clock error solution method provided in the third aspect.

[0050] In an eighth aspect, an embodiment of the present application provides a computer storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the floating-point ambiguity fixing method provided in the first aspect of the embodiment of the present application, the orbit solution method provided in the second aspect, and the clock error solution method provided in the third aspect are implemented.

[0051] The floating-point ambiguity fixing method, orbit solution method and clock error solution method provided in the embodiments of the present application first obtain the floating-point ambiguity of at least one epoch, wherein the at least one epoch includes the target epoch, and then the floating-point ambiguity is iteratively rounded according to the iterative algorithm to obtain the target integer ambiguity of the target epoch. In the process of iterative rounding of the floating-point ambiguity, a UPD estimation equation is established to determine the solution result of the UPD, and the floating-point ambiguity is rounded based on this as a constraint condition to determine the integer ambiguity. Compared with the prior art, the present application realizes real-time fixation of the floating-point ambiguity through the above-mentioned iterative algorithm, and improves the timeliness and accuracy of the floating-point ambiguity fixation. At the same time, since the ambiguity data targeted by the above-mentioned iterative algorithm is the floating-point ambiguity of at least one epoch with the target epoch as the calculation unit, compared with the prior art, the present application can also reduce the amount of calculation and calculation time. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0053] Figure 1 A flowchart of a floating point ambiguity fixing method provided in an embodiment of the present application;

[0054] Figure 2 A schematic flow chart of another floating point ambiguity fixing method provided in an embodiment of the present application;

[0055] Figure 3 A schematic diagram of a flow chart of a trajectory solution method provided in an embodiment of the present application;

[0056] Figure 4A schematic diagram of the structure of a track solving device provided in an embodiment of the present application;

[0057] Figure 5 A flowchart of a clock error calculation method provided in an embodiment of the present application;

[0058] Figure 6 A schematic diagram of the structure of a clock error solving device provided in an embodiment of the present application;

[0059] Figure 7 A schematic diagram of the structure of a floating point ambiguity fixing device provided in an embodiment of the present application;

[0060] Figure 8 A schematic diagram of the structure of another trajectory solving device provided in an embodiment of the present application;

[0061] Fig. 9 A schematic diagram of the structure of another clock error solving device provided in an embodiment of the present application;

[0062] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0063] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0064] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0065] Correctly fixing floating-point ambiguities is a key step in high-precision positioning of satellite observation data. Correctly fixing floating-point ambiguities can effectively improve the accuracy of orbit fixation and clock error solution, and is currently a research hotspot in the field of satellite navigation and positioning.

[0066] In the floating point ambiguity fixed solution, the traditional undifferenced floating point ambiguity adopts real number solution, but this method has many disadvantages. First, the low-precision pseudorange cannot effectively constrain the phase observation value, and the ambiguity estimate determined by fixing the ambiguity is difficult to converge in a short time; secondly, the slow satellite space geometry changes lead to a strong correlation between the floating point ambiguity parameters and the position parameters, and the two cannot be accurately separated in a short time. The unseparated position parameters will have an error effect on the floating point ambiguity fixed solution. Therefore, the positioning accuracy of the undifferenced floating point ambiguity solution is not high and requires a long convergence time.

[0067] Since the floating-point ambiguity parameters of the directly solved non-differenced observations contain the initial phase deviations of the satellite and receiver ends and the signal hardware delay, they no longer have integer characteristics. Orbit solution and clock error solution are generally performed using non-difference methods, which require the estimation of a large number of floating-point ambiguity parameters, and the floating-point ambiguity parameters are estimated as real numbers, and then the floating-point ambiguity parameters have integer characteristics. Therefore, correctly fixing the floating-point ambiguity parameters to the corresponding integer ambiguities can improve the accuracy of real-time orbit fixation and clock error estimation.

[0068] In the prior art, a double-difference ambiguity fixation method is proposed in real-time orbit fixation and clock error estimation. This method uses double-difference processing between satellites and receivers to eliminate the initial phase bias and hardware delay at the receiver and satellite ends respectively, so as to fix the double-difference ambiguity parameters. Through the mapping relationship between the double-difference ambiguity and the non-difference ambiguity, the ambiguity fixation condition is constrained to the non-difference observation equation, thereby obtaining a fixed solution for the parameters.

[0069] In the above method, according to the mapping relationship between double-difference ambiguity and non-difference ambiguity, the resolution of integer ambiguity is based on the estimation of uncalibrated phase delay UPD (Uncalibrated Phase Delay). UPD estimation is performed by post-segmented batch processing and forecasting methods, in which wide-lane UPD estimates one value per day and narrow-lane UPD estimates one value per arc segment.

[0070] In order to achieve a higher ambiguity fixation rate, the above double-difference ambiguity fixation method needs to sort all possible double-difference ambiguities and search for the easiest independent double-difference ambiguities to fix. Therefore, the double-difference ambiguity fixation method has a complex algorithm, large amount of calculation and is relatively time-consuming, and is not suitable for ambiguity fixation in real-time orbit fixation and real-time clock difference solution.

[0071] Based on this, the embodiment of the present application provides a floating point ambiguity fixing method, an orbit solving method and a clock error solving method, which iteratively rounds the floating point ambiguity at the target epoch according to the iterative algorithm, realizes the real-time fixing of the floating point ambiguity, and improves the timeliness and accuracy of the floating point ambiguity fixing. At the same time, since the floating point ambiguity of the target epoch is fixed, the amount of calculation in the floating point ambiguity fixing process is reduced, saving calculation time and calculation cost.

[0072] like Figure 1 As shown, an embodiment of the present application provides a floating point ambiguity fixing method, the method comprising:

[0073] S101, obtaining a floating-point ambiguity of at least one epoch, wherein the at least one epoch includes a target epoch.

[0074] In some embodiments, each epoch has its corresponding receiver, each receiver is used to receive data from at least one satellite at a preset fixed frequency, and the data received by multiple receivers corresponding to multiple epochs form observation data, and the floating-point ambiguity is determined based on the above observation data.

[0075] In some embodiments, the float ambiguity fixing method may be applicable to widelane float ambiguities and / or narrowlane float ambiguities.

[0076] It should be noted that the wide lane floating point ambiguity is determined based on the smoothing result of the observation data; while the narrow lane floating point ambiguity is determined by performing orbit solution or clock difference solution on the ambiguity data. Specifically, the observation data is first filtered and solved through orbit filtering or clock difference filtering, and then the narrow lane floating point ambiguity is determined by combining the wide lane integer ambiguity after the wide lane floating point ambiguity is fixed.

[0077] In addition, in the floating-point ambiguity fixing method provided in the embodiment of the present application, the fixed value solution of the floating-point ambiguity is based on the estimation of UPD. In the real-time estimation of UPD provided in the embodiment of the present application, compared with the segmented batch UPD estimation method in the prior art, the amount of observation data that can be used for UPD estimation in the target epoch is relatively small. Due to the shortage of observation data, the fluctuation of observation data will have a great impact on the stability of UPD. Therefore, in the embodiment of the present application, the observation data of at least one epoch including the target epoch is used to perform real-time estimation of UPD, which further improves the accuracy of floating-point ambiguity fixing.

[0078] S102, iteratively rounding the floating point ambiguity according to an iterative algorithm to obtain a target integer ambiguity of the target epoch;

[0079] The iterative rounding process includes:

[0080] Taking the reference uncalibrated phase delay UPD as a constraint, the floating point ambiguity is rounded to determine the integer ambiguity, wherein, in the first iteration, the reference UPD is a preset UPD initial value or the UPD determined in the iterative rounding process of the previous target epoch, and in the Nth iteration, the reference UPD is the UPD solved in the N-1th rounding process, and N is an integer greater than or equal to 2;

[0081] According to the floating point ambiguity and the integer ambiguity obtained in each iteration, the UPD estimation equation is established, the UPD is calculated, and the solution of the UPD is determined;

[0082] The UPD solution result is subjected to data verification. If the data verification passes, the integer ambiguity corresponding to the UPD solution result is used as the target integer ambiguity after the target epoch is fixed.

[0083] The floating-point ambiguity fixing method, orbit solution method and clock error solution method provided in the embodiments of the present application first obtain the floating-point ambiguity of at least one epoch, wherein the at least one epoch includes the target epoch, and then the floating-point ambiguity is iteratively rounded according to the iterative algorithm to obtain the target integer ambiguity of the target epoch. In the process of iterative rounding of the floating-point ambiguity, a UPD estimation equation is established to determine the solution result of the UPD, and the floating-point ambiguity is rounded based on this as a constraint condition to determine the integer ambiguity. Compared with the prior art, the present application realizes real-time fixation of the floating-point ambiguity through the above-mentioned iterative algorithm, and improves the timeliness and accuracy of the floating-point ambiguity fixation. At the same time, since the ambiguity data targeted by the above-mentioned iterative algorithm is the floating-point ambiguity of at least one epoch with the target epoch as the calculation unit, compared with the prior art, the present application can also reduce the amount of calculation and calculation time.

[0084] Furthermore, the floating point ambiguity fixing method provided in the embodiment of the present application uses the observation data of at least one epoch to estimate the UPD in real time, but the observation data of at least one epoch is to make up for the problem of insufficient data volume of the observation data of a single epoch, so it still takes each single epoch as a calculation unit and performs real-time UPD estimation on it. Compared with the segmented batch processing UPD estimation method in the prior art, the timeliness of the UPD estimation is improved, and at the same time, the problem that if the UPD of a certain satellite is not solved in time, the UPD solution value corresponding to the entire arc segment satellite signal composed of multiple epochs will be missing, and the floating point ambiguity of the satellite cannot be fixed.

[0085] In some embodiments, performing data verification on the solution result of the UPD, and if the data verification passes, using the integer ambiguity as the target integer ambiguity after the target epoch is fixed, may include:

[0086] Perform residual check on the UPD solution results according to floating point ambiguity and integer ambiguity to determine the residual value;

[0087] Determine the iteration difference according to the UPD solution results obtained in this iteration and the previous iteration;

[0088] When the residual value is less than the preset residual threshold and the iteration difference is less than the preset iteration difference threshold, the UPD solution result obtained in this iteration is determined as the UPD solution result of the target epoch, and the integer ambiguity obtained in this iteration is used as the target integer ambiguity after the target epoch is fixed.

[0089] Specifically, in the process of iteratively rounding the floating-point ambiguity, it is necessary to perform data verification on the UPD solution result obtained by each iterative calculation. If the data verification passes, the iteration is stopped, otherwise the next iterative calculation is continued until a UPD solution result that passes the data verification is obtained.

[0090] The data check of the UPD solution result can be judged whether it has passed according to at least the following two aspects: first, based on the floating-point ambiguity data obtained from the observation data and the integer ambiguity obtained by the current iterative calculation, the residual check is performed on the UPD solution result to determine the residual value; second, based on the UPD obtained by the current iterative calculation and the UPD obtained by the previous iterative calculation, the iterative difference is determined. When the above residual value and iterative difference both meet the preset requirements, that is, the residual value is less than the preset residual threshold and the iterative difference is less than the preset iterative difference threshold, it is determined that the UPD solution result obtained by the current iterative calculation has passed the data check.

[0091] The floating point ambiguity fixing method provided by the embodiment of the present invention determines whether to stop the iterative algorithm based on the data verification result of the UPD solution result. In each iterative calculation, the accuracy of the UPD solution result is improved by the above data verification. Furthermore, since the UPD solution result is the premise for determining the integer ambiguity, the accuracy of the floating point ambiguity fixing is improved.

[0092] In some embodiments, before obtaining the floating point ambiguity of at least one epoch, the method may further include:

[0093] Data screening is performed on the ambiguity data of at least one epoch, data whose variance in the ambiguity data is greater than a preset variance threshold is filtered out, and a floating point ambiguity is determined.

[0094] Specifically, the ambiguity data is determined by the observation data received by the receiver corresponding to at least one epoch. Since the influence of environmental factors often leads to errors in the ambiguity data, it is necessary to screen the ambiguity data. Specifically, the data greater than the preset error threshold can be eliminated based on the variance information, altitude information and other auxiliary information to ensure that the floating-point ambiguity extracted from the ambiguity data is not affected by the error, thereby improving the accuracy of the floating-point ambiguity fixation.

[0095] In some embodiments, the UPD solution may include satellite UPD and receiver UPD.

[0096] The satellite UPD is obtained based on the floating point ambiguity of at least two epochs in at least one epoch, the at least two epochs include a target epoch, and the receiver UPD is obtained based on the floating point ambiguity of the target epoch.

[0097] In the method of fixing floating-point ambiguities, since the fluctuation of satellite UPD is small and the fluctuation of receiver UPD is large, in the observation data of at least two epochs, the satellite UPD of different epochs can be the same parameter, that is, the satellite UPD of the target epoch can be determined by at least two epoch data, where at least two epochs include the target epoch; the receiver UPD of different epochs is different parameters, that is, the receiver UPD of the target epoch is determined by the target epoch data.

[0098] The floating point ambiguity fixing method of the above embodiment is described in detail below with reference to the accompanying drawings.

[0099] like Figure 2 As shown, the embodiment of the present application provides another floating point ambiguity fixing method, which is applicable to both wide lane floating point ambiguity and narrow lane floating point ambiguity.

[0100] S201, acquiring ambiguity data of at least one epoch, and performing data screening on the ambiguity data to determine a floating point ambiguity of at least one epoch.

[0101] S202, iteratively rounding the floating point ambiguity based on the reference satellite UPD and the reference receiver UPD to determine the integer ambiguity.

[0102] Specifically, during the first iteration, the reference satellite UPD and the reference receiver UPD are preset UPD initial values ​​or UPD determined during the iterative rounding process of the previous target epoch; during the Nth iteration, the reference satellite UPD and the reference receiver UPD are the satellite UPD and receiver UPD solved during the N-1th iterative rounding process, where N is an integer greater than or equal to 2.

[0103] It should be noted that the fixing principle of floating point ambiguity can be explained by the following formulas.

[0104] As shown in Formula 1, the ambiguity data can be represented by a linear combination of wide-lane floating-point ambiguity and narrow-lane floating-point ambiguity:

[0105]

[0106] Among them, f1 and f2 represent the frequencies of the corresponding frequency points of the carrier observation quantity, represents the floating point ionospheric-free ambiguity, λ lc Represents the ionosphere-free combined wavelength. represents the narrow lane floating point ambiguity, λ nl represents the narrow lane wavelength. represents the wide-lane floating-point ambiguity, λ wl Indicates the wide-lane wavelength. In the real-time UPD estimation algorithm, the wide-lane floating-point ambiguity is determined by combining the observation data and smoothing the observation data, and the narrow-lane floating-point ambiguity comes from the orbit solution or clock error solution floating-point ambiguity.

[0107] The combined observation method for the observation data may be the MW (Melbourne, Wubbena) combined observation method, which is not limited in the present invention.

[0108] When the floating point ambiguity is a wide lane floating point ambiguity, the relationship between the wide lane floating point ambiguity, the wide lane integer ambiguity, the wide lane receiver UPD and the wide lane satellite UPD is as shown in Formula 2:

[0109]

[0110] Among them, N wl represents the integer wide-lane ambiguity, d r,wl represents the receiver wide lane UPD, Indicates satellite widelane UPD.

[0111] After fixing the wide lane ambiguity, based on formula 1, the narrow lane floating point ambiguity can be obtained by formula 3:

[0112]

[0113] Therefore, based on the above formula 3, it can be known that the premise for obtaining the narrow lane floating point ambiguity is to first determine the wide lane integer ambiguity, and then combine the clock error filtering or orbit filtering results of the narrow lane floating point ambiguity to determine the narrow lane floating point ambiguity through the above formula 3.

[0114] Similarly to Formula 2, when the floating point ambiguity is a narrow lane floating point ambiguity, the relationship between the wide lane floating point ambiguity, the wide lane integer ambiguity, the wide lane receiver UPD and the wide lane satellite UPD can be expressed by

[0115] Formula 4 gives:

[0116]

[0117] In formula 4, N nl represents the integer narrow lane ambiguity, d r,nl Indicates the receiver narrow lane UPD, Indicates satellite narrow lane UPD.

[0118] S203, according to the integer ambiguity and floating point ambiguity determined in S202, establish satellite UPD and receiver UPD solution equations, and determine the UPD solution result.

[0119] Specifically, when the floating-point ambiguity is a wide-lane floating-point ambiguity, the established UPD solution equation is shown in the above formula 2; when the floating-point ambiguity is a narrow-lane floating-point ambiguity, the established UPD solution equation is shown in the above formula 3.

[0120] S204, determine whether the UPD solution has passed the data verification, and execute S205 if the data verification has passed. Otherwise, use the UPD solution that has not passed the data verification as the reference satellite UPD and the reference receiver UPD, and return to S202 to perform iterative calculation again.

[0121] Specifically, the data check of the UPD solution result can be judged by at least the following two aspects: first, based on the floating-point ambiguity data and the integer ambiguity obtained by the current iterative calculation, the residual check is performed on the UPD solution result to determine the residual value; second, based on the UPD obtained by the current iterative calculation and the UPD obtained by the previous iterative calculation, the iterative difference is determined. When the above residual value and iterative difference both meet the preset requirements, that is, the residual value is less than the preset residual threshold and the iterative difference is less than the preset iterative difference threshold, it is determined that the data check of the UPD solution result obtained by the current iterative calculation has passed.

[0122] S205, determining the solution result of the UPD that passes the data verification as the target UPD, and at the same time, using the integer ambiguity corresponding to the above target UPD as the target integer ambiguity after the target epoch is fixed.

[0123] In the floating-point ambiguity fixing method provided in the embodiment of the present invention, the determination of the integer ambiguity is based on the estimation of UPD. Compared with the piecewise batch UPD estimation method in the prior art, the UPD estimation algorithm realizes real-time estimation of UPD by establishing a UPD estimation equation to perform multiple iterative calculations on UPD, thereby improving the timeliness of UPD estimation. At the same time, it avoids the problem that if the UPD of a certain satellite is not solved in time, the UPD solution value corresponding to the entire arc segment satellite signal composed of multiple epochs will be missing, and the floating-point ambiguity of the satellite cannot be fixed.

[0124] Furthermore, when the target UPD is determined according to the iterative algorithm, the target integer ambiguity is further determined, that is, the above iterative algorithm also realizes the real-time fixation of the floating-point ambiguity, thereby improving the timeliness and accuracy of the floating-point ambiguity fixation. At the same time, since the ambiguity data targeted by the above iterative algorithm is the floating-point ambiguity of at least one epoch with the target epoch as the calculation unit, compared with the prior art, the present application can also reduce the amount of calculation and the calculation time.

[0125] After determining the target integer ambiguity, the target integer ambiguity and the corresponding UPD product can be used to constrain the floating-point clock error equation and the floating-point orbit equation to determine the clock error solution result and the orbit solution result with fixed ambiguity.

[0126] The following is a detailed description of the process of determining the clock error solution results and the orbit solution results in conjunction with the accompanying drawings.

[0127] like Figure 3 As shown, the embodiment of the present application provides a trajectory solution method, comprising the following steps:

[0128] S301, obtaining observation data of at least one epoch, wherein the at least one epoch includes a target epoch.

[0129] In some embodiments, the biggest difference between the real-time UPD estimation process and the traditional piecewise batch UPD estimation is that the observations available for UPD estimation in a single epoch are greatly reduced, and due to the reduction in the observations, the fluctuation of the observations will have a great impact on the stability of UPD. Therefore, in the embodiment of the present application, multi-epoch splicing observation data is used to perform real-time estimation of UPD, that is, the acquired floating-point ambiguity data can be data of at least one epoch to increase the data observations.

[0130] In some embodiments, each epoch has its corresponding receiver, each receiver is used to receive data from at least one satellite at a preset fixed frequency, and the data received by multiple receivers corresponding to multiple epochs form observation data.

[0131] S302, preprocessing the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filter data, wherein the narrow-lane filter data is used to perform orbit filter resolution on the narrow-lane ambiguity data.

[0132] It should be noted that the wide lane floating point ambiguity comes from the smoothing result of the observation data, that is, it can be directly extracted from the observation data; while the narrow lane floating point ambiguity comes from the orbit solution or clock error solution floating point ambiguity, that is, the observation data is first filtered and solved through orbit filtering or clock error filtering, and then the narrow lane floating point ambiguity is determined by combining the wide lane integer ambiguity after the wide lane floating point ambiguity is fixed. Therefore, what is directly extracted from the observation data is the narrow lane filtered data used for orbit filtering or clock error filtering.

[0133] S303, based on the widelane floating point ambiguity and the floating point ambiguity fixing method provided in the embodiment of the present application, determine the solution results of the target widelane integer ambiguity and the widelane UPD corresponding to the target epoch.

[0134] In some embodiments, the widelane UPD includes a widelane satellite UPD corresponding to each epoch in the at least one epoch, and at least one widelane receiver UPD corresponding one-to-one to each epoch in the at least one epoch.

[0135] S304, determining narrow lane floating point ambiguity according to the narrow lane filter data and the wide lane integer ambiguity.

[0136] The calculation principle of narrow lane floating point ambiguity can be explained by the above formula 3.

[0137] S305, based on the narrowlane floating point ambiguity and the floating point ambiguity fixing method provided in the embodiment of the present application, determine the solution results of the target narrowlane integer ambiguity and the narrowlane UPD corresponding to the target epoch.

[0138] In some embodiments, the solution result of the narrowlane UPD includes narrowlane satellite UPDs corresponding to at least one epoch, and narrowlane receiver UPDs corresponding to each epoch of the at least one epoch.

[0139] S306, using the wide lane floating point ambiguity, the target wide lane integer ambiguity, the solution result of the wide lane UPD, the narrow lane floating point ambiguity, the target narrow lane integer ambiguity and the solution result of the narrow lane UPD as constraints, constraining the floating point orbit variance, and determining the orbit solution result with fixed ambiguity.

[0140] For ease of understanding, the above-mentioned orbit solution method is described in detail in conjunction with a specific implementation device.

[0141] like Figure 4 As shown, an embodiment of the present application provides a track solution device, including a data preprocessing module 401, a wide lane UPD estimation module 402, a narrow lane UPD estimation module 403, a clock error filtering module 404, and a clock error UPD module 405.

[0142] In step A, the data preprocessing module 401 receives observation data sent by the satellite and extracts wide-lane floating-point ambiguity data and narrow-lane filtering data therefrom.

[0143] Step B: the wide lane UPD estimation module 402 receives the wide lane floating point ambiguity data sent by the data preprocessing module 401, and determines the wide lane integer ambiguity, the wide lane receiver UPD and the wide lane satellite UPD according to the floating point ambiguity fixing method provided in the embodiment of the present application.

[0144] Step C: the clock error filtering module 404 receives the narrowlane filter data sent by the data preprocessing module 401 and the widelane integer ambiguity sent by the widelane UPD estimation module 402 via the narrowlane UPD estimation module 403, and determines the narrowlane floating point ambiguity according to the narrowlane filter data and the widelane integer ambiguity.

[0145] Step D: the narrow lane UPD module 403 receives the narrow lane floating point ambiguity sent by the clock error filtering module 404, and determines the narrow lane integer ambiguity, the narrow lane receiver UPD and the narrow lane satellite UPD according to the floating point ambiguity fixing method provided in the embodiment of the present application.

[0146] In step E, the clock error filtering module 404 uses the wide lane integer ambiguity, wide lane receiver UPD, wide lane satellite UPD, narrow lane integer ambiguity, narrow lane receiver UPD and narrow lane satellite UPD as constraints, constrains the floating point orbit variance, and determines the orbit solution result with fixed ambiguity.

[0147] The above UPD solution result can be sent to the clock difference UPD module 405 for use in other positioning algorithms.

[0148] Based on the same inventive concept mentioned above, an embodiment of the present application provides a method for solving clock errors.

[0149] like Figure 5 As shown, the embodiment of the present application provides a clock error solution method, comprising the following steps:

[0150] S501, obtaining observation data of at least one epoch, wherein the at least one epoch includes a target epoch.

[0151] S502, preprocessing the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filtered data, wherein the narrow-lane filtered data is used to perform clock error filtering on the narrow-lane ambiguity data.

[0152] S503, based on the widelane floating point ambiguity and the floating point ambiguity fixing method provided in the embodiment of the present application, determine the solution results of the target widelane integer ambiguity and the widelane UPD corresponding to the target epoch.

[0153] S504, determining narrow lane floating point ambiguity according to the narrow lane filter data and the wide lane integer ambiguity.

[0154] S505, based on the narrowlane floating point ambiguity and the floating point ambiguity fixing method provided in the embodiment of the present application, determine the solution results of the target narrowlane integer ambiguity and the narrowlane UPD corresponding to the target epoch.

[0155] S506, using the wide lane floating point ambiguity, the target wide lane integer ambiguity, the solution result of the wide lane UPD, the narrow lane floating point ambiguity, the target narrow lane integer ambiguity and the solution result of the narrow lane UPD as constraints, constraining the floating point clock error variance, and determining the clock error solution result with fixed ambiguities.

[0156] It should be noted that the solution results of wide lane UPD include wide lane receiver UPD and wide lane satellite UPD, and the solution results of narrow lane UPD include narrow lane receiver UPD and narrow lane satellite UPD, among which the solution results of wide lane satellite UPD and narrow lane satellite UPD can be output separately to other required modules, such as for precise point positioning module.

[0157] Based on the same inventive concept as the track solving device, Figure 6 As shown, an embodiment of the present application provides a clock error solving device, including a data preprocessing module 601, a wide lane UPD estimation module 602, a narrow lane UPD estimation module 603, a clock error filtering module 604 and a clock error UPD module 605.

[0158] The clock error solving device and Figure 5 The specific implementation process of the orbit solution device shown is consistent, and this application will not repeat it. However, it should be noted that the clock error UPD module 605 is used to receive the target wide lane satellite UPD and the target narrow lane satellite UPD determined by the clock error filter module 604, and output them to other demand modules, such as a positioning module for precise single point positioning.

[0159] The orbit solution method and clock error solution method provided in the embodiment of the present application adopt the floating point ambiguity fixing method provided in the embodiment of the present invention to determine the wide lane integer ambiguity and the narrow lane integer ambiguity in real time, thereby improving the timeliness and accuracy of the floating point ambiguity fixing, and thus improving the accuracy of the real-time orbit and clock error solution. Compared with the traditional double difference ambiguity fixing technology, the operation efficiency is higher, and at the same time, the UPD estimation device is directly embedded in the orbit and clock error solution device, saving computing resources.

[0160] Based on the same inventive concept of the floating point ambiguity fixing method provided in the embodiment of the present application, the embodiment of the present application also provides a floating point ambiguity fixing device.

[0161] like Figure 7As shown, the embodiment of the present application also provides a floating point ambiguity fixing device, the device comprising:

[0162] An acquiring unit 701 is configured to acquire a floating point ambiguity of at least one epoch, wherein the at least one epoch includes a target epoch;

[0163] A processing unit 702 is configured to iteratively round the floating point ambiguity according to an iterative algorithm to obtain a target integer ambiguity of a target epoch;

[0164] Among them, each iterative rounding process includes:

[0165] Taking the reference uncalibrated phase delay UPD as a constraint condition, the floating point ambiguity is rounded to determine the integer ambiguity, wherein, in the first iteration process, the reference UPD is a preset UPD initial value or the UPD determined in the iterative rounding process of the previous target epoch, and in the Nth iteration process, the reference UPD is the UPD solved in the N-1th iteration rounding process, and N is an integer greater than or equal to 2;

[0166] According to the floating point ambiguity and the integer ambiguity obtained in each iteration, the UPD estimation equation is established, the UPD is calculated, and the solution of the UPD is determined;

[0167] The UPD solution result is subjected to data verification. If the data verification passes, the integer ambiguity corresponding to the UPD solution result is used as the target integer ambiguity after the target epoch is fixed.

[0168] Based on the same inventive concept of the orbit solution method provided in the embodiment of the present application, the embodiment of the present application also provides another orbit solution device.

[0169] In some embodiments, the apparatus may further include:

[0170] The screening unit is used to screen the ambiguity data of at least one epoch, filter out the data whose variance in the ambiguity data is greater than a preset variance threshold, and determine the floating point ambiguity.

[0171] In some embodiments, the processing unit 702 may be specifically configured to:

[0172] Perform residual check on the UPD solution results according to floating point ambiguity and integer ambiguity to determine the residual value;

[0173] Determine the iteration difference according to the UPD solution results obtained in this iteration and the previous iteration;

[0174] When the residual value is less than the preset residual threshold and the iteration difference is less than the preset iteration difference threshold, the UPD solution result obtained in this iteration is determined as the UPD solution result of the target epoch, and the integer ambiguity obtained in this iteration is used as the target integer ambiguity after the target epoch is fixed.

[0175] In some embodiments, the float ambiguity includes a wide lane float ambiguity and / or a narrow lane float ambiguity.

[0176] In some embodiments, the UPD solution includes satellite UPD and receiver UPD.

[0177] The satellite UPD is obtained based on the floating point ambiguity of at least two epochs in at least one epoch, the at least two epochs include a target epoch, and the receiver UPD is obtained based on the floating point ambiguity of the target epoch.

[0178] like Figure 8 As shown, the embodiment of the present application provides another track solving device, the device comprising:

[0179] An acquisition unit 801 is used to acquire observation data of at least one epoch, wherein the at least one epoch includes a target epoch;

[0180] An extraction unit 802 is used to pre-process the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filter data, wherein the narrow-lane filter data is used to perform orbit filter resolution on the narrow-lane ambiguity data;

[0181] The first processing unit 803 is configured to determine a solution result of a target widelane integer ambiguity and a widelane UPD corresponding to a target epoch based on the widelane floating point ambiguity and the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application;

[0182] A determination unit 804, configured to determine narrowlane floating point ambiguities based on the narrowlane filter data and the widelane integer ambiguities;

[0183] The second processing unit 805 is configured to determine a solution result of a target narrow lane integer ambiguity and a narrow lane UPD corresponding to a target epoch based on the narrow lane floating point ambiguity and the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application;

[0184] The solving unit 806 is used to use the solution results of the wide lane floating point ambiguity, the target wide lane integer ambiguity, the wide lane UPD, the narrow lane floating point ambiguity, the target narrow lane integer ambiguity and the narrow lane UPD as constraints, constrain the floating point orbit variance, and determine the orbit solution result with fixed ambiguity.

[0185] Based on the same inventive concept of the clock error solution method provided in the embodiment of the present application, the embodiment of the present application also provides another clock error solution device.

[0186] like Fig. 9 As shown, the embodiment of the present application also provides another clock error solving device, the device comprising:

[0187] An acquisition unit 901 is used to acquire observation data of at least one epoch, wherein the at least one epoch includes a target epoch;

[0188] An extraction unit 902 is used to pre-process the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filter data, wherein the narrow-lane filter data is used to perform clock error filtering on the narrow-lane ambiguity data;

[0189] The first processing unit 903 is configured to determine a solution result of a target widelane integer ambiguity and a widelane UPD corresponding to a target epoch based on the widelane floating point ambiguity and the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application;

[0190] A determination unit 904, configured to determine narrow lane floating point ambiguities based on the narrow lane filter data and the wide lane integer ambiguities;

[0191] The second processing unit 905 is configured to determine a solution result of a target narrow lane integer ambiguity and a narrow lane UPD corresponding to a target epoch based on the narrow lane floating point ambiguity and the floating point ambiguity fixing method provided in the first aspect of the embodiment of the present application;

[0192] The solving unit 906 is used to use the solution results of the wide lane floating point ambiguity, the target wide lane integer ambiguity, the wide lane UPD, the narrow lane floating point ambiguity, the target narrow lane integer ambiguity and the narrow lane UPD as constraints, constrain the floating point clock error variance, and determine the clock error solution result with fixed ambiguity.

[0193] Other details of the floating point ambiguity fixing device, orbit solving device and clock error solving device provided in the embodiments of the present application are combined with the above Figure 1-Figure 3 , Figure 5 The floating point ambiguity fixing method, orbit solution method and clock error solution method described in the embodiments of the present application are similar and will not be repeated here.

[0194] Fig.10 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application is shown.

[0195] Combination Figure 1-Figure 9 The floating-point ambiguity fixing method, orbit solving method, clock error solving method, floating-point ambiguity fixing device, orbit solving device and clock error solving device provided according to the embodiments of the present application can be implemented by an electronic device. Fig.10 FIG. 1 is a schematic diagram showing a hardware structure 1000 of an electronic device according to an embodiment of the present invention.

[0196] The electronic device may include a processor 1001 and a memory 1002 storing computer program instructions.

[0197] Specifically, the processor 1001 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0198] The memory 1002 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 1002 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In one example, the memory 302 may include a removable or non-removable (or fixed) medium, or the memory 1002 is a non-volatile solid-state memory. The memory 1002 may be inside or outside the integrated gateway disaster recovery device.

[0199] In one example, the memory 1002 may be a read-only memory (ROM). In one example, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or a flash memory, or a combination of two or more of these.

[0200] The processor 1001 reads and executes the computer program instructions stored in the memory 1002 to implement Figure 1 The method / steps S101 to S102 in the illustrated embodiment, and / or, Figure 3 The method / steps S301 to S306 in the illustrated embodiment, and / or, Figure 5 The method / steps S501 to S506 in the embodiment shown in the figure are achieved Figure 1 and / or Figure 3 and / or Figure 5 The corresponding technical effects achieved by executing the methods / steps in the examples shown are not repeated here for the sake of brevity.

[0201] In one example, the electronic device may further include a communication interface 1003 and a bus 1010. Fig. 9 As shown, the processor 1001, the memory 1002, and the communication interface 1003 are connected via a bus 1010 and communicate with each other.

[0202] The communication interface 1003 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0203] Bus 1010 includes hardware, software or both, and the components of online data flow billing equipment are coupled to each other. For example, but not limitation, the bus may include Accelerated Graphics Port (AGP) or other graphics bus, Enhanced Industry Standard Architecture (EISA) bus, Front Side Bus (FSB), Hyper Transport (HT) interconnection, Industry Standard Architecture (ISA) bus, InfiniBand interconnection, Low Pin Count (LPC) bus, Memory bus, Micro Channel Architecture (MCA) bus, Peripheral Component Interconnect (PCI) bus, PCI-Express (PCI-X) bus, Serial Advanced Technology Attachment (SATA) bus, Video Electronics Standards Association Local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 1010 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the present application considers any suitable bus or interconnection.

[0204] The electronic device provided in the embodiment of the present application first obtains the floating-point ambiguity of at least one epoch, wherein the at least one epoch includes a target epoch, and then iteratively rounds the floating-point ambiguity according to an iterative algorithm to obtain a target integer ambiguity of the target epoch. In the process of iteratively rounding the floating-point ambiguity, a UPD estimation equation is established to determine the solution result of the UPD, and the floating-point ambiguity is rounded based on this as a constraint condition to determine the integer ambiguity. The integer ambiguity is determined by the above-mentioned iterative algorithm, which improves the timeliness and accuracy of the fixing of the floating-point ambiguity. At the same time, since the ambiguity data targeted by the above-mentioned iterative algorithm is the floating-point ambiguity of at least one epoch with the target epoch as the calculation unit, compared with the prior art, the present application can also reduce the amount of calculation and calculation time.

[0205] In addition, in combination with the floating point ambiguity fixing method, orbit solving method and clock error solving method in the above embodiments, the embodiments of the present application may provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any one of the floating point ambiguity fixing method, orbit solving method and clock error solving method in the above embodiments is implemented.

[0206] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0207] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), appropriate firmware, plug-in, function card, etc. When implemented in software, the elements of the present application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or communication link by a data signal carried in a carrier. "Machine-readable medium" may include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (Radio Frequency, RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0208] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0209] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0210] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A floating point ambiguity fixing method, characterized in that: The method comprises: obtaining floating point ambiguities for at least one epoch, the at least one epoch comprising a target epoch; Iteratively rounding the floating point ambiguity according to an iterative algorithm to obtain a target integer ambiguity of the target epoch; Among them, each iterative rounding process includes: Taking the reference uncalibrated phase delay UPD as a constraint condition, the floating point ambiguity is rounded to determine the integer ambiguity, wherein, in the first iteration process, the reference uncalibrated phase delay UPD is a preset UPD initial value or the UPD determined in the iterative rounding process of the previous target epoch, and in the Nth iteration process, the reference uncalibrated phase delay UPD is the UPD solved in the N-1th rounding process, and N is an integer greater than or equal to 2; Establishing a UPD estimation equation according to the floating point ambiguity and the integer ambiguity obtained in each iteration, calculating the UPD, and determining a solution result of the UPD; A data check is performed on the solution result of the UPD. If the data check passes, the integer ambiguity corresponding to the solution result of the UPD is used as the target integer ambiguity after the target epoch is fixed.

2. The method according to claim 1, characterized in that Before obtaining the floating point ambiguity of at least one epoch, the method further comprises: Data screening is performed on the ambiguity data of the at least one epoch, data whose variance in the ambiguity data is greater than a preset variance threshold is filtered out, and the floating point ambiguity is determined.

3. The method according to claim 1, characterized in that The performing data verification on the solution result of the UPD, and if the data verification passes, using the integer ambiguity as the target integer ambiguity after the target epoch is fixed, comprises: Performing a residual check on a solution result of the UPD according to the floating point ambiguity and the integer ambiguity to determine a residual value; Determine an iteration difference according to the solution results of the UPD obtained in this iteration and the previous iteration; When the residual value is less than a preset residual threshold and the iteration difference is less than a preset iteration difference threshold, it is determined that the solution result of the UPD obtained in this iteration is the solution result of the UPD of the target epoch, and the integer ambiguity obtained in this iteration is used as the target integer ambiguity after the target epoch is fixed.

4. The method according to claim 1, characterized in that: The floating point ambiguity includes wide lane floating point ambiguity and / or narrow lane floating point ambiguity.

5. The method according to claim 1, characterized in that: The UPD solution includes satellite UPD and receiver UPD. The satellite UPD is obtained based on the floating-point ambiguity of at least two epochs of the at least one epoch, the at least two epochs include the target epoch, and the receiver UPD is obtained based on the floating-point ambiguity of the target epoch.

6. A trajectory solution method, characterized in that: The method comprises: Acquire observation data of at least one epoch, the at least one epoch comprising a target epoch; Preprocessing the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filter data, wherein the narrow-lane filter data is used to perform orbit filter resolution on the narrow-lane ambiguity data; Based on the widelane floating point ambiguity and the method according to any one of claims 1 to 5, determining a solution result of a target widelane integer ambiguity and a widelane UPD corresponding to the target epoch; determining narrowlane floating point ambiguities based on the narrowlane filtered data and the widelane integer ambiguities; Based on the narrowlane floating point ambiguity and the method according to any one of claims 1 to 5, determining a solution result of a target narrowlane integer ambiguity and a narrowlane UPD corresponding to the target epoch; The wide lane floating point ambiguity, the target wide lane integer ambiguity, the solution result of the wide lane UPD, the narrow lane floating point ambiguity, the target narrow lane integer ambiguity and the solution result of the narrow lane UPD are used as constraints to constrain the floating point orbit variance and determine the orbit solution result with fixed ambiguity.

7. A clock error calculation method, characterized in that: The method comprises: Acquire observation data of at least one epoch, the at least one epoch comprising a target epoch; Preprocessing the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filter data, wherein the narrow-lane filter data is used to perform clock error filtering on the narrow-lane ambiguity data; Based on the widelane floating point ambiguity and the method according to any one of claims 1 to 5, determining a solution result of a target widelane integer ambiguity and a widelane UPD corresponding to the target epoch; determining narrowlane floating point ambiguities based on the narrowlane filtered data and the widelane integer ambiguities; Based on the narrowlane floating point ambiguity and the method according to any one of claims 1 to 5, determining a solution result of a target narrowlane integer ambiguity and a narrowlane UPD corresponding to the target epoch; The wide lane floating point ambiguity, the target wide lane integer ambiguity, the solution result of the wide lane UPD, the narrow lane floating point ambiguity, the target narrow lane integer ambiguity and the solution result of the narrow lane UPD are used as constraints to constrain the floating point clock error variance and determine the clock error solution result with fixed ambiguity.

8. A device for fixing floating point ambiguity, characterized in that: The device comprises: an acquisition unit, configured to acquire a floating point ambiguity of at least one epoch, the at least one epoch comprising a target epoch; A processing unit, configured to iteratively round the floating point ambiguity according to an iterative algorithm to obtain a target integer ambiguity of the target epoch; Among them, each iterative rounding process includes: Taking the reference uncalibrated phase delay UPD as a constraint condition, the floating point ambiguity is rounded to determine the integer ambiguity, wherein, in the first iteration process, the reference uncalibrated phase delay UPD is a preset UPD initial value or the UPD determined in the iterative rounding process of the previous target epoch, and in the Nth iteration process, the reference uncalibrated phase delay UPD is the UPD solved in the N-1th iteration rounding process, and N is an integer greater than or equal to 2; Establishing a UPD estimation equation according to the floating point ambiguity and the integer ambiguity obtained in each iteration, calculating the UPD, and determining a solution result of the UPD; A data check is performed on the solution result of the UPD. If the data check passes, the integer ambiguity corresponding to the solution result of the UPD is used as the target integer ambiguity after the target epoch is fixed.

9. A track solving device, characterized in that: The device comprises: an acquisition unit, configured to acquire observation data of at least one epoch, wherein the at least one epoch includes a target epoch; An extraction unit, used for preprocessing the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filter data, wherein the narrow-lane filter data is used for performing orbit filter resolution on the narrow-lane ambiguity data; A first processing unit, configured to determine a solution result of a target widelane integer ambiguity and a widelane UPD corresponding to the target epoch based on the widelane floating point ambiguity and the method according to any one of claims 1 to 5; a determining unit, configured to determine narrowlane floating point ambiguities according to the narrowlane filter data and the widelane integer ambiguities; A second processing unit, configured to determine a solution result of a target narrowlane integer ambiguity and a narrowlane UPD corresponding to the target epoch based on the narrowlane floating point ambiguity and the method according to any one of claims 1 to 5; A solution unit is used to use the wide lane floating point ambiguity, the target wide lane integer ambiguity, the solution result of the wide lane UPD, the narrow lane floating point ambiguity, the target narrow lane integer ambiguity and the solution result of the narrow lane UPD as constraints, constrain the floating point orbit variance, and determine the orbit solution result with fixed ambiguity.

10. A clock error calculation device, characterized in that: The device comprises: an acquisition unit, configured to acquire observation data of at least one epoch, wherein the at least one epoch includes a target epoch; An extraction unit, used for preprocessing the observation data to obtain wide-lane floating-point ambiguity and narrow-lane filtering data, wherein the narrow-lane filtering data is used for performing clock error filtering on the narrow-lane ambiguity data; A first processing unit, configured to determine a solution result of a target widelane integer ambiguity and a widelane UPD corresponding to the target epoch based on the widelane floating point ambiguity and the method according to any one of claims 1 to 5; a determining unit, configured to determine narrowlane floating point ambiguities according to the narrowlane filter data and the widelane integer ambiguities; A second processing unit, configured to determine a solution result of a target narrowlane integer ambiguity and a narrowlane UPD corresponding to the target epoch based on the narrowlane floating point ambiguity and the method according to any one of claims 1 to 5; A solving unit is used to use the wide lane floating point ambiguity, the target wide lane integer ambiguity, the solution result of the wide lane UPD, the narrow lane floating point ambiguity, the target narrow lane integer ambiguity and the solution result of the narrow lane UPD as constraints, constrain the floating point clock error variance, and determine the clock error solution result with fixed ambiguity.

11. An electronic device, characterized in that: The device includes: a processor, and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the floating-point ambiguity fixing method as described in any one of claims 1 to 5, the orbit solution method as described in claim 6, and the clock error solution method as described in claim 7.

12. A computer storage medium, characterized in that: The computer storage medium stores computer program instructions, which, when executed by a processor, implement the floating-point ambiguity fixing method according to any one of claims 1 to 5, the orbit solution method according to claim 6, and the clock error solution method according to claim 7.

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