A bus-based data elastic buffer system and data transmission method

Abstract

The present invention discloses a data elastic buffer system and a data transmission method based on a bus. The system includes: an APB bus; an APB configuration register module; a data buffer structure; an I2S control module; an I2S bus. The data buffer structure is respectively communicatively connected to the APB configuration register module and the I2S control module. The APB configuration register module is connected to the APB bus, and the I2S control module is connected to the I2S bus. The APB configuration register module and the I2S control module establish a communication connection with the data buffer structure by using a handshake protocol, and perform read and write operations in the data buffer structure through the handshake protocol. By adopting the handshake protocol in the elastic buffer structure, the system and method enable the I2S bus to have enough time to read data from the elastic buffer structure, which can ensure the continuity of the Gray-coded pointer when synchronized to the clock domain of the other party.

Description

Technical Field

[0001] The present invention relates to the technical field of bus structure and data transmission technology, and in particular to a bus-based data elastic buffer system and a data transmission method. Background Art

[0002] The existing data elastic buffer structure mostly uses Gray code for pointer synchronization in asynchronous FIFO, and expands the pointer bit width by one bit to assist in the judgment of FIFO empty or full. However, the above-mentioned prior art has the following technical problems: 1. In the process of converting the binary pointer into Gray code and synchronizing it to the other party's clock domain, the slow clock domain may miss the sampling of the fast clock domain, which will make the judgment of empty or full signals more conservative, thereby reducing efficiency; 2. Due to the occurrence of missed sampling, when the pointer of the fast clock domain is synchronized to the slow clock domain, the pointer change transmitted by the Gray code is not continuous, but several bits of Gray code change will occur at one time. Summary of the invention

[0003] One of the inventive purposes of the present invention is to provide a bus-based data elastic buffer system and data transmission method. The system and method adopt a handshake protocol in the elastic buffer structure so that the i2s bus reads data from the elastic buffer structure in sufficient time, thereby ensuring the continuity of the gray-coded pointer when it is synchronized to the other party's clock domain.

[0004] Another object of the present invention is to provide a bus-based data elastic buffer system and data transmission method. The system and method perform synchronization of read and write pointers through the handshake protocol, which can reduce the leakage phenomenon of the slow clock domain sampling the fast clock domain, thereby improving the efficiency of judging empty and full signals.

[0005] Another object of the present invention is to provide a bus-based data elastic buffer system and data transmission method. The system and method can fully ensure the continuity and accuracy of data changes by reducing the phenomenon of missed data, and the judgment of almost empty and almost full is more accurate.

[0006] In order to achieve at least one of the above-mentioned invention objects, the present invention further provides a bus-based data elastic buffer system, the system comprising:

[0007] apb bus;

[0008] apb configuration register module;

[0009] Data buffer structure;

[0010] i2s control module;

[0011] i2s bus;

[0012] The data buffer structure is respectively communicatively connected to the APB configuration register module and the I2S control module. The APB configuration register module is connected to the APB bus, and the I2S control module is connected to the I2S bus. The APB configuration register module and the I2S control module establish a communication connection with the data buffer structure using a handshake protocol, and perform read and write operations in the data buffer structure through the handshake protocol.

[0013] According to one preferred embodiment of the present invention, the data buffer structure includes a data storage unit and a data synchronization unit, and the data storage unit is connected to the data synchronization unit.

[0014] According to another preferred embodiment of the present invention, the data buffer structure further includes a write control unit and a read control unit. The write control unit and the read control unit are respectively communicatively connected to the data storage unit and the data synchronization unit, and the write control unit and the read control unit perform synchronous operations of writing data and reading out data using a handshake protocol.

[0015] In order to achieve at least one of the above invention objectives, the present invention further provides a bus-based data transmission method, and the method includes:

[0016] Obtain status data in the data buffer structure, and determine whether it is valid data according to the status data;

[0017] Generate a valid read or write enable according to the valid data;

[0018] Convert the pointer of the valid read / write enable into a Gray code, and synchronize the valid read or write enable from the current clock domain to the target clock domain according to the Gray code;

[0019] After synchronizing to the target clock domain, simultaneously synchronize the valid read or write enable to the current clock domain to update the status of the data buffer structure;

[0020] According to the updated data buffer structure, determine again whether there is valid data in the status data to perform the next read or write synchronization operation.

[0021] According to one preferred embodiment of the present invention, the status data of the data buffer structure includes empty, full, almost empty, almost full, read empty, and read full states, and the status data constitutes an interruption of data transmission in the buffer structure.

[0022] According to another preferred embodiment of the present invention, the data transmission method includes a data writing method: the APB configuration register module and the I2S control module input the data and write enable of the corresponding bus into the data buffer structure. If the data buffer structure detects external written data and determines that the current state in the data buffer structure is a full interrupt, then the currently detected external written data is invalid data, and the corresponding input write enable is an invalid enable.

[0023] According to another preferred embodiment of the present invention, during data writing, the APB configuration register module and the I2S control module input the data and write enable of the corresponding bus into the data buffer structure. When the data buffer structure detects external written data, if it is determined that the current state in the buffer structure is a non-full state, then the write enable data is a valid write enable, and the corresponding external written data is valid data. The write enable is synchronized to the read clock domain through the handshake protocol and synchronized to the current write clock domain.

[0024] According to another preferred embodiment of the present invention, the data transmission method includes a readout method: the APB configuration register module or the I2S control module inputs the data and read enable of the corresponding bus into the data buffer structure. If the data buffer structure detects external readout data and determines that the current state in the data buffer structure is an empty interrupt, then the currently detected external readout data is regarded as invalid data, and the currently detected read enable is an invalid enable.

[0025] According to another preferred embodiment of the present invention, the data transmission method includes a readout method: the APB configuration register module or the I2S control module inputs the data and its own read enable of the corresponding bus into the data buffer structure. If the data buffer structure detects external readout data and determines that the current state in the data buffer structure is a non-empty interrupt, then the currently detected external readout data is regarded as valid data, and the currently detected read enable is a valid enable. The corresponding external read enable is synchronized to the write clock domain through the handshake protocol and synchronized to the current read clock domain.

[0026] According to another preferred embodiment of the present invention, when synchronizing a valid read enable or write enable to the corresponding clock domain, the corresponding write pointer Gray code or read pointer Gray code is converted into binary data, the converted write pointer binary data is subtracted from the read pointer binary data, and the state data in the data buffer structure is regenerated according to the subtraction result and synchronized to the corresponding clock domain.

[0027] The present invention further provides a computer-readable storage medium storing a computer program that can be executed by a processor to perform the above data transmission method. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a schematic structural diagram of a data elastic buffer system based on a bus according to the present invention.

[0029] Figure 2 Shown is a schematic diagram of a data transmission method based on a bus according to the present invention.

[0030] Figure 3 Shown is a schematic flowchart of the write mode in the present invention.

[0031] Figure 4 Shown is a schematic flowchart of the read mode in the present invention. Detailed implementation manners

[0032] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles defined in the following description can be applied to other implementation manners, variation schemes, improvement schemes, equivalent schemes, and other technical schemes that do not depart from the spirit and scope of the present invention.

[0033] It can be understood that the term "a" should be understood as "at least one" or "one or more". That is, in one embodiment, the number of an element can be one, and in other embodiments, the number of the element can be multiple. The term "a" cannot be understood as a limitation on the number.

[0034] Please refer to Figures 1 - 4 , the present invention discloses a data elastic buffer system structure and a data transmission method based on a bus, wherein the data elastic buffer system includes: an APB bus, an APB configuration register module, a data buffer structure, an I2S control module, and an I2S bus. The APB bus is connected to the APB configuration register module, and the APB configuration register module is connected to the data buffer structure. The I2S bus is connected to the I2S control module, and the I2S control module is communicatively connected to the data buffer structure. The present invention writes data or reads data from the data buffer structure through the above-mentioned APB configuration register module and I2S control module, and the APB configuration register module and the I2S control module are communicatively connected to the buffer structure through a handshake protocol. The buffer module includes a data storage unit (stram) and a data synchronization unit. The data storage unit is used to store and read valid data, and the data storage unit is connected to the data synchronization unit for synchronous operations of data reading and writing.

[0035] It is worth mentioning that the data buffer structure further includes a data write control unit and a read control unit. The write control unit and the read control unit will obtain the status data in the data buffer structure, and further generate valid data and invalid data according to the status data in the data buffer structure, and further perform data transmission operations in different clock domains according to the valid data.

[0036] Specifically, the clock domains include a read clock domain and a write clock domain. The read control unit is in the read clock domain, and the write control unit is in the write clock domain. The APB configuration register module is respectively connected to the write control unit and the read control unit, and can obtain corresponding data from the APB bus through the APB configuration register module, and write the data into the data buffer structure through the APB configuration register module. The read control unit and the write control unit in the data buffer structure judge the status data of the current data buffer structure, and further judge the validity of the current data and enable according to the status data, and then further perform operations such as data writing, reading and transmission. Similarly, the I2S control module can input the data in the I2S bus into the corresponding data buffer structure, and read the data in the data buffer structure. The read control unit and the write control unit in the data buffer structure obtain the status data of the data buffer structure, and perform operations such as writing, reading and transmission of the data and enable after judging the validity of the current data and enable according to the status data.

[0037] In the present invention, the read and write operations of data are respectively performed through the read clock domain and the write clock domain in the data buffer structure. The status of the data buffer structure includes 6 status signals such as empty, full, almost empty, almost full, read empty, and read full. Each status signal implements an interruption. The 6 status signals are directly determined according to the filling degree of the data queue in the data buffer structure. The empty signal is the case where there is no data signal in the data queue in the data buffer structure, the full signal is the signal that the data queue in the data buffer structure is full, and the almost empty signal is according to the threshold of the preset queuing sequence. If the sorting value of the data queue in the current buffer data structure is less than the preset almost empty signal threshold, the corresponding almost empty signal interruption is output through the preset almost empty signal threshold. Similarly, the almost full signal threshold is set. If the sorting value of the data queue in the current buffer data structure is greater than the almost full signal threshold, the almost full signal interruption is output according to the almost full signal threshold. In the read mode, the read empty signal interruption is further output according to the sorting value of the data queue in the current buffer data structure. The generation method of the read empty interruption includes: if there is no data in the data queue in the current buffer data structure, the read empty interruption signal is output. If the data queue in the current buffer data structure is full of data, the read full interruption signal is output.

[0038] It is worth mentioning that the present invention utilizes a handshake protocol to perform different data transmission and synchronization operations under state data with different data queue sorting values in the buffer data structure. In one preferred embodiment of the present invention, in the write mode of the APB configuration register module, the APB bus writes data and write enable into the data buffer structure through the APB configuration register module. At the same time, the I2S control module generates a read enable, and the read enable is transmitted into the data buffer structure. In the read mode of the APB configuration register module, the I2S control module generates data and write enable, and writes the generated data and write enable into the data buffer structure. Then, the read enable generated by the APB configuration register module reads the corresponding data.

[0039] Please refer to Figure 3 the flow schematic diagram in the write mode shown, where the APB configuration register module or the I2S control module determines that there is an external data write operation on the corresponding bus, obtains the data on the corresponding bus, and generates the corresponding write enable. The APB configuration register module or the I2S control module determines the state data in the current data buffer structure. If the state data in the current data buffer structure is a full interrupt state, then further the currently obtained data is invalid data, and the currently generated write enable is an invalid enable. At this time, the data on the external bus cannot be written into the data buffer structure. If it is determined through the corresponding APB configuration register module or I2S control module that the data in the current data buffer structure is not in a full interrupt state, and may be empty, almost empty, read empty, etc. interrupt signals, then the data written on the bus is regarded as valid data through the corresponding APB configuration register module or I2S control module, and the write enable generated by itself is used as a valid enable to generate a request and transmit it into the read clock domain. And the valid data written on the bus is saved in the data storage unit (scram). At the same time, the write pointer is synchronized to the read clock domain in the form of a Gray code by using the handshake protocol according to the valid write enable data. Among them, after the write pointer is converted into a Gray code, the synchronization operation is performed in the form of two-stage flip-flops. After the synchronization operation of the write pointer is completed, the write pointer converted into a Gray code is further converted into binary data, and the binary data of the write pointer minus the binary data of the current read pointer is used as the basis for finally judging the state of the data buffer structure. Among them, the binary data of the write pointer minus the current binary data of the read pointer can obtain the value of the sorting queue of the corresponding data in the data buffer structure, so as to determine the final state data according to the preset state threshold of the data buffer structure.

[0040] Please refer to Figure 4The figure shows a schematic diagram of the process in read mode. In this diagram, the APB configuration register module or the I2S control module determines that there is an external read data request. The APB configuration register module or the I2S control module generates a corresponding read enable. By the APB configuration register module or the I2S control module, the status data of the current data buffer structure is judged. If the status data of the current data buffer structure is an empty interrupt, it indicates that there is no corresponding data in the sorting queue of the current data buffer structure. Then the APB configuration register module or the I2S control module regards the corresponding external read data as invalid data, and the corresponding read enable as an invalid enable. At this time, because the data and the read enable are invalid, it can ensure that the reading and writing in the data queue of the data buffer structure are in order, avoiding the occurrence of missed sampling phenomena. When the APB configuration register module or the I2S control module judges that the status data of the current data buffer structure is not empty, where the not empty status includes statuses such as almost empty, almost full, full, and read full. At this time, the APB configuration register module or the I2S control module regards the current external read data (from the data buffer structure) as valid data, and also regards the read enable as a valid enable. Further, a synchronization request is sent to the write clock domain through the valid read enable. The read pointer corresponding to the valid read enable is converted into a Gray code form data and synchronized into the write clock domain, and the read pointer data converted into the Gray code form is converted into binary data. The binary data of the read pointer obtained by the conversion is subtracted from the binary data of the write pointer in the current data buffer structure. Thus, the result obtained by the above subtraction is used as the judgment basis for the status data of the current data buffer structure, and the status data in the current data buffer structure is finally judged according to the preset status data threshold.

[0041] It is worth mentioning that the present invention utilizes a handshake protocol with a one-time response method and applies the handshake protocol to read / write enable control. Through the control of the read / write enable, when the read / write enable is valid, a request signal is generated and synchronized to the other clock domain to generate a response signal. After synchronizing back to the original clock domain, the generated request signal is pulled low, so that the read / write pointers can be accurately counted after being synchronized to the other clock domain, avoiding read / write mis-sampling phenomena.

[0042] In another preferred embodiment of the present invention, if the APB configuration register module or the I2S control module judges that the current data buffer structure is in an almost full interrupt state, the generation of the write enable is stopped, so as to stop the corresponding bus from writing data to the data buffer structure until the current data buffer structure issues an almost empty signal, and then the write enable is regenerated to perform the write operation.

[0043] In particular, according to the embodiments disclosed in the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, an embodiment of the present disclosure includes a computer program product that includes a computer program carried on a computer-readable medium, and the computer program contains program code for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), the above functions defined in the method of the present application are performed. It should be noted that the computer-readable medium in the present application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wire segments, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or combined with an instruction execution system, apparatus, or device. In the present application, the computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries the computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable medium can send, propagate, or transmit a program for use by or combined with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination of the above.

[0044] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0045] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are only examples and do not limit the present invention. The objectives of the present invention have been fully and effectively achieved. The functions and structural principles of the present invention have been demonstrated and explained in the embodiments. Without departing from the said principles, the embodiments of the present invention may have any variations or modifications.

Claims

1. A data elastic buffer system based on a bus, characterized in that The system includes: APB bus; APB configuration register module; Data buffer structure; I2S control module; I2S bus; The data buffer structure is respectively communicatively connected to the APB configuration register module and the I2S control module. The APB configuration register module is connected to the APB bus, and the I2S control module is connected to the I2S bus. The APB configuration register module and the I2S control module establish a communication connection with the data buffer structure using a handshake protocol, and perform read and write operations in the data buffer structure through the handshake protocol; Among them, performing read and write operations in the data buffer structure through the handshake protocol includes the following steps: Obtain the status data in the data buffer structure, and determine whether it is valid data according to the status data; Generate a valid read or write enable according to the valid data; Convert the pointer of the valid read or write enable generated by the valid data into a Gray code through the handshake protocol, and synchronize the valid read or write enable from the current clock domain to the target clock domain according to the Gray code; After synchronizing to the target clock domain, simultaneously synchronize the valid read or write enable to the current clock domain to update the status of the data buffer structure; Judge whether there is valid data according to the status data of the updated data buffer structure again, and perform the next read or write synchronization operation.

2. The data elastic buffer system based on a bus according to claim 1, characterized in that The data buffer structure includes a data storage unit and a data synchronization unit, and the data storage unit is connected to the data synchronization unit; The data buffer structure further includes a write control unit and a read control unit. The write control unit and the read control unit are respectively communicatively connected to the data storage unit and the data synchronization unit, and the write control unit and the read control unit perform synchronization operations of writing data and reading data using a handshake protocol.

3. A data transmission method based on a bus, characterized in that, The data transmission method is applied to the bus-based data elastic buffer system according to any one of claims 1-2, and the method includes: Obtain the status data in the data buffer structure, and determine whether it is valid data according to the status data; Generate a valid read or write enable according to the valid data; Convert the pointer of the valid read or write enable generated by the valid data into a Gray code through the handshake protocol, and synchronize the valid read or write enable from the current clock domain to the target clock domain according to the Gray code; After synchronizing to the target clock domain, simultaneously synchronize the valid read or write enable to the current clock domain to update the status of the data buffer structure; Judge whether there is valid data according to the status data of the updated data buffer structure again, and perform the next read or write synchronization operation.

4. A data transmission method based on a bus according to claim 3, characterized in that, The status data of the data buffer structure includes empty, full, almost empty, almost full, read empty, and read full states, and the status data constitutes an interruption of data transmission in the buffer structure.

5. The data transmission method based on a bus according to claim 3, characterized in that, The data transmission method includes a data writing method: the APB configuration register module and the I2S control module input the data and write enable of the corresponding bus into the data buffer structure. If the data buffer structure detects external written data and determines that the current state in the data buffer structure is a full interrupt, the currently detected external written data is considered invalid data, and the corresponding input write enable is an invalid enable.

6. The data transmission method based on a bus according to claim 3, characterized in that, During data writing, the APB configuration register module and the I2S control module input the data and write enable of the corresponding bus into the data buffer structure. When the data buffer structure detects external written data, if it is determined that the current state in the buffer structure is a non-full state, the external written data is a valid write enable, and the corresponding external written data is valid data. The write enable is synchronized to the read clock domain through the handshake protocol and synchronized to the current write clock domain.

7. A data transmission method based on a bus according to claim 3, characterized in that, The APB configuration register module or the I2S control module inputs the data and read enable of the corresponding bus into the data buffer structure. If the data buffer structure detects external read data and determines that the current state in the data buffer structure is an empty interrupt, the currently detected external read data is considered invalid data, and the currently detected read enable is an invalid enable.

8. A data transmission method based on a bus according to claim 3, characterized in that, The data transmission method includes a readout method: the APB configuration register module or the I2S control module inputs the data and its own read enable of the corresponding bus into the data buffer structure. If the data buffer structure detects external read data and determines that the current state in the data buffer structure is a non-empty interrupt, the currently detected external read data is considered valid data, and the currently detected read enable is a valid enable. The corresponding external read enable is synchronized to the write clock domain through the handshake protocol and synchronized to the current read clock domain.

9. A data transmission method based on a bus according to claim 3, characterized in that, When synchronizing a valid read enable or write enable to the corresponding clock domain, the corresponding write pointer Gray code or read pointer Gray code is converted into binary data. The converted write pointer binary data is subtracted from the read pointer binary data, and the state data in the data buffer structure is regenerated based on the subtraction result and synchronized to the corresponding clock domain.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and the computer program can be executed by a processor to implement the bus-based data transmission method according to any one of claims 3-9.

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