Full adder circuit, chip, and computing device

Abstract

The embodiment of the present disclosure discloses a full adder circuit, a chip and a computing device, wherein the full adder circuit comprises a control module, a sum operation module and a carry value operation module; the control module is configured to receive a first value and a second value to be subjected to full addition operation and generate a control signal; the sum operation module is configured to receive an input carry value to be subjected to full addition operation, and perform logical operation on the input carry value according to the control signal to obtain a digit value of a sum of the first value and the second value; and the carry value operation module is configured to receive the input carry value and an input value, and perform logical operation on the input carry value and the input value according to the control signal to obtain a carry value of the sum of the first value and the second value. The embodiment of the present disclosure realizes the modularization of the circuit structure of the full adder, can realize the functions of each module by using fewer devices, and is helpful to reduce the power consumption, the occupied area and the signal transmission delay of the full adder circuit and improve the performance of the full adder circuit.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a full adder circuit, chip, and computing device. Background Technology

[0002] A full-adder is a combinational circuit that uses logic gates to add two binary numbers and calculate the sum; it is also called a one-bit full-adder. A one-bit full-adder can handle the carry from the least significant bit and output the carry from the current bit. Cascading multiple one-bit full-adders can produce a multi-bit full-adder.

[0003] In chip design, especially for data processing chips and computing chips, traditional adder logic circuits such as full adders and half adders are typically used to perform operations on binary numbers. When calculating the addition of two multi-bit numbers, multiple adders can usually be cascaded to form an adder array or adder tree. Due to the widespread and extensive use of adders in digital chip design, the performance of adders, including speed, power consumption, and area, is particularly important to the performance of digital chips. Summary of the Invention

[0004] Embodiments of this disclosure provide a full adder circuit, a chip, and a computing device.

[0005] According to one aspect of the present disclosure, a full adder circuit is provided, the circuit comprising: a control module, a sum operation module, and a carry operation module; the control module is configured to receive a first value and a second value to be added, and generate a control signal based on the first value and the second value; the sum operation module is configured to receive an input carry value to be added, and perform logical operations on the input carry value according to the control signal to obtain a digit value of the sum of the first value and the second value; the carry operation module is configured to receive an input carry value and an input value, and perform logical operations on the input carry value and the input value according to the control signal to obtain a carry value of the sum of the first value and the second value, wherein the input value includes the first value and / or the second value.

[0006] In some embodiments, the control module includes an XOR gate and a NAND gate; the XOR gate is used to perform an XOR operation on a first value and a second value to obtain a first control signal; the NAND gate is used to perform an NAND operation on bits of the first value and the second value to obtain a second control signal.

[0007] In some embodiments, the control module further includes a first amplitude expansion subunit and a second amplitude expansion subunit; the first amplitude expansion subunit is connected to the output of an XOR gate and is used to expand the amplitude of the level of the first control signal; the second amplitude expansion subunit is connected to the output of an XNOR gate and is used to expand the amplitude of the level of the second control signal.

[0008] In some embodiments, the sum calculation module includes an inverting unit and a first selection unit, and the carry calculation module includes a second selection unit. The inverting unit is used to perform an inverting operation on the input carry value; the first selection unit is used to select a value as the digit value of the sum from the input carry value and the inverted value output by the inverting unit according to the control signal; the second selection unit is used to select a value as the carry value of the sum from the input value and the input carry value according to the control signal.

[0009] In some embodiments, the first selection unit includes a first switch and a second switch, and the second selection unit includes a third switch and a fourth switch. The control terminals of the first, second, third, and fourth switches are used to receive control signals. The input terminal of the first switch is used to receive an input carry value, and the output terminal of the first switch is used to output the digit value of the sum. The second switch is connected in series with an inverting unit to control the inverted value of the input carry value to be output as the digit value of the sum. The input terminal of the third switch is used to receive an input carry value, and the output terminal of the third switch is used to output the carry value of the sum. The input terminal of the fourth switch is used to receive an input value, and the output terminal of the fourth switch is used to output the carry value of the sum.

[0010] In some embodiments, the first switch, the second switch, the third switch, and the fourth switch are switches of the transmission gate structure, respectively.

[0011] In some embodiments, the inverting unit includes a first inverter and a second inverter, which are connected in series, and the common output terminal of the first inverter and the second inverter is connected to the input terminal of the second switch.

[0012] According to another aspect of the present disclosure, a computing device is provided, the computing device including the above-described chip.

[0013] The full adder circuit, chip, and computing device provided in the above embodiments of this disclosure, by setting up a control module, a sum operation module, and a carry operation module, wherein the control module generates a control signal based on the first and second values ​​to be added, the sum operation module performs logical operations on the input carry value according to the control signal to obtain the digit value of the sum of the first and second values, and the carry operation module performs logical operations on the input carry value, the first value, and / or the second value according to the control signal to obtain the carry value of the sum of the first and second values, thereby realizing the modularization of the circuit structure of the full adder, which can use fewer components to implement the functions of each module, helps to reduce the power consumption, area occupied, and signal transmission delay of the full adder circuit, and improves the performance of the full adder circuit.

[0014] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0016] Figure 1 This is an exemplary schematic diagram of an existing 28T full adder.

[0017] Figure 2 This is a schematic diagram of the structure of a full adder circuit provided in an exemplary embodiment of this disclosure.

[0018] Figure 3 This is a schematic diagram of the structure of a full adder circuit provided in another exemplary embodiment of this disclosure.

[0019] Figure 4 This is a schematic diagram of the structure of the first selection unit and the second selection unit provided in an exemplary embodiment of this disclosure.

[0020] Figure 5 This is a schematic diagram of the structure of a 20T full adder circuit provided in another exemplary embodiment of this disclosure. Detailed Implementation

[0021] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0022] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0023] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0024] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0025] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0026] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0027] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0028] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0029] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0030] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0031] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0032] Application Overview

[0033] In chip design, traditional logic adder circuits such as full adders and half adders are typically used to perform calculations on binary numbers. When calculating the sum of two multi-bit numbers, multiple traditional adders are usually used. Table 1 below shows the truth table of a one-bit adder circuit. Ci-1 represents the carry input of the previous bit, Ai and Bi represent the two one-bit binary numbers to be added, Si represents the sum of the outputs, and Ci represents the carry output after the calculation. Ci can be used as the carry input of the next adder circuit.

[0034] Table 1

[0035]

[0036] Figure 1 This is a typical full adder commonly used in existing technical solutions, consisting of 28 MOSFETs. a and b are two one-bit binary inputs, c is the carry-in value from the previous stage, Si is the sum of the outputs, and Ci is the carry-out value from the outputs. Its logic function is the same as the corresponding input / output logic function in Table 1 above.

[0037] Figure 1The traditional typical adder shown has a total of 28 MOSFETs, including 14 PMOS and 14 NMOS, resulting in a relatively complex structure. To obtain the output Si, the longest path is affected by the inputs a, b, and c, passing through N1, N2, N3, N4, and N5, a total of 5 MOSFET delays. To obtain the carry-out Ci, the longest path is affected by the inputs a, b, and c, passing through P1, P2, and P3, a total of 3 MOSFET delays. Therefore, the existing technology has a complex circuit structure and logic, resulting in long delays for Si and Ci, and low performance. Furthermore, due to the large number of MOSFETs, including many dynamically switching ones, the existing technology has relatively large dynamic power consumption and area.

[0038] Exemplary Structure

[0039] Figure 2 This is a schematic diagram of a full adder circuit provided in an exemplary embodiment of this disclosure. The various components of this circuit are typically integrated into a single chip, but can also be disposed in discrete components, which establish data communication links between these discrete components.

[0040] Based on the logic truth table shown in Table 1 above, the full adder circuit provided in this embodiment can be obtained. This full adder circuit is usually included in the multi-bit data full adder circuit that performs full addition operation on multi-bit data. That is, the multi-bit data full adder circuit includes N full adder circuits, and each full adder circuit is used to calculate the sum of the corresponding two single-bit values.

[0041] like Figure 2 As shown, the full adder circuit includes: a control module 201, a sum operation module 202, and a carry operation module 203;

[0042] The control module 201 is used to receive the first value and the second value to be added, and to generate a control signal based on the first value and the second value.

[0043] In this context, both the first and second values ​​are single-bit binary numbers. As shown in Table 1 above, the first value is Ai, and the second value is Bi. The control signal can be a signal obtained by the control module performing operations on the first value Ai and the second value Bi according to a preset operation method. For example, the control module 201 may include an XOR gate, and the control signal is the signal output by the XOR gate.

[0044] The summation module 202 receives the input carry value to be added and performs logical operations on the input carry value according to the control signal to obtain the digit value of the sum of the first and second values. As shown in Table 1 above, Ci-1 is the input carry value, that is, the carry value from the (i-1)th bit value to the ith bit value when performing full addition on multi-bit data. Si is the digit value of the sum of the first value Ai and the second value Bi.

[0045] The carry-value calculation module 203 is used to receive the input carry-value and the input value, and perform logical operations on the input carry-value and the input value according to the control signal to obtain the carry-value of the sum of the first value and the second value. As shown in Table 1 above, the input value includes the first value Ai and / or the second value Bi.

[0046] As an example, the control module may include an XOR gate, and the control signal is the signal output by the XOR gate. That is, when Ai = 0, Bi = 0, or Ai = 1, Bi = 1, the control signal H = 0; when Ai = 0, Bi = 1, or Ai = 1, Bi = 0, H = 1.

[0047] Based on the truth table shown in Table 1 above, the following logical rules are obtained:

[0048] When Ai=Bi, H=0, Si=Ci-1, Ci=Ai or Bi;

[0049] When Ai≠Bi, H=1, Si=Ci-1B (i.e., the inverse value of Ci-1), Ci=Ci-1.

[0050] Therefore, a switching circuit can be set in the sum calculation module 202 to make Si and Ci-1 conduct when H=0; an inverter can also be set in the sum calculation module 202 to invert Ci-1 when H=1 to obtain Ci-1B, and make Ci-1B conduct with Si.

[0051] A switching circuit can be set in the carry-value calculation module 203. When H = 0, Ci is turned on with Ai and / or Bi, and when H = 1, Ci is turned on with Ci-1.

[0052] The circuit provided in the above embodiments of this disclosure, by setting a control module, a sum operation module, and a carry operation module, allows the control module to generate a control signal based on the first and second values ​​to be added. The sum operation module performs logical operations on the input carry value according to the control signal to obtain the digit value of the sum of the first and second values. The carry operation module performs logical operations on the input carry value, the first value, and / or the second value according to the control signal to obtain the carry value of the sum of the first and second values. This modularizes the circuit structure of the full adder, allowing the use of fewer components to implement the functions of each module. This helps to reduce the power consumption, area occupied, and signal transmission delay of the full adder circuit, and improves the performance of the full adder circuit.

[0053] In some optional implementations, the control module 201 includes an XOR gate 2011 and a NAND gate 2012. The XOR gate 2011 is used to perform an XOR operation on the first value and the second value to obtain a first control signal. The NAND gate 2012 is used to perform an NAND operation on the first value and the second value to obtain a second control signal.

[0054] The first control signal and the second control signal can be used simultaneously as control signals for the sum calculation module 202 and the carry value calculation module 203.

[0055] like Figure 3 As shown, the control module 201 includes an XOR gate 2011 and a NAND gate 2012 that output HB (i.e., the inverted value of H) and H respectively. HB and H are the first control signal and the second control signal, and also serve as control signals for the sum operation module 202 and the carry operation module 203.

[0056] like Figure 5 As shown, this diagram illustrates a full adder circuit implemented using MOS transistor combinational logic, comprising 20 MOS transistors; therefore, it can also be called a 20T adder circuit. In the diagram, P1, P2, N1, and N2 form an XOR gate, and P3, P4, N3, and N4 form a XNOR gate. The first and second output control signals are represented as HB and H, respectively.

[0057] This embodiment improves the stability of the circuit logic operation process and helps to improve the accuracy of addition operations by setting XOR gates and XNOR gates in the control module, which enable the sum value operation module and carry value operation module to be controlled by the first control signal and the second control signal, which are inversely phased values.

[0058] In some alternative implementations, the control module may also include a first amplitude extension subunit and a second amplitude extension subunit.

[0059] The first swing expansion subunit is connected to the output of the XOR gate and is used to expand the level swing of the first control signal. The second swing expansion subunit is connected to the output of the XNOR gate and is used to expand the level swing of the second control signal.

[0060] A full-swing circuit refers to a circuit where the highest voltage of the input and output signals can reach the full-swing power supply voltage, and the lowest voltage can reach the full-swing ground voltage. In this embodiment, the purpose of setting up a first and second swing extension subunit is to reduce the threshold loss of the levels corresponding to the first and second control signals, respectively, thereby achieving the effect of a full-swing circuit. Typically, the first and second swing extension subunits can be implemented in various ways, such as using components like MOSFETs or transistors to reduce threshold loss.

[0061] like Figure 5 As shown, it includes N5 and P5, which are the first swing expansion sub-unit and the second swing expansion sub-unit, respectively. N5 and P5 are NMOS transistors and PMOS transistors, respectively, and their input terminals are connected to each other's output terminals, thus achieving a complementary effect.

[0062] from Figure 5 As can be seen from this, when Ai≠Bi, HB=1, H=0, N5 and P5 are both cut off, the HB signal is set to high level (close to VDD) through P1 or P2, and the H signal is set to low level (close to VSS) through N3 or N4. The threshold loss of H and HB is very small.

[0063] When Ai and Bi are the same, HB = 0, H = 1, N5 is on, HB is connected to VSS, and the output is low. At the same time, P5 is also on, H is connected to VDD, and the output is high. Therefore, the levels of H and HB are close to VDD and VSS, respectively, reducing the threshold loss of H and HB.

[0064] This embodiment, by setting a first swing amplitude expansion subunit and a second swing amplitude expansion subunit in the control module, can effectively increase the level swing of the first control signal and the second control signal, reduce threshold loss, and make the levels of the first control signal and the second control signal more stable. This provides stable control signals for the control sum operation module and the carry operation module, thereby further improving the stability of the full adder circuit, that is, further improving the accuracy of the addition operation.

[0065] In some alternative implementations, such as Figure 3 As shown, the sum operation module 202 includes an inverting unit 2021 and a first selection unit 2022, and the carry operation module 203 includes a second selection unit 2031. The inverting unit 2021 is used to invert the input carry value. Optionally, the inverting unit can be composed of a NOT gate circuit.

[0066] The first selection unit 2022 is used to select a value as the digit value of the sum from the input carry value and the inverted value output by the inverting unit 2021 according to the control signal. The second selection unit 2031 is used to select a value as the carry value of the sum from the input value and the input carry value according to the control signal.

[0067] like Figure 3 As shown, the inverting unit 2021 receives the input carry value Ci-1 and outputs Ci-1B (i.e., the inverted value of Ci-1). The first selection unit 2022 and the second selection unit 2031 can be composed of a circuit simulating a single-pole double-throw switch. The first selection unit 2022 receives the input Ci-1 and Ci-1B, and the second selection unit 2031 receives the input Ai / Bi (i.e., the input value, either Ai or Bi) and Ci-1. The control module outputs a first control signal HB and a second control signal H. The first selection unit 2022 and the second selection unit 2031 select, based on H and HB, either output Ci-1 or Ci-1B as Si, and select either output Ai / Bi or Ci-1 as Ci.

[0068] The specific logical operation process is as follows:

[0069] When Ai=0, Bi=0, or Ai=1, Bi=1, H=1, HB=0, Si=Ci-1, Ci=Ai / Bi;

[0070] When Ai=0, Bi=1, or Ai=1, Bi=0, H=0, HB=1, Si=Ci-1B, Ci=Ci-1.

[0071] As can be seen from Table 1 above, the logic operation process conforms to the logic truth table shown in Table 1.

[0072] This embodiment achieves the output of the digit value and carry value of the sum of a full addition operation based on a simpler circuit by setting an inverting unit and a first selection unit in the sum operation module and a second selection unit in the carry operation module. This makes the full adder simpler to implement and improves the manufacturing efficiency of the full adder circuit and the calculation efficiency of binary numbers.

[0073] In some alternative implementations, such as Figure 4 As shown, the first selection unit 2022 includes a first switch 20221 and a second switch 20222, and the second selection unit 2031 includes a third switch 20311 and a fourth switch 20312. The control terminals of the first switch 20221, the second switch 20222, the third switch 20311 and the fourth switch 20312 are used to receive control signals.

[0074] The input terminal of the first switch 20221 is used to receive the input carry value Ci-1, and the output terminal of the first switch 20221 is used to output the digital value Si of the sum; the second switch 20222 is connected in series with the inverting unit 2021 and is used to control the inverted value Ci-1B of the input carry value as the digital value Si of the sum value to be output.

[0075] The input terminal of the third switch 20311 is used to receive the input carry value Ci-1, and the output terminal of the third switch 20311 is used to output the carry value Ci of the sum; the input terminal of the fourth switch 20312 is used to receive the input value Ai / Bi, and the output terminal of the fourth switch 20312 is used to output the carry value Ci of the sum.

[0076] Optionally, the first switch, the second switch, the third switch, and the fourth switch can all be single-input single-output switches, which are controlled to open or close by the control signal output by the control module.

[0077] like Figure 4 As shown, if the input module includes XOR gates and XNOR gates, and control signals H and HB control the state of each switch, then the specific logic operation flow is as follows:

[0078] When Ai = 0, Bi = 0, or Ai = 1, Bi = 1, H = 1, HB = 0, at this time, the first switch 20221 and the fourth switch 20312 are turned on, the second switch 20222 and the third switch 20311 are turned off, Si = Ci-1, Ci = Ai / Bi;

[0079] When An = 0 and Bn = 1, or An = 1 and Bn = 0, H = 0 and HB = 1. At this time, the first switch 20221 and the fourth switch 20312 are off, and the second switch 20222 and the third switch 20311 are on. Si = Ci-1B and Ci = Ci-1.

[0080] The logic operation process conforms to the logic truth table shown in Table 1.

[0081] This embodiment sets a first switch and a second switch in the first selection unit, and a third switch and a fourth switch in the second selection unit. The state of each switch is controlled by a control signal, thereby enabling the accurate output of the digit value and carry value of the sum of the first and second values ​​through a simple switching circuit. This helps to reduce the manufacturing difficulty of the circuit and improves the manufacturing efficiency and design flexibility of the full adder circuit.

[0082] In some alternative implementations, the first switch, second switch, third switch, and fourth switch are switches for the transmission gate structure. For example... Figure 5As shown, P6 and N6 form the first switch of the transmission gate structure, P9 and N10 form the second switch, P7 and N7 form the third switch, and P8 and N8 form the fourth switch. Since the switches in the transmission gate structure have two control terminals, this embodiment can combine the first and second control signals from the optional embodiments described above, allowing the first and second control signals to control the state of each switch.

[0083] like Figure 5 As shown, when Ai = Bi, H = 1, HB = 0, both the first and fourth switches are on, and Si = Ci-1, Ci = An / Bn; when Ai ≠ Bi, H = 0, HB = 1, both the first and fourth switches are off, and Si and Ci need to be transmitted by the second and third switches.

[0084] It should be noted that, Figure 5 The transmission gate structure shown is just an example. In practical applications, the first switch, second switch, third switch and fourth switch can also be constructed using transmission gates constructed in other ways.

[0085] This embodiment sets the first, second, third, and fourth switches as a transmission gate structure, which can effectively utilize the characteristics of the transmission gate, such as very low on-resistance, very high off-resistance, and output data level close to the full swing, thereby improving the stability of the full adder circuit and further improving the accuracy of addition operations.

[0086] In some alternative implementations, the inverting unit includes a first inverter and a second inverter connected in series, and the common output terminal of the first inverter and the second inverter is connected to the input terminal of the second switch.

[0087] The first inverter and the second inverter can be composed of various components, such as MOSFETs and transistors.

[0088] like Figure 5 As shown, P10 and N9 are the first inverter and the second inverter, respectively. P10 and N9 are connected in series, and P9 and N10 form the second switch. This embodiment can combine the first control signal and the second control signal from the optional embodiment above, and the state of each switch can be controlled by the first control signal and the second control signal.

[0089] When Ai≠Bi, H=0, HB=1, P9 and N10 (second switch) are both on, N7 and P7 (third switch) are both on. At this time, Si=Ci-1B, Ci=Ci-1;

[0090] When Ai = Bi, H = 1, HB = 0, and P9 and N10 are both cut off. At this time, Si and Ci are transmitted by the first switch (P6 and N6) and the fourth switch (P8 and N8).

[0091] Figure 5 The 20T full adder circuit shown requires only 20 MOSFETs to perform a full addition operation on a single bit of data, compared to the commonly used 28T adder. Existing technology requires 28 MOSFETs for the same operation. Therefore, Figure 5 The circuit shown has significantly reduced power consumption and area compared to existing technologies. Figure 5 The longest path for the digital value Si in the 20T full adder circuit shown is affected by the inputs Ai, Bi, and Ci-1, and is delayed by a total of three MOS transistors: P1, N9, N10 or N3, P9, P10. Figure 1 The traditional typical adder shown has two fewer stages of delay; the longest path for the output carry value Ci is affected by the inputs A, B, and Ci-1, and involves delays through two MOSFETs (P1 and N7 or N3 and P7), resulting in one fewer stage of delay than the existing traditional typical adder. Therefore, Figure 5 The signal transmission delay of the 20T full adder shown is greatly reduced, and the calculation speed is greatly improved.

[0092] This embodiment, by setting a first inverter and a second inverter connected in series, can achieve a stable output of the inverted value of the input carry value through simpler connections and a more compact arrangement between devices. This helps to simplify the wiring complexity of the circuit, thereby further reducing the area occupied by the full adder circuit and improving the stability of the full adder circuit.

[0093] Embodiments of this disclosure also provide a chip on which a full adder circuit is integrated. Technical details of the full adder circuit are as follows: Figures 2-5 As shown in the relevant descriptions, further details will not be provided here.

[0094] Embodiments of this disclosure also provide a computing device including the chip described in the above embodiments. Furthermore, the computing device may also include an input device, an output device, and necessary memory. The input device may include, for example, a mouse, keyboard, touchscreen, or communication network connector, for inputting a first value and a second value to be added. The output device may include, for example, a display, printer, and communication network and its connected remote output devices, for outputting the sum of the first and second values. The memory is used to store data input by the input device and data generated during the operation of the full adder circuit. The memory may include volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0095] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0096] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0097] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0098] The circuits of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps of the method in the circuit is for illustrative purposes only, and the steps of the method of this disclosure are not limited to the order specifically described above, unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the functions of the circuits according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the functions of the circuits according to this disclosure.

[0099] It should also be noted that in the circuits of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of this disclosure.

[0100] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0101] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A full adder circuit, comprising: The control module, the sum value operation module and the carry value operation module; The control module is configured to receive a first value and a second value to be subjected to a full add operation, and generate a control signal based on the first value and the second value; The sum value operation module is configured to receive an input carry value to be subjected to a full add operation, and perform a logical operation on the input carry value according to the control signal to obtain a digit value of a sum value of the first value and the second value; the sum value operation module comprises an inversion unit and a first selection unit, the inversion unit is configured to perform an inversion operation on the input carry value, and the first selection unit is configured to select a value from the input carry value and an inverted value output by the inversion unit as the digit value of the sum value according to the control signal; The carry value operation module is configured to receive the input carry value and an input value, and perform a logical operation on the input carry value and the input value according to the control signal to obtain a carry value of the sum value of the first value and the second value, wherein the input value comprises the first value and / or the second value; the carry value operation module comprises a second selection unit configured to select a value from the input value and the input carry value as the carry value of the sum value according to the control signal.

2. The circuit of claim 1, wherein, The control module comprises an exclusive OR gate and an exclusive NOR gate; The exclusive OR gate is configured to perform an exclusive OR operation on the first value and the second value to obtain a first control signal; The exclusive NOR gate is configured to perform an exclusive NOR operation on the first value and the second value to obtain a second control signal.

3. The circuit of claim 2, wherein, The control module further comprises a first swing expansion subunit and a second swing expansion subunit; The first swing expansion subunit is connected to an output end of the exclusive OR gate and is configured to expand a level swing of the first control signal; The second swing expansion subunit is connected to an output end of the exclusive NOR gate and is configured to expand a level swing of the second control signal.

4. The circuit of any one of claims 1-3, wherein, The first selection unit comprises a first switch and a second switch, and the second selection unit comprises a third switch and a fourth switch; control ends of the first switch, the second switch, the third switch and the fourth switch are configured to receive the control signal; An input end of the first switch is configured to receive the input carry value, and an output end of the first switch is configured to output the digit value of the sum value; the second switch is connected in series with the inversion unit and is configured to control an inverted value of the input carry value to be output as the digit value of the sum value; An input end of the third switch is configured to receive the input carry value, and an output end of the third switch is configured to output the carry value of the sum value; an input end of the fourth switch is configured to receive the input value, and an output end of the fourth switch is configured to output the carry value of the sum value.

5. The circuit of claim 4, wherein, The first switch, the second switch, the third switch and the fourth switch are switches in a transmission gate structure.

6. The circuit of claim 4, wherein, The inversion unit comprises a first inverter and a second inverter, the first inverter and the second inverter are connected in series, and a common output end of the first inverter and the second inverter is connected to an input end of the second switch.

7. A chip, characterized by A full adder circuit comprising any of claims 1-6.

8. A computing device, comprising: A chip comprising the full adder circuit of claim 7.

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