A memory repairable error reporting method, device, equipment and medium

Abstract

This invention discloses a method, apparatus, device, and medium for reporting recoverable memory errors, belonging to the field of data processing technology. The method is applied to an ARM architecture server, which includes several memory modules. The method includes: a system control processor obtaining the value of a recoverable memory error register via the I2C protocol; determining whether the value is a multiple of the initial recoverable memory error threshold set by the basic input / output system; and confirming whether to report the error to the operating system based on the determination result. This invention implements a similar memory recoverable error reporting scheme to x86 architecture servers on ARM architecture servers, improving the reporting mechanism when recoverable memory errors occur on ARM architecture servers. This facilitates physical replacement by maintenance personnel when memory modules on ARM architecture servers are confirmed to have errors, while also improving the performance of ARM architecture servers.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a method, apparatus, device, and medium for reporting memory-repairable errors. Background Technology

[0002] Currently, most data centers primarily use Intel and AMD chips with x86 architecture. However, as internet customers increasingly prioritize energy efficiency and cost-effectiveness, Advanced RISC Machine (ARM) servers are also gaining traction in data centers. This is because ARM architecture has more than twice the number of cores as traditional x86 processors, and it supports cloud services such as cloud gaming and web services. Therefore, the deployment of ARM architecture will continue to grow.

[0003] However, all data runs on the memory of any server architecture. If the memory is damaged, or if there are unrecoverable or recoverable errors, how to handle or report them is a key issue that needs to be considered. For the x86 architecture, the reporting mechanism is already very mature, but for the emerging ARM architecture processor, the memory error reporting mechanism is not yet perfect. Summary of the Invention

[0004] To overcome the aforementioned technical deficiencies, the present invention aims to provide a method, apparatus, device, and medium for reporting recoverable memory errors. The method is applied to an ARM architecture server, which includes several memory modules. The method includes: a system control processor obtaining the value of a recoverable memory error register via the I2C protocol; determining whether the value is a multiple of the initial recoverable memory error threshold set by the Basic Input / Output System; and confirming whether to report the error to the operating system based on the determination result. This invention implements a similar memory recoverable error reporting scheme to x86 architecture servers on ARM architecture servers, improving the reporting mechanism when recoverable memory errors occur on ARM architecture servers. This facilitates physical replacement by maintenance personnel when errors are confirmed in the memory modules of the ARM architecture server, while also improving the performance of the ARM architecture server.

[0005] The specific technical solutions provided by the embodiments of the present invention are as follows:

[0006] Firstly, a method for reporting recoverable memory errors is provided. This method is applied to an ARM architecture server, which includes several memory modules. The method includes:

[0007] The system control processor obtains the value of the memory-repairable error register via the I2C protocol;

[0008] Determine whether the value is a multiple of the initial threshold for memory-recoverable errors set by the Basic Input / Output System;

[0009] Based on the judgment result, determine whether to report to the operating system.

[0010] Furthermore, before obtaining the value of the memory-repairable error register, the process includes:

[0011] Enable the basic input / output system;

[0012] The basic input / output system sets the initial threshold for memory-recoverable errors to a first threshold.

[0013] Enter the operating system.

[0014] Furthermore, the step of determining whether to report to the operating system based on the judgment result includes:

[0015] When the value of the memory repairable error register is a multiple of the first threshold, the system control processor reports to the operating system via an interrupt through the power management interface.

[0016] The operating system records the number of times memory-repairable errors are reported.

[0017] Furthermore, the step of determining whether to report to the operating system based on the judgment result also includes:

[0018] When the value of the memory-repairable error register is not a multiple of the first threshold, the system control processor does not report to the operating system;

[0019] The system control processor retrieves the values ​​of the memory-repairable error register via the I2C protocol.

[0020] Furthermore, after confirming whether to report to the operating system based on the judgment result, the following steps are included:

[0021] Determine whether the operating system is shut down;

[0022] If so, then stop the reporting of memory-repairable errors;

[0023] If not, the system control processor retrieves the value of the memory repairable error register via the I2C protocol and determines whether to report it to the operating system based on the result.

[0024] Furthermore, the method for reporting recoverable memory errors also includes:

[0025] The recoverable errors of each memory module of the ARM architecture server are reported separately, and each report carries the identifier of the memory module that caused the recoverable error.

[0026] The number of repairable errors reported by each memory module is determined based on the memory module identifier;

[0027] The corresponding memory module handling mechanism is determined based on the number of recoverable errors reported by each memory module.

[0028] Furthermore, the mechanism for determining the corresponding memory module handling based on the number of repairable errors reported by each memory module includes:

[0029] If the number of repairable error reports for any memory module exceeds the second threshold within a first unit of time, a memory module error alarm will be issued to prompt the physical replacement of the memory module.

[0030] If the number of repairable error reports for any memory module within the second unit of time is less than the third threshold and the operating system does not crash, then the repairable error reports are ignored and the ARM architecture server continues to run its services.

[0031] Secondly, a memory repairable error reporting device is provided, the device comprising:

[0032] The acquisition module is used by the system control processor to obtain the value of the memory repairable error register via the I2C protocol;

[0033] The judgment module is used to determine whether the value is a multiple of the initial threshold for memory-repairable errors set by the basic input / output system;

[0034] The processing module is used to determine whether to report to the operating system based on the judgment result.

[0035] Thirdly, a computer device is provided, the device comprising:

[0036] A memory, a processor, and a computer program stored on the memory, wherein the processor executes the computer program to implement the steps of the memory-repairable error reporting method as described in any of the first aspects.

[0037] Fourthly, a computer storage medium is provided, the medium comprising:

[0038] It stores a computer program that, when executed by the memory, implements the steps of the memory-repairable error reporting method described in any of the first aspects.

[0039] Compared with existing technologies, the method described in this invention is applied to an ARM architecture server, which includes several memory modules. The method includes: a system control processor obtaining the value of a memory recoverable error register via the I2C protocol; determining whether the value is a multiple of the initial threshold for memory recoverable errors set by the basic input / output system; and confirming whether to report the error to the operating system based on the determination result. This invention is the first to implement a memory recoverable error reporting scheme similar to that of an x86 architecture server on an ARM architecture server, improving the reporting mechanism when recoverable errors occur in the memory of an ARM architecture server. This facilitates maintenance personnel in physically replacing memory modules when errors are confirmed to have occurred on the ARM architecture server, while also improving the performance of the ARM architecture server.

[0040] The ARM architecture server provided in this embodiment of the invention supports a mechanism for separately reporting repairable errors for each memory module of the server, rather than a mechanism for reporting all repairable errors of the memory modules together. This allows for the identification of which memory module has a physical defect based on the separate error reporting, thereby improving system stability and adding the function of analyzing and locating physical defects in memory modules. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a first flowchart of the memory repairable error reporting method provided in Embodiment 1 of the present invention;

[0043] Figure 2 This is a second flowchart of the memory repairable error reporting method provided in Embodiment 2 of the present invention;

[0044] Figure 3 This is a flowchart illustrating the memory repairable error reporting method provided in Embodiment 2 of the present invention.

[0045] Figure 4 This is a structural diagram of the memory repairable error reporting device provided in Embodiment 3 of the present invention;

[0046] Figure 5 This is an exemplary system provided in Embodiment 5 of the present invention, which can be used to implement the various embodiments described in this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0048] It should be noted that, unless the context explicitly requires it, the words "comprising," "including," and similar terms in the entire specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0049] Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0050] Example 1

[0051] This invention provides a method for reporting recoverable memory errors, such as... Figure 1 As shown, the method is applied to an ARM architecture server, which includes several memory modules. The method includes:

[0052] The system control processor obtains the value of the memory-repairable error register via the I2C protocol;

[0053] Determine whether the value is a multiple of the initial threshold for memory-recoverable errors set by the Basic Input / Output System;

[0054] Based on the judgment result, determine whether to report to the operating system.

[0055] Specifically, the ARM architecture server has a total of 8 memory controllers, namely 8 microcontroller units (MCUs). Here, we take 1 memory controller as an example to describe the functional implementation. The error reporting mechanism implemented by the other 7 memory controllers is the same as the memory repairable error reporting method here. The only difference is that each memory controller counts and reports separately.

[0056] The Basic Input Output System (BIOS) sets the memory recoverability threshold in its code. The initial value is the first threshold by default. When the operating system runs, the System Control Processor (SCP) reads the value of the memory recoverability error register via the I2C protocol and determines whether the current value of the memory recoverability error register is a multiple of the first threshold. If the value of the memory recoverability error register is not a multiple of the first threshold, it continues to re-polulate and read the value of the memory recoverability error register. If the value of the memory recoverability error register is a multiple of the first threshold, it reports it to the operating system via the Advanced Configuration and Power Management Interface (ACPI) interrupt. At the same time, the operating system logs the information to record that a memory recoverability error has occurred. When the operating system is not shut down, the system control processor continues to poll and read the value of the memory recoverable error register. If the value of the memory recoverable error register is a multiple of the first threshold, it continues to report to the operating system through the power management interface to inform that another recoverable error reporting record has been triggered. The processor polls and reads the value of the memory recoverable error register in turn, and determines whether the value is a multiple of the initial threshold for memory recoverable errors set by the basic input / output system. Based on the determination result, it determines whether to report to the operating system until the operating system shuts down.

[0057] This invention, in its embodiments, sets an initial threshold for recoverable errors for each memory segment of the memory controller using a Basic Input / Output System (PIS). A method for reporting recoverable memory errors is employed, where the System Control Processing Unit (SCP) reads the value of the recoverable memory register and determines whether the value is a multiple of the initial threshold. Based on this determination, a decision is made whether to report the error to the Operating System (OS). This reporting process is performed sequentially until the system is shut down, at which point no further reporting is initiated. The number of reports indicates the frequency of recoverable memory errors. Furthermore, by setting a reporting mechanism that only occurs when the error reaches a multiple of the initial threshold, the number of recoverable error reports can be effectively reduced while still ensuring error reporting.

[0058] The technical solution provided in this invention is applied to ARM architecture servers. The protection point of this invention is that after the BIOS sets the initial threshold for recoverable memory errors, the system control processor (SCP) reads the value of the recoverable memory error register via I2C and determines whether the value of the register is a multiple of the initial threshold set by the BIOS to decide whether to report the number of recoverable memory errors. This invention is the first to implement a memory recoverable error reporting scheme similar to that of x86 architecture servers on ARM architecture servers, improving the reporting mechanism when recoverable errors occur in the memory of ARM architecture servers. This facilitates physical replacement by maintenance personnel when a memory module in an ARM architecture server is confirmed to be faulty, while also improving the performance of the ARM architecture server.

[0059] Example 2

[0060] This invention provides a method for reporting recoverable memory errors, such as... Figure 2 As shown, the method is applied to an ARM architecture server, which includes several memory modules. The method includes:

[0061] Step S01: Enable the basic input / output system;

[0062] The basic input / output system sets the initial threshold for memory-recoverable errors to a first threshold.

[0063] Enter the operating system.

[0064] Specifically, the first threshold here is 5.

[0065] The Basic Input / Output System (BIOS) defaults to a memory-recoverable error initial threshold of 5. It then boots normally and enters the operating system.

[0066] In step S02, the system control processor obtains the value of the memory repairable error register via the I2C protocol.

[0067] The system control processor (SCP) reads the values ​​of the memory-repairable error registers via the I2C protocol.

[0068] Step S03: Determine whether the value is a multiple of the initial threshold for memory-repairable errors set by the basic input / output system.

[0069] Specifically, it is determined whether the value of the memory repairable error register is a multiple of 5.

[0070] Step S04: Based on the judgment result, confirm whether to report to the operating system.

[0071] Step S04 also includes:

[0072] Step S041: When the value of the memory repairable error register is a multiple of the first threshold, the system control processor reports to the operating system via an interrupt through the power management interface.

[0073] The operating system records the number of times memory-repairable errors are reported.

[0074] Specifically, when the value of the memory repairable error register is a multiple of 5, the system control processor SCP reports to the operating system via the power management interface ACPI in an interrupt manner.

[0075] The operating system records the number of recoverable memory errors, that is, it records the number of times a recoverable memory error occurs. Here, the number of recoverable memory errors recorded by the operating system is equivalent to the number of times a recoverable memory error is actually reported.

[0076] Step S042: When the value of the memory repairable error register is not a multiple of the first threshold, the system control processor does not report to the operating system.

[0077] The system control processor retrieves the values ​​of the memory-repairable error register via the I2C protocol.

[0078] Specifically, when the value of the memory repairable error register is not a multiple of 5, the system control processor does not report it to the operating system;

[0079] The system control processor retrieves the value of the repairable error register in memory via the I2C protocol and determines whether the current value of the repairable error register is a multiple of 5.

[0080] It is understandable that the ARM architecture server itself does not support the reporting mechanism for recoverable errors (CEs) in memory. However, since the data is stored on physical memory modules, if the stored data is incorrect or a recoverable error occurs on the memory module but is not reported to the operating system, the system may crash or freeze.

[0081] However, when a recoverable memory error occurs, it's difficult to pinpoint whether the problem stems from the memory module itself or an error occurring during data transfer within the memory. Therefore, for example, by setting the recoverable memory error threshold to 10000 or 50000 via the Basic Input / Output System (PIS), when the value of the recoverable memory error register reaches 10000 or 50000, the system control processor reports this to the operating system via an interrupt through the power management interface. The operating system records the number of recoverable memory error reports. When the value of the recoverable memory error register does not reach 10000 or 50000, the system control processor does not report this to the operating system; instead, the system control processor retrieves the value of the recoverable memory error register again via the I2C protocol.

[0082] Step S05: Determine whether the operating system is powered off;

[0083] If so, then stop the reporting of memory-repairable errors;

[0084] If not, the system control processor retrieves the value of the memory repairable error register via the I2C protocol and determines whether to report it to the operating system based on the result.

[0085] Specifically, when the value of the memory repairable error register is a multiple of 5, the system control processor SCP reports to the operating system via the power management interface ACPI in an interrupt manner; the operating system records the number of memory repairable errors and sequentially reads the value until the operating system shuts down.

[0086] Step S06: Report the repairable errors of each memory stick of the ARM architecture server separately, and carry the identifier of the memory stick that caused the repairable error with each report;

[0087] The number of repairable errors reported by each memory module is determined based on the memory module identifier;

[0088] The corresponding memory module handling mechanism is determined based on the number of recoverable errors reported by each memory module;

[0089] If the number of repairable error reports for any memory module exceeds the second threshold within a first unit of time, a memory module error alarm will be issued to prompt the physical replacement of the memory module.

[0090] If the number of repairable error reports for any memory module within the second unit of time is less than the third threshold and the operating system does not crash, then the repairable error reports are ignored and the ARM architecture server continues to run its services.

[0091] Specifically, the ARM architecture server supports a mechanism for separately reporting repairable errors for each memory module of the server, rather than a mechanism for reporting all repairable errors of the memory modules together. This allows the system to identify which memory module has a physical defect based on the separate error reports, thereby improving system stability and adding the ability to analyze and locate physical defects in memory modules.

[0092] If the system reports 100 or 200 records within 1 hour, it is considered that there is a problem with the physical memory module, and the reported memory module needs to be physically replaced. If the number of reports is less than 2 within 1 hour or less than 1 within 24 hours and there is no system downtime, the system ignores the repairable error report and the ARM architecture server continues to run the customer's business.

[0093] Wherein, the first unit of time is 1 hour; the second threshold is 100 times or 200 times; the second unit of time is 24 hours; and the third threshold is 1 time.

[0094] like Figure 3 The diagram shows a flowchart of a method for reporting corrective errors (CE) in memory. This invention relates to a method for reporting corrective errors (CE) in memory on an ARM architecture server. Since ARM architecture server processors support eight memory controllers and the corrective error reporting mechanism of microcontrollers (MCUs) is the same, only one memory controller is used as an example for explanation. The basic input / output system sets the initial threshold for corrective errors in memory to 5 and starts the operating system (OS). At this time, the system control processor (SCP) reads the value of the corrective error register through the I2C protocol and judges whether the value of the corrective error register is a multiple of 5. If it is not a multiple of 5, it continues to read the value of the corrective error threshold register. If it is a multiple of 5, the system control processor (SCP) reports to the operating system (OS) via the power management interface (ACPI) in the form of an interrupt, records one corrective error reporting, and sequentially re-reads the value of the corrective error register until the operating system shuts down.

[0095] The embodiments of this invention have strong replicability and scalability. By setting an initial threshold for recoverable memory errors through the Basic Input / Output System (BIOS), the System Control Processor (SCP) reads the value of the recoverable memory register via the I2C protocol and determines whether the value of the recoverable memory register is a multiple of the initial threshold for recoverable memory errors set by the BIOS. Based on the determination result, it decides whether to report to the operating system (OS) via the ACPI interrupt method of the power management interface. The polling and reporting mechanism stops after the system is shut down to realize the reporting of the number of recoverable memory errors.

[0096] The method for reporting recoverable memory errors provided in this embodiment of the invention can be improved and optimized in several ways without departing from the technical solution of this invention, and these improvements and optimizations should also be considered within the scope of protection of this invention.

[0097] This invention provides a method for reporting recoverable memory errors. The technical solution provided is applied to an ARM architecture server. The method includes: a system control processor obtaining the value of a recoverable memory error register via the I2C protocol; determining whether the value is a multiple of the initial recoverable memory error threshold set by the Basic Input / Output System; and confirming whether to report to the operating system based on the determination result. This invention is the first to implement a memory recoverable error reporting scheme similar to that of an x86 architecture server on an ARM architecture server. It improves the reporting mechanism when recoverable memory errors occur on an ARM architecture server, facilitating physical replacement by maintenance personnel when a memory module error is confirmed, and simultaneously improving the performance of the ARM architecture server.

[0098] The ARM architecture server provided in this embodiment of the invention supports a mechanism for separately reporting repairable errors for each memory module of the server, rather than a mechanism for reporting all repairable errors of the memory modules together. This allows for the identification of which memory module has a physical defect based on the separate error reporting, thereby improving system stability and adding the function of analyzing and locating physical defects in memory modules.

[0099] The technical solution provided by the embodiments of the present invention improves the performance of ARM architecture servers. The present invention is only applicable to ARM architecture servers and only applied to ARM architecture server products, which is more conducive to large-scale procurement and deployment of ARM architecture servers by Internet customers.

[0100] Example 3

[0101] This invention provides a memory repairable error reporting device, such as... Figure 4 As shown, the device includes a pre-processing module, an acquisition module, a judgment module, and a processing module.

[0102] In this embodiment, the preprocessing module is used to enable the Basic Input / Output System (PIOS), which sets the initial threshold for recoverable memory errors to a first threshold, and then enters the operating system; the acquisition module is used by the system control processor to acquire the value of the recoverable memory error register via the I2C protocol; the judgment module is used to determine whether the value is a multiple of the initial threshold for recoverable memory errors set by the PIOS; and the processing module is used to determine whether to report to the operating system based on the judgment result.

[0103] Furthermore, the processing module is configured to, when the value of the memory repairable error register is a multiple of the first threshold, have the system control processor report to the operating system via an interrupt through the power management interface;

[0104] The operating system records the number of times memory-repairable errors are reported.

[0105] Furthermore, the processing module is also configured to prevent the system control processor from reporting to the operating system when the value of the memory repairable error register is not a multiple of the first threshold.

[0106] The system control processor retrieves the values ​​of the memory-repairable error register via the I2C protocol.

[0107] Furthermore, the determination module can also be used to determine whether the operating system is powered off;

[0108] If so, then stop the reporting of memory-repairable errors;

[0109] If not, the system control processor retrieves the value of the memory repairable error register via the I2C protocol and determines whether to report it to the operating system based on the result.

[0110] Furthermore, the processing module is also used to report the repairable errors of each memory module of the ARM architecture server separately, and to carry the identifier of the memory module that generated the repairable error with each report; to determine the number of repairable errors reported by each memory module based on the memory module identifier; and to determine the corresponding memory module processing mechanism based on the number of repairable errors reported by each memory module.

[0111] Furthermore, the processing module is also used to issue a memory module error alarm when the number of repairable error reports of any memory module within a first unit of time exceeds a second threshold, so as to prompt the physical replacement of the memory module;

[0112] If the number of repairable error reports for any memory module within the second unit of time is less than the third threshold and the operating system does not crash, then the repairable error reports are ignored and the ARM architecture server continues to run its services.

[0113] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows:

[0114] The technical solution provided by this invention implements a reporting scheme for recoverable memory errors similar to that of x86 architecture servers for the first time on ARM architecture servers. It improves the reporting mechanism when recoverable errors occur in the memory of ARM architecture servers, making it easier for maintenance personnel to physically replace the memory modules when an error is confirmed in the ARM architecture server, while also improving the performance of ARM architecture servers.

[0115] The ARM architecture server provided in this embodiment of the invention supports a mechanism for separately reporting repairable errors for each memory module of the server, rather than a mechanism for reporting all repairable errors of the memory modules together. This allows for the identification of which memory module has a physical defect based on the separate error reporting, thereby improving system stability and adding the function of analyzing and locating physical defects in memory modules.

[0116] Example 4

[0117] This invention provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it can perform the following method for reporting memory-repairable errors:

[0118] The system control processor obtains the value of the memory-repairable error register via the I2C protocol;

[0119] Determine whether the value is a multiple of the initial threshold for memory-recoverable errors set by the Basic Input / Output System;

[0120] Based on the judgment result, determine whether to report to the operating system.

[0121] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows:

[0122] The technical solution provided by this invention implements a reporting scheme for recoverable memory errors similar to that of x86 architecture servers for the first time on ARM architecture servers. It improves the reporting mechanism when recoverable errors occur in the memory of ARM architecture servers, making it easier for maintenance personnel to physically replace the memory modules when an error is confirmed in the ARM architecture server, while also improving the performance of ARM architecture servers.

[0123] Example 5

[0124] This invention provides a computer storage medium, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it performs the following steps:

[0125] The system control processor obtains the value of the memory-repairable error register via the I2C protocol;

[0126] Determine whether the value is a multiple of the initial threshold for memory-recoverable errors set by the Basic Input / Output System;

[0127] Based on the judgment result, determine whether to report to the operating system.

[0128] Furthermore, before obtaining the value of the memory-repairable error register, the process includes:

[0129] Enable the basic input / output system;

[0130] The basic input / output system sets the initial threshold for memory-recoverable errors to a first threshold.

[0131] Enter the operating system.

[0132] Furthermore, the step of determining whether to report to the operating system based on the judgment result includes:

[0133] When the value of the memory repairable error register is a multiple of the first threshold, the system control processor reports to the operating system via an interrupt through the power management interface.

[0134] The operating system records the number of times memory-repairable errors are reported.

[0135] Furthermore, the step of determining whether to report to the operating system based on the judgment result also includes:

[0136] When the value of the memory-repairable error register is not a multiple of the first threshold, the system control processor does not report to the operating system;

[0137] The system control processor retrieves the values ​​of the memory-repairable error register via the I2C protocol.

[0138] Furthermore, after confirming whether to report to the operating system based on the judgment result, the following steps are included:

[0139] Determine whether the operating system is shut down;

[0140] If so, then stop the reporting of memory-repairable errors;

[0141] If not, the system control processor retrieves the value of the memory repairable error register via the I2C protocol and determines whether to report it to the operating system based on the result.

[0142] Furthermore, the method for reporting recoverable memory errors also includes:

[0143] The recoverable errors of each memory module of the ARM architecture server are reported separately, and each report carries the identifier of the memory module that caused the recoverable error.

[0144] The number of repairable errors reported by each memory module is determined based on the memory module identifier;

[0145] The corresponding memory module handling mechanism is determined based on the number of recoverable errors reported by each memory module.

[0146] Furthermore, the mechanism for determining the corresponding memory module handling based on the number of repairable errors reported by each memory module includes:

[0147] If the number of repairable error reports for any memory module exceeds the second threshold within a first unit of time, a memory module error alarm will be issued to prompt the physical replacement of the memory module.

[0148] If the number of repairable error reports for any memory module within the second unit of time is less than the third threshold and the operating system does not crash, then the repairable error reports are ignored and the ARM architecture server continues to run its services.

[0149] Figure 5 This is an exemplary system provided in Embodiment 5 of the present invention that can be used to implement the various embodiments described in this application;

[0150] like Figure 5 As shown, in some embodiments, the system can function as any of the aforementioned devices for reporting memory-repairable errors in each of the described embodiments. In some embodiments, the system may include one or more computer-readable media (e.g., system memory or NVM / storage device) having a result and one or more processors (e.g., one or more processors) coupled to the one or more computer-readable media and configured to execute the result to implement the module thereby performing the actions described in this application.

[0151] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program using related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0152] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for reporting memory repairable error, characterized in that, The method is applied to an ARM architecture server including a plurality of memory banks, and the method comprises: The system control processor acquires the value of the memory correctable error register through the I2C protocol; It is judged whether the value is a multiple of the initial threshold value of the memory correctable error set by the basic input / output system; It is determined whether to report to the operating system according to the judgment result; The determination whether to report to the operating system according to the judgment result comprises: When the value of the memory correctable error register is a multiple of the first threshold value, the system control processor reports to the operating system in an interrupt mode through the power management interface; The operating system records the number of memory correctable error reports; When the value of the memory correctable error register is not a multiple of the first threshold value, the system control processor does not report to the operating system; The system control processor reacquires the value of the memory correctable error register through the I2C protocol; The method further comprises: The correctable errors of each memory bank of the ARM architecture server are reported separately, and the memory bank identifier generating the correctable error is carried each time the correctable error is reported; The number of correctable errors reported by each memory bank is determined according to the memory bank identifier; The corresponding memory bank processing mechanism is determined according to the number of correctable errors reported by each memory bank.

2. The method of claim 1, wherein, Before the value of the memory correctable error register is acquired, it comprises: The basic input / output system is started; The basic input / output system sets the initial threshold value of the memory correctable error as the first threshold value; The operating system is entered.

3. The method of claim 1, wherein the memory repairable error reporting method is characterized by, After it is determined whether to report to the operating system according to the judgment result, it comprises: It is judged whether the operating system is shut down; If yes, the memory correctable error reporting operation is stopped; If no, the system control processor reacquires the value of the memory correctable error register through the I2C protocol and judges, and determines whether to report to the operating system according to the judgment result.

4. The method of claim 1, wherein the memory repairable error reporting method is characterized by, When the number of correctable errors reported by any memory bank in a first unit of time is greater than a second threshold value, an error alarm of the memory bank is issued to prompt the physical replacement of the memory bank; When the number of correctable errors reported by any memory bank in a second unit of time is less than a third threshold value and the operating system has no dead machine phenomenon, the correctable error reporting problem is ignored, and the ARM architecture server continues to operate the business. The device comprises:

5. A memory repairable error reporting device for implementing the method of claim 1, characterized by An acquisition module for the system control processor to acquire the value of the memory correctable error register through the I2C protocol; A judgment module for judging whether the value is a multiple of the initial threshold value of the memory correctable error set by the basic input / output system; A processing module for determining whether to report to the operating system according to the judgment result. The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 4.

6. A computer device comprising a memory, a processor, and a computer program stored on the memory, wherein the computer program comprises instructions that, when executed by the processor, cause the processor to perform the method of any one of claims 1-5. The computer program is executed by the memory to implement the steps of the method according to any one of claims 1 to 4.

7. A computer storage medium having stored thereon a computer program, characterized in that ​

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