Delay simulation method and device, electronic equipment and computer readable medium

Abstract

The present disclosure provides a delay simulation method, which comprises: determining a delay buffer time of an event based on a preset delay time and a network-on-chip transmission delay time; wherein the event is pulse firing information between neurons; and writing the event into a delay slot of a delay buffer and placing it in a slot position corresponding to the delay buffer time. The present disclosure also provides a delay simulation device, an electronic device and a computer readable medium.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of brain simulation, and in particular to a delay simulation method and device, an electronic device, and a computer readable medium. BACKGROUND

[0002] The development of computational neuroscience has had a significant impact on the fields of intelligent science, cognitive science, information processing, and artificial intelligence, and has also promoted the combination of artificial intelligence and brain science.

[0003] A many-core system is a hardware device for implementing brain simulation. With the increase in the number of cores and the increase in the complexity of on-chip interconnection in the many-core system, there is a time delay between neurons (also referred to as event transmission delay between neurons) when the many-core system performs brain simulation. SUMMARY

[0004] The present disclosure provides a delay simulation method, device, electronic device, and computer readable medium.

[0005] In a first aspect, the present disclosure provides a delay simulation method, the delay simulation method comprising:

[0006] determining a delay buffer time of an event based on a preset delay time and an on-chip network transmission delay time; wherein the event is pulse firing information between neurons;

[0007] writing the event into a delay slot of a delay buffer area and placing it in a slot position corresponding to the delay buffer time.

[0008] In a second aspect, the present disclosure provides a delay simulation device, the delay simulation device comprising:

[0009] a first determining module configured to determine a delay buffer time of an event based on a preset delay time and an on-chip network transmission delay time;

[0010] a delay buffer module configured to write the event into a delay slot of a delay buffer area and place it in a slot position corresponding to the delay buffer time.

[0011] In a third aspect, the present disclosure provides an electronic device, the electronic device comprising: a plurality of processing cores; and an on-chip network configured to interact data between the plurality of processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and the one or more instructions are executed by the one or more processing cores to cause the one or more processing cores to perform the delay simulation method described above.

[0012] In a fourth aspect, the present disclosure provides a computer readable medium having a computer program stored thereon, wherein the computer program, when executed by a processing core, implements the delay simulation method described above.

[0013] The delay simulation method, apparatus, electronic device, and computer-readable medium provided in this disclosure determine the delay buffer time of an event based on a preset delay time and an on-chip network transmission delay time, and write the event into a delay slot of the delay buffer and place it in a slot corresponding to the delay buffer time. This can simulate the event transmission delay between neurons, thereby promoting the development and research of many-core systems.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0015] The accompanying drawings are provided to further understand the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the present disclosure and do not constitute a limitation thereof.

[0016] The above and other features and advantages will become more apparent to those skilled in the art from the detailed example embodiments described with reference to the accompanying drawings, in which:

[0017] Figure 1 This is a schematic diagram illustrating the event transmission delay between neurons in an embodiment of this disclosure;

[0018] Figure 2 This is a diagram illustrating an application scenario of delayed simulation according to an embodiment of this disclosure;

[0019] Figure 3 A flowchart of a delayed simulation method provided in this disclosure embodiment;

[0020] Figure 4 A block diagram illustrating the composition of a delay buffer provided in an embodiment of this disclosure;

[0021] Figure 5 A block diagram of a delay simulation device provided in this disclosure embodiment;

[0022] Figure 6 A block diagram illustrating the composition of another delay buffer provided in an embodiment of this disclosure;

[0023] Figure 7 A flowchart of another delayed simulation method provided in this disclosure embodiment;

[0024] Figure 8 A block diagram of another delay simulation apparatus provided in this disclosure embodiment;

[0025] Figure 9 A flowchart of another delayed simulation method provided in this disclosure embodiment;

[0026] Figure 10 A schematic diagram for a one-to-many case of neurons in embodiments of the present disclosure;

[0027] Figure 11 A constituent block diagram of a delay simulation device provided by embodiments of the present disclosure;

[0028] Figure 12 A constituent block diagram of an electronic device provided by embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] For those skilled in the art to better understand the technical solutions of the present disclosure, the following describes exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to help understanding, which should be considered only as exemplary. Therefore, those of ordinary skill in the art should realize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, for the sake of clarity and conciseness, the description below omits the description of well-known functions and structures.

[0030] In the case of no conflict, each embodiment of the present disclosure and each feature in the embodiments can be combined with each other.

[0031] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprise" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The terms "connected" or "coupled" and / or like terms are not limited to a direct connection or coupling, but also include an indirect connection or coupling, whether or not it is physical, mechanical, electrical, and / or the like.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0034] Neurons are the basic structural and functional units of the nervous system, and synapses are the interconnection positions of two neurons, which are the key positions for information transmission between neurons. Synaptic transmission events require a certain time, that is, there is a delay in the transmission of events from one neuron to the target neuron. This delay is referred to as event transmission delay between neurons in this embodiment.

[0035] When brain simulation is performed using a many-core system, the time difference between the event transmitted by neuron X to neuron Y is usually referred to as delay time, which is a parameter that can be set. In some embodiments, the delay time can be discrete data, such as any integer greater than 0, etc.

[0036] Figure 1 A schematic diagram of the event transmission delay between neurons in an embodiment of the present disclosure is shown. Referring to Figure 1 , neuron X sends events to neuron Y, neuron Z, …, neuron N, wherein the delay time of the event sent by neuron X to neuron Y is dA, and the delay time of the event sent by neuron X to neuron Z is dB. Wherein, the delay times dA and dB can be pre-set.

[0037] In a first aspect, the present disclosure provides a delay simulation method for simulating the delay time of event transmission between neurons.

[0038] Figure 2 An application scenario diagram of a delay simulation of an embodiment of the present disclosure is shown. Referring to Figure 2 , the many-core system includes two first cores 21 and second cores 22, wherein the first core 21 includes at least one neuron, such as neuron X1, and the second core 22 includes at least one neuron, such as neuron Y. A delay buffer 23 is provided between the first core 21 and the second core 22 for delaying the time of event entering the second core 22, and an on-chip network transmission area 24 is a transmission medium for neurons from the first core 21 to the second core 22. The delay time of the on-chip network transmission area 24 can be obtained by calculation. For example, the delay time of the on-chip network transmission area 24 is obtained by calculating the difference between the timestamp ts of the event and the current time t.

[0039] Figure 3 A flowchart of a delay simulation method provided by an embodiment of the present disclosure is shown. Referring to Figure 2 and Figure 3 The delay simulation method provided by the embodiment of the present disclosure includes:

[0040] In step S301, the delay buffer time of the event is determined based on the pre-set delay time and the on-chip network transmission delay time; wherein the event is the pulse firing information between neurons.

[0041] The delay time refers to the time difference between the time when the neuron X1 sends the event and the time when the neuron Y1 receives the event. The on-chip network transmission delay time refers to the time spent by the event in the on-chip network transmission in the many-core system.

[0042] In some embodiments, the delay time of the event sent by the neuron X1 to the neuron Y1 is dA, which includes the on-chip network transmission delay time dN and the delay buffer time dy, i.e., dA = dN + dy. The delay time dA can be preset. The on-chip network transmission delay time dN can be obtained by calculation. For example, the on-chip network transmission delay time dN can be determined by the difference between the time stamp ts of the event sent by the neuron X1 and the current time, i.e., dN = t-ts.

[0043] In step S302, the event is written into the delay slot of the delay buffer, and is placed in the slot corresponding to the delay buffer time.

[0044] The delay buffer is used to buffer the time when the event is received by the target neuron. The target neuron is the neuron that receives the event. For example, as shown in FIG. 2, the neuron Y provided in the second core 22 is the target neuron. When the event is transmitted from the neuron X1 to the neuron Y1, the delay buffer can be used to delay the time when the event enters the neuron Y1. Figure 2

[0045] The delay simulation method provided by the embodiments of the present disclosure can simulate the transmission delay of the event by determining the delay buffer time of the event based on the preset delay time and the on-chip network transmission delay time, writing the event into the delay slot of the delay buffer, and placing the event in the slot corresponding to the delay buffer time.

[0046] Figure 4 A composition block diagram of the delay buffer provided by the embodiments of the present disclosure is shown in FIG. 3. Figure 4 As shown in FIG. 3, at least one delay slot is provided in the delay buffer, and the value of the slot position represents the delay time. The delay time of each slot position is different. In some embodiments, the slot positions of the delay slot increase from right to left.

[0047] For example, the delay slot includes n slot positions. The value of the slot position on the rightmost side is “0”, which means that the event with a delay buffer time of 0 can be written into the slot position with the value of “0”. The slot position with the value of “1” can write the event with a delay buffer time of “1”, the slot position with the value of “2” can write the event with a delay buffer time of “2”, and so on.

[0048] ​In some embodiments, the delay buffer time is counted in units of "ticks", each tick can be 1 millisecond or 1 microsecond, or 2 milliseconds or 2 microseconds. When the delay buffer time is counted in units of "ticks", each slot of the delay slot delays for the delay buffer time of "ticks". For example, a value of "1" corresponds to a slot that can write an event with a delay buffer time of "1 tick".

[0049] In some embodiments, as shown in Figure 5 The delay buffer area includes a first input delay buffer area 53A, which is arranged on the side of the input neuron, i.e., the first input delay buffer area 53A is arranged on the side of the second core 52. The first input delay buffer area 53A includes a delay slot, the structure of which is shown in Figure 4

[0050] In this embodiment, each slot of the delay slot can write a preset number of events, where the preset number can be one or more.

[0051] For the convenience of description, in this embodiment, the delay buffer time is counted in units of "ticks", and the absolute time length of each time tick can be set as needed. In addition, the delay buffer time can also be counted in other time units.

[0052] In step S302, an event is written into the delay slot of the delay buffer area, and is placed in the slot corresponding to the delay buffer time.

[0053] In an alternative implementation, the processing method of step S302 described above can be various, and an alternative processing method is provided below, and the specific processing process of the following steps is described in detail.

[0054] In some embodiments, the delay buffer area includes an input delay buffer area, and the input delay buffer area includes a first input delay buffer area. An event is written into the delay slot of the first input delay buffer area, and each delay slot slot writes a preset number of events, such as one or more events.

[0055] In some embodiments, when the delay buffer time of an event is determined, the number of ticks of the delay buffer is also determined, and the event is written into the corresponding slot of the delay slot according to the number of ticks.

[0056] For example, when the delay buffer time of an event is determined to be 2 ticks, the event is written into the 2nd slot of the delay slot.

[0057] In this embodiment, when each slot of the delay slot can only write one event, when the slot is occupied by an event, other events with the same delay buffer time as the event cannot be written into the delay slot.

[0058] ​For example, when the first slot of the delay slot has written event A with a delay buffer time of 1 beat, if event B also has a delay buffer time of 1 beat, event B cannot be written to the first slot of the delay slot. If event B has a delay buffer time of 2 beats, event B can be written to the second slot of the delay slot.

[0059] In some embodiments, when each slot of the delay slot can write multiple events, each slot is not exclusively occupied by one event, but can be simultaneously written by multiple events. For example, when the delay buffer time of events A, B and C is 1 beat, events A, B and C can be simultaneously written to the first slot of the delay slot.

[0060] As shown in Figure 6 , the delay time of events numbered 1, 5 and 8 is 1 beat, and events numbered 1, 5 and 8 can be written to the first slot of the delay slot. The delay time of events numbered 2, 4 and 6 is 3 beats, and events numbered 2, 4 and 6 can be written to the third slot of the delay slot.

[0061] In some embodiments, multiple first input delay buffer areas can be provided, and each first input delay buffer area can correspond to one neuron.

[0062] Figure 5 A composition block diagram of a delay simulation device provided by an embodiment of the present disclosure is provided. As shown in Figure 5 , first input delay buffer areas 53A and 53B are provided at the input end of the second core 52, wherein the first input delay buffer areas 53A and 53B can correspond to different neurons, i.e., events emitted by neurons in the first core 51 can be written to different first input buffer areas according to different target objects. For example, events with a target object of neuron Y are written to the first input delay buffer area 53A, and events with a target object of neuron Z are written to the first input delay buffer area 53B.

[0063] For example, when the delay buffer time of an event emitted by neuron X and transmitted to neuron Y is 1 beat, the event is written to the first slot of the delay slot in the first input delay buffer area 53A. When the delay buffer time of an event emitted by neuron X and transmitted to neuron Z is 3 beats, the event is written to the third slot of the delay slot in the first input delay buffer area 53A.

[0064] In some embodiments, as shown in Figure 5 , the delay simulation device further includes a second input buffer area 55 for storing events sent to the second core 52.

[0065] Based on Figure 5 the delay simulation device, in step S302, the event is written to the delay slot of the delay buffer area and placed before the slot corresponding to the delay buffer time, further comprising:

[0066] In the case that the first input delay buffer has no free space, the event is written into the second input delay buffer.

[0067] In the case that the first input delay buffer has no free space, the event is written into the second input delay buffer 55, and after being delayed for a certain time in the second input delay buffer 55, the event is written into the first input delay buffer 53A, 53B.

[0068] Figure 7 A flowchart of another delay simulation method provided by an embodiment of the present disclosure. Referring to Figure 5 and Figure 7 , the delay simulation method comprises:

[0069] Step S701, determining the delay buffer time of the event based on the preset delay time and the on-chip network transmission delay time.

[0070] Step S701 is the same as step S301, and will not be described here.

[0071] Step S702, judging whether the first input delay buffer has free space.

[0072] In the case that the first input delay buffer has no free space, all delay slots in the first input delay buffer are written with events, and there is no free slot position to write events. Alternatively, a slot position of the delay slots in the first input delay buffer is written with events, and the number of events stored in the slot position has reached the preset upper limit, and the slot position cannot write events with the same delay buffer time.

[0073] In some embodiments, it is judged whether the slot position corresponding to the delay buffer time of the event in the delay slot of the first input delay buffer has free space. If there is free space, it can be considered that the first input delay buffer has free space; if there is no free space, it can be considered that the first input delay buffer has no free space.

[0074] In the case that the delay simulation device comprises a first input delay buffer, each event of the neuron sent to the second core 52 is buffered in the first input delay buffer. If the delay slot of the first input delay buffer has no free space, the event cannot be written into the first input delay buffer.

[0075] It should be noted that since the delay slots of the first input delay buffer are multiple, and the delay time corresponding to each delay slot is different, the event sent to the second core 52 can be buffered in any first input delay buffer.

[0076] Step S703, in the case that the first input delay buffer has no free space, the event is written into the second input delay buffer.

[0077] In the case that there is no free slot in the first input delay buffer, the event is written into the second input delay buffer 55, and in the case that there is a corresponding free slot in the first input delay buffer, the event is written into the first input delay buffer.

[0078] In some embodiments, in the case that there is no free slot in the first input delay buffer corresponding to the delay buffer time, the event is written into the second input delay buffer.

[0079] For example, the first input delay buffer includes a first slot and a second slot, the first slot can be used to buffer events with a delay buffer time of 1 beat, and the second slot can be used to buffer events with a delay buffer time of 2 beats. If the second slot has been occupied, i.e., there is no free slot in the second slot, other events with a delay buffer time of 2 beats can be written into the second input delay buffer. Other events with a delay buffer time of 1 beat can still be written into the first slot of the first input delay buffer.

[0080] In step S704, the event is written into the delay slot of the first input delay buffer and placed in the slot corresponding to the delay buffer time.

[0081] It should be noted that the sum of the delay time of the event in the second input delay buffer 55 and the delay time of the first input delay buffer 53 is equal to the delay buffer time of the event. For example, when the delay buffer time of the event is 5 beats, since there is no free slot in the first input delay buffer 53, the event is first written into the second input delay buffer 55, and then written into the first input delay buffer 53 when there is a free slot in the first input delay buffer 53. If the event has been delayed for 2 beats in the second input delay buffer 55, the event can be delayed for 3 beats in the first input delay buffer 53, and thus the event is written into the third slot of the delay slot of the first input delay buffer 53.

[0082] The embodiment can reduce the space of the first input delay buffer because the event can be delayed in the second input delay buffer, and the space of the first input delay buffer can be saved simultaneously because the second input delay buffer can write multiple events at the same time.

[0083] Figure 8 Another composition block diagram of the delay simulation device provided by the embodiment of the present disclosure is provided. Referring to Figure 8The delay simulation device includes a first core 71, a second core 72, a first input delay buffer 73, an on-chip network transmission area 74, and an output delay buffer 75. The first input delay buffer 73 is arranged at the input side of the second core 72, the output delay buffer 75 is arranged at the output side of the first core 71, and the on-chip network transmission area 74 is arranged between the first input delay buffer 73 and the output delay buffer 75. Moreover, the delay simulation device is provided with a plurality of first input delay buffers 73, such as first input delay buffers 73A, 73B, and 73C, corresponding to neurons Y, Y, and N in the second core 72, respectively. That is, events sent from neuron X1 in the first core 71 to neurons Y, Y, and N in the second core 72 are written into the first input delay buffer 73A, the first input delay buffer 73B, and the first input delay buffer 73C, respectively.

[0084] In some embodiments, the delay buffer includes Figure 7 In the case of the output delay buffer shown in FIG. 3, the step S302 of writing the event into the delay slot of the delay buffer and placing it before the slot corresponding to the delay buffer time further includes: writing the event into the output delay buffer and writing the event into the input delay buffer after waiting for the common delay buffer time in the output delay buffer.

[0085] Specifically, Figure 9 Another flowchart of a delay simulation method provided by the embodiments of the present disclosure is provided. The delay simulation method can be used in a one-to-many case, such as sending events from neuron X to neurons Y, Z, and N. Referring to FIG. 4, the delay simulation method includes the following steps. Figure 8 and Figure 9 The delay simulation method includes the following steps.

[0086] In step S901, the delay buffer time of the event is determined based on the preset delay time and the on-chip network transmission delay time.

[0087] Step S901 is the same as step S301, and will not be described here.

[0088] In step S902, a plurality of events are written into the output delay buffer and wait for the common delay buffer time in the output delay buffer.

[0089] The common delay buffer time refers to the time when a plurality of events are simultaneously delayed. For example, if neuron X1 in the first core 71 sends three events, the delay times of the three events are 3, 4, and 5, respectively. The three events can be delayed together for 1, 2, or 3, and the time of being delayed together is the common delay buffer time. It should be noted that the common delay buffer time is less than or equal to the minimum number of beats in the three events.

[0090] For example, as shown in FIG. 7, neuron X1 sends events to neuron Y, neuron Z and neuron N, and the preset delay times of the three events are 10 ticks, 15 ticks and 12 ticks respectively. The three events are first written into the output delay buffer 75, delayed for 5 ticks in the output delay buffer 75, and then input into the first input delay buffer 73A, 73B and 73C. Figure 8 Figure 10 For example, as shown in FIG. 7, neuron X1 sends events to neuron Y, neuron Z and neuron N, and the preset delay times of the three events are 10 ticks, 15 ticks and 12 ticks respectively. The three events are first written into the output delay buffer 75, delayed for 5 ticks in the output delay buffer 75, and then input into the first input delay buffer 73A, 73B and 73C.

[0091] In step S903, a plurality of events are written into delay slots of the first input delay buffer, and one event is written into each slot.

[0092] In this embodiment, the delay buffer time can be determined by dA = dx + dy + dN, where dA is the preset delay time, dx is the common delay time, dy is the delay buffer time, and dN is the delay time of the network on chip.

[0093] For example, neuron X1 in the first core 71 sends events to neuron Y, neuron Z and neuron N in the second core 72, and the preset delay times of the three events are 10 ticks, 15 ticks and 12 ticks respectively. The common delay time of the output delay buffer 74 is 5 ticks, and the delay times dN of the network on chip transmission area 75 are 2 ticks, 3 ticks and 4 ticks respectively. Then, the delay buffer times dy are 3 ticks, 7 ticks and 3 ticks respectively.

[0094] In the case of one-to-many, the events can be commonly delayed for a period of time in the output delay buffer 74 to reduce the space of the first input delay buffer, and the space of the first input delay buffer 73A, 73B and 73C can be saved.

[0095] In some embodiments, after the event is written into the delay slot of the delay buffer and placed in the slot corresponding to the delay buffer time, the event in the delay buffer is further transmitted to the target computing unit at a preset time before the end of the delay buffer time.

[0096] The preset time can be the previous time before the end of the delay buffer time, and the previous time can be one clock cycle of the target computing unit. The previous time before the end of the delay buffer time can refer to one clock cycle of the target computing unit before the end of the delay buffer time.

[0097] ​In the embodiments of the present disclosure, the target computing unit can be a short form of a target synapse and neuron computing unit, and the event is transmitted to the target computing unit for processing after being buffered in the slot corresponding to the delay buffer. It should be noted that the target computing unit can be a processing unit of a many-core system for brain simulation, and the target neuron can be a destination of event transmission in the nervous system.

[0098] In some embodiments, the event includes event data and / or an axon identifier corresponding to the event.

[0099] The event data can refer to the pulse firing information transmitted from one neuron to another neuron. The axon identifier can be the code of the axon, and the axon identifier includes but is not limited to the axon number.

[0100] In some embodiments, the delay buffer time is in units of time ticks. Each tick can be 1 millisecond or 1 microsecond, or 2 milliseconds or 2 microseconds, which is not limited in the present disclosure.

[0101] In some embodiments, before determining the delay buffer time of the event based on the preset delay time and the network-on-chip transmission delay time, the method further includes: determining the network-on-chip transmission delay time based on the timestamp and the current time.

[0102] For example, the network-on-chip transmission delay time is calculated according to the difference between the timestamp of the event and the current time. When the timestamp of the event is ts and the current time is t, the value of t-ts is the network-on-chip transmission delay time.

[0103] The delay simulation method provided by the present embodiment determines the delay buffer time of the event based on the preset delay time and the network-on-chip transmission delay time, writes the event into the delay slot of the delay buffer, and places it in the slot corresponding to the delay buffer time. The delay of the event transmission between neurons during brain simulation can be simulated, thereby promoting the development and research of the many-core system.

[0104] The delay simulation method provided by the embodiments of the present disclosure is based on the same idea. The present disclosure further provides a delay simulation device for the delay time of data transmission between neurons during brain simulation.

[0105] Figure 11 The composition block diagram of the delay simulation device provided by the embodiments of the present disclosure is shown in Figure 11 The delay simulation device includes:

[0106] The first determining module 1101 is configured to determine a delay buffer time of event transmission information based on a preset delay time and an on-chip network transmission delay time, wherein the event is inter-neuron pulse firing information.

[0107] In the embodiments of the present disclosure, the delay buffer area includes an input delay buffer area, and the input delay buffer area includes a first input delay buffer area.

[0108] The delay buffer module 1102 is configured to write the event into a delay slot of the first input delay buffer area, and a slot position of each delay slot writes a preset number of events.

[0109] In the embodiments of the present disclosure, the input delay buffer area further includes a second input delay buffer area, and the apparatus further includes:

[0110] The first writing module is configured to write the event into the second input delay buffer area when the first input delay buffer area has no free space.

[0111] In the embodiments of the present disclosure, the delay buffer area includes an output delay buffer area, and the apparatus further includes:

[0112] The second writing module is configured to write the event into the output delay buffer area, and write the event into the input delay buffer area after waiting for a common delay buffer time in the output delay buffer area.

[0113] In the embodiments of the present disclosure, the apparatus further includes:

[0114] The event transmission module is configured to transmit the event in the delay buffer area to a target computing unit at a preset time before the end of the delay buffer time.

[0115] In the embodiments of the present disclosure, the event includes event data and / or an axon identifier corresponding to the event.

[0116] In the embodiments of the present disclosure, the delay buffer time is counted in time ticks.

[0117] In the embodiments of the present disclosure, the apparatus can further include:

[0118] The second determining module is configured to determine the on-chip network transmission delay buffer time based on a timestamp and a current time.

[0119] The application provides an application service processing device, which determines an event delay buffer time based on a preset delay time and an on-chip network transmission delay time, writes an event into a delay slot of a delay buffer, and is placed in a slot position corresponding to the delay buffer time, so that the event transmission delay between neurons during brain simulation can be simulated, thereby promoting the development and research of a many-core system.

[0120] The delay simulation device provided by the embodiments of the present disclosure can implement each process in the embodiments corresponding to the delay simulation method described above, and thus details are not repeated here.

[0121] It should be noted that the delay simulation device provided by the embodiments of the present disclosure and the delay simulation method provided by the embodiments of the present disclosure are based on the same inventive concept, and thus the specific implementation of this embodiment can be referred to the implementation of the foregoing delay simulation method, and details are not repeated.

[0122] Corresponding to the delay simulation method provided by the above embodiments, based on the same technical concept, the embodiments of the present disclosure also provide an electronic device, which can be used to execute the delay simulation method described above, Figure 12 The present disclosure provides a constituent block diagram of an electronic device.

[0123] Referring to Figure 12 The present disclosure provides an electronic device, which includes a plurality of processing cores 1201 and an on-chip network 1202, wherein the plurality of processing cores 1201 are connected with the on-chip network 1202, and the on-chip network 1202 is used to interact data between the plurality of processing cores and external data.

[0124] Among the one or more processing cores 1201, one or more instructions are stored, and the one or more instructions are executed by the one or more processing cores 1201, so that the one or more processing cores 1201 can execute the delay simulation method described above.

[0125] In addition, the present disclosure also provides a computer readable medium having a computer program stored thereon, wherein the computer program is executed by the processing core to implement the delay simulation method described above.

[0126] Those of ordinary skill in the art will realize and understand that all or some of the steps in the methods disclosed above and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, it is common technical knowledge that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

[0127] Example embodiments have been disclosed herein and, although the use of specific terms is expressly used herein, they are intended in a generic sense only and are not intended to limit the scope of the present disclosure. In some instances, it will be apparent to those skilled in the art that features, characteristics or / and elements described in connection with a particular embodiment can be used in conjunction with other embodiments unless otherwise explicitly stated. As such, those skilled in the art will appreciate that various changes can be made in form and detail without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A delayed simulation method, comprising: The delay buffer time of an event is determined based on a preset delay time and an on-chip network transmission delay time; wherein, the event is pulse firing information between neurons; The event is written into a delay slot of the delay buffer and placed in the slot corresponding to the delay buffer time; The delay buffer includes an input delay buffer and an output delay buffer. The step of writing the event into a delay slot of the delay buffer and placing it before the slot corresponding to the delay buffer time further includes: For any one of the multiple events, the event is written to the output delay buffer, and after waiting for a common delay buffer time in the output delay buffer, it is written to the input delay buffer; wherein, the common delay buffer time is the time for the multiple events to be delayed and buffered simultaneously, and the common delay buffer time has multiple selectable values.

2. The delay simulation method according to claim 1, wherein, The input delay buffer includes a first input delay buffer; The step of writing the event into a delay slot of the delay buffer and placing it in the slot corresponding to the delay buffer time includes: The events are written to the delay slots of the first input delay buffer, and a preset number of events are written to each delay slot.

3. The delay simulation method according to claim 2, wherein, The input delay buffer also includes a second input delay buffer; The step of writing the event into a delay slot of the delay buffer and placing it before the slot corresponding to the delay buffer time further includes: If the first input delay buffer is not free, the event is written to the second input delay buffer.

4. The delay simulation method according to claim 1, wherein, After writing the event into the delay slot of the delay buffer and placing it in the slot corresponding to the delay buffer time, the method further includes: At a preset time before the end of the delay buffer period, the events in the delay buffer are transmitted to the target computing unit.

5. The delay simulation method according to claim 1, wherein, The event includes event data and / or the axon identifier corresponding to the event.

6. The delay simulation method according to claim 1, wherein, The delay buffer time is measured in time ticks.

7. The delay simulation method according to claim 1, wherein, Before determining the delay buffer time of the event based on the preset delay time and the on-chip network transmission delay time, the method further includes: The on-chip network transmission delay time is determined based on the timestamp and the current time.

8. A delay simulation device, comprising: The first determining module is configured to determine the delay buffer time of the event based on a preset delay time and on-chip network transmission delay time; The delay buffer module is configured to write the event into a delay slot of the delay buffer and place it in a slot corresponding to the delay buffer time; The delay buffer includes an input delay buffer and an output delay buffer. The step of writing the event into a delay slot of the delay buffer and placing it before the slot corresponding to the delay buffer time further includes: For any one of the multiple events, the event is written to the output delay buffer, and after waiting for a common delay buffer time in the output delay buffer, it is written to the input delay buffer; wherein, the common delay buffer time is the time for the multiple events to be delayed and buffered simultaneously, and the common delay buffer time has multiple selectable values.

9. An electronic device, comprising: Multiple processing cores; as well as The on-chip network is configured to interact with data between the multiple processing cores and external data; One or more processing cores store one or more instructions, and the one or more instructions are executed by one or more processing cores to cause one or more processing cores to perform the delayed simulation method of any one of claims 1-7.

10. A computer-readable medium having a computer program stored thereon, wherein, The computer program, when executed by the processing core, implements the delayed simulation method as described in any one of claims 1-7.

Images