Pixel driving circuit, display panel and electronic device
By introducing storage capacitors and compensation units into the AMOLED display circuit, the problems of reduced brightness, screen flicker, and color shift caused by TFT leakage at low screen refresh rates have been solved, achieving higher display brightness and stability.
Patent Information
- Application Number
- CN202210700012.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-20
- Publication Date
- 2026-02-17
- Estimated Expiration
- 2042-06-20
AI Technical Summary
Existing AMOLED display circuits suffer from reduced brightness, screen flicker, and color shift issues due to TFT leakage at low screen refresh rates.
A pixel driving circuit is employed, including a storage capacitor, a charging unit, a compensation unit, a reset unit, a writing unit, and a driving unit. By charging the second node to the compensation voltage during the light-emitting holding phase, the voltage difference between the first node and the second node is reduced, thereby reducing leakage current.
It improves the brightness of AMOLED displays and avoids screen flickering and color shift when switching screen refresh rates.
Smart Images
Figure CN115035852B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of integrated circuits, specifically relating to a pixel driving circuit, a display panel, and an electronic device. Background Technology
[0002] AMOLED (Active Matrix / Organic Light Emitting Diode) display circuits include OLED (Organic Light-Emitting Diode) pixel driving circuits, which consist of multiple thin-film transistor (TFT) driving switches. The pixel driving circuit typically employs a 7T1C pixel compensation circuit, where input signals include: control signal EM, scan signals Scann and Scann-1, reset voltage signals VINT1 and VINT2, and pixel data signals Data.
[0003] The pixel driving process of the 7T1C pixel driving circuit consists of two parts within one frame: one data write to the organic light-emitting diode (OLED) and multiple data hold operations. During the data hold process, leakage current exists in some TFTs, causing a decrease in the display brightness of the OLED.
[0004] Especially when the screen refresh rate is lower, the data is retained for a longer time, the leakage is more serious, resulting in lower display brightness of the organic light-emitting diode, and screen flickering and color deviation when the screen refresh rate is switched. Summary of the Invention
[0005] The purpose of this application is to provide a pixel driving circuit, a display panel, and an electronic device that can solve the leakage problem caused by low screen refresh rate.
[0006] In a first aspect, embodiments of this application provide a pixel driving circuit, including:
[0007] A storage capacitor, wherein a first terminal of the storage capacitor is connected to a first power supply voltage and a second terminal of the storage capacitor is connected to a first node;
[0008] The charging unit, whose connection node with the storage capacitor is the first node, is connected to a first voltage and a first scan signal, and is used to write the first voltage to the first node during the charging phase.
[0009] A compensation unit is connected to a compensation voltage and a light emission signal. The connection node between the compensation unit and the charging unit is a second node. The compensation unit is used to charge the second node to the compensation voltage during the light emission holding phase.
[0010] A reset unit is connected to a second voltage and a second scan signal. The reset unit is connected to the first electrode of the light-emitting element. The reset unit is used to reset the light-emitting element during the reset phase.
[0011] The writing unit is connected to a data voltage and the second scan signal, and the writing unit is used to write the data voltage into the first node during the data writing phase;
[0012] A driving unit is connected to a first power supply voltage and a light emission signal. The driving unit, the charging unit, and the writing unit are all connected to the first node. The driving unit is used to provide driving current to the light emission element.
[0013] The first electrode of the light-emitting element is connected to the driving unit, and the second electrode of the light-emitting element receives a second power supply voltage.
[0014] Secondly, embodiments of this application provide a pixel driving circuit, including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a storage capacitor, and a light-emitting element;
[0015] The first terminal of the storage capacitor is connected to the first power supply voltage, and the connection point between the second terminal of the storage capacitor and the fourth transistor is the first node.
[0016] The gate of the first transistor is connected to the second terminal of the storage capacitor through the first node, the source of the first transistor is connected to the drain of the fifth transistor, and the drain of the first transistor is connected to the source of the third transistor.
[0017] The gate of the second transistor is connected to the second scan signal, the source of the second transistor is connected to the data voltage, and the drain of the second transistor is connected to the drain of the fifth transistor.
[0018] The gate of the third transistor is connected to the second scan signal, the source of the third transistor is connected to the source of the sixth transistor, and the drain of the third transistor is connected to the source of the fourth transistor.
[0019] The gate of the fourth transistor is connected to the first scan signal, the source of the fourth transistor is connected to the second terminal of the storage capacitor at the first node, and the connection node between the drain of the fourth transistor and the drain of the ninth transistor is the second node.
[0020] The gate of the fifth transistor is connected to the light-emitting signal, the source of the fifth transistor is connected to the first power supply voltage, and the drain of the fifth transistor is connected to the source of the first transistor.
[0021] The gate of the sixth transistor is connected to the light-emitting signal, the source of the sixth transistor is connected to the drain of the first transistor, and the drain of the sixth transistor is connected to the first electrode of the light-emitting element.
[0022] The gate of the seventh transistor is connected to the second scan signal, the source of the seventh transistor is connected to the second voltage, and the drain of the seventh transistor is connected to the first electrode of the light-emitting element.
[0023] The gate of the eighth transistor is connected to the first scan signal, the source of the eighth transistor is connected to the first voltage, and the drain of the eighth transistor is connected to the drain of the fourth transistor.
[0024] The gate of the ninth transistor is connected to a light-emitting signal, and the source of the ninth transistor is connected to a compensation voltage.
[0025] Thirdly, embodiments of this application provide a display panel including the pixel driving circuit described in the first or second aspect above.
[0026] Fourthly, embodiments of this application provide an electronic device including a display panel as described in the third aspect above.
[0027] In this embodiment, the connection node between the charging unit and the storage capacitor is the first node, and the connection node between the compensation unit and the charging unit is the second node. The compensation unit is used to charge the second node to the compensation voltage during the light-emitting holding stage, thereby raising the voltage of the second node to the compensation voltage. The voltage difference between the first node and the second node is reduced, which can reduce the leakage current of the corresponding components, improve the display brightness of the light-emitting diode, and avoid display flickering and color deviation caused by screen refresh rate switching. Attached Figure Description
[0028] Figure 1 This is a block diagram of the pixel driving circuit according to an embodiment of this application.
[0029] Figure 2 This is a circuit structure diagram of the pixel driving circuit according to an embodiment of this application.
[0030] Figure 3 This is a signal timing diagram of the pixel driving circuit in an embodiment of this application. Detailed Implementation
[0031] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.
[0032] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0033] The pixel driving circuit, display panel, and electronic device provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.
[0034] like Figure 1 As shown, this application embodiment provides a pixel driving circuit, including:
[0035] A storage capacitor, wherein a first terminal of the storage capacitor is connected to a first power supply voltage and a second terminal of the storage capacitor is connected to a first node;
[0036] The charging unit, whose connection node with the storage capacitor is the first node, is connected to a first voltage and a first scan signal, and is used to write the first voltage to the first node during the charging phase.
[0037] A compensation unit is connected to a compensation voltage and a light emission signal. The connection node between the compensation unit and the charging unit is a second node. The compensation unit is used to charge the second node to the compensation voltage during the light emission holding phase.
[0038] A reset unit is connected to a second voltage and a second scan signal. The reset unit is connected to the first electrode of the light-emitting element. The reset unit is used to reset the light-emitting element during the reset phase.
[0039] The writing unit is connected to a data voltage and the second scan signal, and the writing unit is used to write the data voltage into the first node during the data writing phase;
[0040] A driving unit is connected to a first power supply voltage and a light emission signal. The driving unit, the charging unit, and the writing unit are all connected to the first node. The driving unit is used to provide driving current to the light emission element.
[0041] The first electrode of the light-emitting element is connected to the driving unit, and the second electrode of the light-emitting element receives a second power supply voltage.
[0042] Now for reference Figure 2 , Figure 1 This is a circuit structure diagram of the pixel driving circuit according to an embodiment of this application.
[0043] like Figure 2 As shown, the pixel driving circuit 100 of this application embodiment includes a storage capacitor 12. The first end of the storage capacitor 12 is connected to the first power supply voltage ELVDD, and the second end of the storage capacitor 12 is connected to the first node, i.e., point A.
[0044] Optionally, the charging unit includes:
[0045] The fourth transistor has its gate connected to the first scan signal, and the connection node between the source of the fourth transistor and the second terminal of the storage capacitor is the first node;
[0046] The eighth transistor has its gate connected to the first scan signal, its source connected to the first voltage, and its drain connected to the drain of the fourth transistor.
[0047] like Figure 2 As shown, the gate of the fourth transistor T4 is connected to the first scan signal scann-1, and the connection node between the source of the fourth transistor T4 and the second terminal of the storage capacitor 12 is the first node A.
[0048] The gate of the eighth transistor T8 is connected to the first scan signal Scan n-1, the source is connected to the first voltage VINT1, and the drain is connected to the drain of the fourth transistor T4.
[0049] When the eighth transistor T8 is turned on, the first voltage VINT1 is input to the drain of the fourth transistor T4 through the source and drain of the eighth transistor T8. At this time, the potential at point B is also the potential of the first voltage VINT1.
[0050] Optionally, the compensation unit includes a ninth transistor, the gate of which is connected to a light-emitting signal, the source of which is connected to the compensation voltage, and the connection node between the drain of the ninth transistor and the drain of the fourth transistor is the second node.
[0051] like Figure 2As shown, the gate of the ninth transistor T9 is connected to the light-emitting signal EM, the source is connected to the compensation voltage V1, and the connection node between the drain of the ninth transistor T9 and the drain of the fourth transistor T4 is the second node B.
[0052] When the ninth transistor T9 is turned on, the compensation voltage V1 is written to the drain of the fourth transistor T4 through the source and drain of the ninth transistor T9. At this time, the potential at point B is also the potential of the compensation voltage V1.
[0053] Optionally, the reset unit includes a seventh transistor, the gate of which is connected to the second scan signal, the source of which is connected to the second voltage, and the drain of which is connected to the first electrode of the light-emitting element.
[0054] like Figure 2 As shown, the gate of the seventh transistor T7 is connected to the second scan signal Scan n, the source is connected to the second voltage VINT2, and the drain is connected to the first terminal of a light-emitting element, such as a light-emitting diode 14.
[0055] Optionally, the writing unit includes:
[0056] The second transistor has its gate connected to the second scan signal, its source connected to the data voltage, and its drain connected to the driving unit.
[0057] The third transistor has its gate connected to the second scan signal, its drain connected to the second terminal of the storage capacitor through the first node, and its source connected to the driving unit.
[0058] like Figure 2 As shown, the gate of the second transistor T2 is connected to the second scan signal Scan n, the source is connected to the data voltage Data, and the drain is connected to the drain of the fifth transistor T5 of the driving unit.
[0059] The gate of the third transistor T3 is connected to the second scan signal Scan n, the drain is connected to the second terminal of the storage capacitor 12 through point A, and the source is connected to the source of the sixth transistor T6 of the driving unit.
[0060] Optionally, the driving unit includes:
[0061] The first transistor has its gate connected to the second terminal of the storage capacitor at the first node, and its drain connected to the source of the third transistor.
[0062] The fifth transistor has its gate connected to the light-emitting signal, its source connected to the first power supply voltage, and its drain connected to the source of the first transistor.
[0063] A sixth transistor, the gate of which is connected to the light-emitting signal, the source of which is connected to the drain of the first transistor, and the drain of which is connected to the first electrode of the light-emitting element.
[0064] like Figure 2 As shown, the gate of the first transistor T1 is connected to the second terminal of the storage capacitor 12 at point A, and the drain is connected to the source of the third transistor T3.
[0065] The gate of the fifth transistor T5 is connected to the light-emitting signal EM, the source is connected to the first power supply voltage ELVDD, and the drain is connected to the source of the first transistor T1.
[0066] The gate of the sixth transistor T6 is connected to the light-emitting signal EM, the source is connected to the drain of the first transistor T1, and the drain is connected to the first terminal of the light-emitting diode 14.
[0067] Optionally, during the charging phase, the first scan signal is at a low potential, the fourth transistor and the eighth transistor are turned on to pull the voltage of the first node down to the first voltage, and the storage capacitor is charged.
[0068] During the light-emitting holding phase, the light-emitting signal is at a high potential, the ninth transistor is turned on to pull the voltage of the second node up to the compensation voltage, the voltage difference between the first node and the second node decreases, and the leakage current of the fourth transistor decreases.
[0069] Below, in conjunction with Figure 2 and Figure 3 The signal-corresponding timing stages of the pixel driving circuit in the embodiments of this application will be described.
[0070] like Figure 3 As shown, a frame consists of two parts: one data write and multiple data hold operations.
[0071] (1) Data writing stage: Display one frame, write data once for each pixel, corresponding to t1, t2, t3 and t4.
[0072] t1 is the charging stage: the first scan line Scan n-1 is at a low potential, the fourth transistor T4 is turned on, the eighth transistor T8 is turned on, and the charging process begins. Figure 2 The potential at point A on one end of the storage capacitor 12 is pulled down to the potential of the first voltage VINT1, and the storage capacitor 12 is charged.
[0073] t2 is the reset and data writing phase: the seventh transistor T7 is turned on, and the light-emitting diode 14 is reset; the second scan line Scan n is at a low potential, and the second transistor T2, the third transistor T3, and the seventh transistor T7 are turned on, writing the data voltage Data to point A connected to one end of the storage capacitor 12; the source and drain of the first transistor T1 are short-circuited, and the potential at point A is |VA|>|Vth|, that is, at this time the first transistor T1 becomes a diode, and Vth is the threshold voltage of the diode; the first transistor T1 is turned on until the potential at point A becomes Vdata-|Vth| and is turned off, where Vdata is the voltage at which the data voltage is written to point A;
[0074] t3 is the light-emitting display stage: the light-emitting signal EM is at a low potential, the fifth transistor T5 and the sixth transistor T6 are turned on, the storage capacitor 12 discharges to the light-emitting diode 14, the gate-source voltage Vgs of the first transistor T1 is ELVdd-(Vdata-|Vth|), and the source-drain current Ids through the first transistor T1 is (1 / 2)K[Vdd-(Vdata-|Vth|)-|Vth|]^2=(1 / 2)K(Vdd-Vdata)^2, where K=CoxμW / L, Cox is the gate oxide layer capacitance per unit area, W / L is the width-to-length ratio of the oxide layer, and the current flows through the light-emitting diode 14 to display the brightness;
[0075] t4 is the light-emitting holding stage: the light-emitting signal EM is at a high potential, the seventh transistor T7 is turned on, and the ninth transistor T9 is turned on to pull the voltage at point B up to the compensation voltage V1.
[0076] As a result, the voltage difference between point A and point B decreases, and the leakage current through the third transistor T3 and the fourth transistor T4 decreases.
[0077] (2) Data holding phase: Display one frame, do not write data within the pixel, hold the data of each pixel multiple times, refresh repeatedly at a certain interval, corresponding to multiple loops of t3' and t4'.
[0078] t3' is the light-emitting display stage: the light-emitting signal EM is at a low potential, the fifth transistor T5 and the sixth transistor T6 are turned on, the storage capacitor 12 discharges to the light-emitting diode 14, the gate-source voltage Vgs of the first transistor T1 is ELVdd-(Vdata-|Vth|), and the source-drain current Ids through the first transistor T1 is (1 / 2)K[Vdd-(Vdata-|Vth|)-|Vth|]^2=(1 / 2)K(Vdd-Vdata)^2, where K=CoxμW / L, Cox is the gate oxide layer capacitance per unit area, W / L is the width-to-length ratio of the oxide layer, and the current flows through the light-emitting diode 14 to display the brightness;
[0079] t4' is the light-emitting holding stage: the light-emitting signal EM is at a high potential, the seventh transistor T7 is turned on, and the ninth transistor T9 is turned on to pull the voltage at point B up to the compensation voltage V1.
[0080] Therefore, the voltage difference between points A and B decreases, and the leakage current through the third transistor T3 and the fourth transistor T4 decreases. During the aforementioned light-emitting holding phase t4 / t4', the magnitude of the compensation voltage V1 is determined based on the brightness of the screen image displayed by the LED driven by the pixel driving circuit.
[0081] Specifically, the steps for determining the compensation voltage V1 include:
[0082] The system obtains the first display brightness value corresponding to the display panel when the pixel driving circuit writes the data voltage Data at the first screen refresh rate with the current Data holding; and obtains the second display brightness value corresponding to the display panel when the pixel driving circuit writes the data voltage Data at the second screen refresh rate, wherein the data voltage Data written at the second screen refresh rate does not have Data holding.
[0083] The first display brightness value is adjusted according to the second display brightness value, and the magnitude of the compensation voltage V1 is determined according to the voltage value of the drain of the fourth transistor T4 when the second display brightness value is adjusted to the first display brightness value.
[0084] High screen refresh rates, such as 120Hz, can lead to excessive power consumption. Therefore, lower screen refresh rates, such as 60Hz or 90Hz, are usually used to refresh the screen.
[0085] The lower the screen refresh rate, the longer the data is held, meaning there are more cycles in the t3' and t4' stages. For example, at a high screen refresh rate of 120Hz, there are no data holding frames after writing the pixel data signal. However, at low screen refresh rates of 60Hz and 90Hz, there are data holding frames after writing the data voltage, with the number of data holding frames at 90Hz being greater than that at 60Hz.
[0086] During the data holding process, due to the voltage difference between some TFTs of the display panel, such as the third transistor T3 and the fourth transistor T4 and the first voltage VINT1, the third transistor T3 and the fourth transistor T4 will have leakage current, which will cause the display brightness of the light-emitting diode 14 to decrease.
[0087] Therefore, when the display panel is currently writing data at the first screen refresh rate using the data voltage Data, the potential of point B can be increased by the compensation voltage V1 to reduce the voltage difference between point A and point B, thereby reducing the leakage current of the third transistor T3 and the fourth transistor T4.
[0088] The data voltage (Data) written at the second screen refresh rate is not held, resulting in low leakage and high display brightness. During the illumination holding phase, the display brightness at the current first screen refresh rate is adjusted to the high display brightness corresponding to the second screen refresh rate. This obtains the voltage at the drain of the fourth transistor T4 required for this brightness adjustment, i.e., the potential at point B. Using this brightness adjustment voltage value as the compensation voltage value, the potential at point B can be made the same as or close to the potential at point A. Therefore, the voltage difference between points A and B is very small and can be ignored.
[0089] This significantly reduces leakage current in the third transistor T3 and the fourth transistor T4, thereby improving the display brightness of the LEDs and avoiding screen flickering and color distortion caused by screen refresh rate switching.
[0090] The second display brightness value, written to the display panel at the second screen refresh rate using the data voltage Data, can be obtained through detection. When the display panel writes the data voltage Data at the first screen refresh rate, the corresponding first display brightness can be detected. If it is less than the second display brightness value, the first display brightness value is increased by adjusting the compensation voltage V1 until the compensation voltage can increase the first display brightness value to be equal to or close to the second display brightness value.
[0091] Subsequently, while keeping the current first screen refresh rate of the display panel unchanged, the compensation voltage V1 also remains at the last adjusted output compensation voltage level, continuously writing to point B of the drain of the fourth transistor T4, so that the potential at point A remains unchanged, reducing leakage current.
[0092] In this embodiment, the connection node between the charging unit and the storage capacitor is the first node, and the connection node between the compensation unit and the charging unit is the second node. The compensation unit is used to charge the second node to the compensation voltage during the light-emitting holding stage, thereby raising the voltage of the second node to the compensation voltage. The voltage difference between the first node and the second node is reduced, which can reduce the leakage current of the corresponding components, improve the display brightness of the light-emitting diode, and avoid display flickering and color deviation caused by screen refresh rate switching.
[0093] In this application, Figure 2 In the illustrated embodiment, a pixel driving circuit is also proposed, including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor 12, and a light-emitting element 14.
[0094] The first terminal of the storage capacitor is connected to the first power supply voltage, and the connection point between the second terminal of the storage capacitor and the fourth transistor is the first node.
[0095] The gate of the first transistor is connected to the second terminal of the storage capacitor through the first node, the source of the first transistor is connected to the drain of the fifth transistor, and the drain of the first transistor is connected to the source of the third transistor.
[0096] The gate of the second transistor is connected to the second scan signal, the source of the second transistor is connected to the data voltage, and the drain of the second transistor is connected to the drain of the fifth transistor.
[0097] The gate of the third transistor is connected to the second scan signal, the source of the third transistor is connected to the source of the sixth transistor, and the drain of the third transistor is connected to the source of the fourth transistor.
[0098] The gate of the fourth transistor is connected to the first scan signal, the source of the fourth transistor is connected to the second terminal of the storage capacitor at the first node, and the connection node between the drain of the fourth transistor and the drain of the ninth transistor is the second node.
[0099] The gate of the fifth transistor is connected to the light-emitting signal, the source of the fifth transistor is connected to the first power supply voltage, and the drain of the fifth transistor is connected to the source of the first transistor.
[0100] The gate of the sixth transistor is connected to the light-emitting signal, the source of the sixth transistor is connected to the drain of the first transistor, and the drain of the sixth transistor is connected to the first electrode of the light-emitting element.
[0101] The gate of the seventh transistor is connected to the second scan signal, the source of the seventh transistor is connected to the second voltage, and the drain of the seventh transistor is connected to the first electrode of the light-emitting element.
[0102] The gate of the eighth transistor is connected to the first scan signal, the source of the eighth transistor is connected to the first voltage, and the drain of the eighth transistor is connected to the drain of the fourth transistor.
[0103] The gate of the ninth transistor is connected to a light-emitting signal, and the source of the ninth transistor is connected to a compensation voltage.
[0104] In yet another embodiment of this application, a display panel is provided, including the pixel driving circuit described in any of the above embodiments.
[0105] In another embodiment of this application, an electronic device is also proposed, including the display panel described above.
[0106] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A pixel driving circuit, characterized in that, include: A storage capacitor, wherein a first terminal of the storage capacitor is connected to a first power supply voltage, and a second terminal of the storage capacitor is connected to a first node; The charging unit, whose connection node with the storage capacitor is the first node, is connected to a first voltage and a first scan signal, and is used to write the first voltage to the first node during the charging phase. The compensation unit is connected to a compensation voltage and a light emission signal. The connection node between the compensation unit and the charging unit is a second node. The compensation unit is used to charge the second node to the compensation voltage during the light emission holding phase. The compensation voltage is determined based on the brightness of the screen image displayed by the light emission element driven by the pixel driving circuit. A reset unit is connected to a second voltage and a second scan signal. The reset unit is connected to the first electrode of the light-emitting element. The reset unit is used to reset the light-emitting element during the reset phase. The writing unit is connected to a data voltage and the second scan signal, and the writing unit is used to write the data voltage into the first node during the data writing phase; A driving unit is connected to a first power supply voltage and a light emission signal. The driving unit, the charging unit, and the writing unit are all connected to the first node. The driving unit is used to provide driving current to the light emission element. The first electrode of the light-emitting element is connected to the driving unit, and the second electrode of the light-emitting element receives a second power supply voltage; The step of determining the compensation voltage includes: The first display brightness value corresponding to the display panel is obtained when the pixel driving circuit writes data voltage at the currently existing first screen refresh rate. The second display brightness value corresponding to the display panel is obtained when the pixel driving circuit writes the data voltage at the second screen refresh rate, wherein there is no data voltage holding when writing the data voltage at the second screen refresh rate; Adjust the first display brightness value according to the second display brightness value; The voltage value of the second node is determined when the first display brightness value is adjusted based on the second display brightness value, thereby determining the magnitude of the compensation voltage.
2. The pixel driving circuit according to claim 1, characterized in that, The charging unit includes: The fourth transistor has its gate connected to the first scan signal, and the connection node between the source of the fourth transistor and the second terminal of the storage capacitor is the first node; The eighth transistor has its gate connected to the first scan signal, its source connected to the first voltage, and its drain connected to the drain of the fourth transistor.
3. The pixel driving circuit according to claim 2, characterized in that, The compensation unit includes a ninth transistor, the gate of which is connected to a light-emitting signal, the source of which is connected to the compensation voltage, and the connection node between the drain of the ninth transistor and the drain of the fourth transistor is the second node.
4. The pixel driving circuit according to claim 1, characterized in that, The reset unit includes a seventh transistor, the gate of which is connected to the second scan signal, the source of which is connected to the second voltage, and the drain of which is connected to the first electrode of the light-emitting element.
5. The pixel driving circuit according to claim 1, characterized in that, The writing unit includes: The second transistor has its gate connected to the second scan signal, its source connected to the data voltage, and its drain connected to the driving unit. The third transistor has its gate connected to the second scan signal, its drain connected to the second terminal of the storage capacitor through the first node, and its source connected to the driving unit.
6. The pixel driving circuit according to claim 5, characterized in that, The driving unit includes: The first transistor has its gate connected to the second terminal of the storage capacitor at the first node, and its drain connected to the source of the third transistor. The fifth transistor has its gate connected to the light-emitting signal, its source connected to the first power supply voltage, and its drain connected to the source of the first transistor. A sixth transistor, the gate of which is connected to the light-emitting signal, the source of which is connected to the drain of the first transistor, and the drain of which is connected to the first electrode of the light-emitting element.
7. The pixel driving circuit according to claim 3, characterized in that, During the charging phase, the first scan signal is at a low potential, the fourth transistor and the eighth transistor are turned on to pull the voltage of the first node down to the first voltage, and the storage capacitor is charged. During the light-emitting holding phase, the light-emitting signal is at a high potential, the ninth transistor is turned on to pull the voltage of the second node up to the compensation voltage, and the voltage difference between the first node and the second node decreases.
8. A pixel driving circuit, characterized in that, It includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a storage capacitor, and a light-emitting element; The first terminal of the storage capacitor is connected to the first power supply voltage, and the connection point between the second terminal of the storage capacitor and the fourth transistor is the first node. The gate of the first transistor is connected to the second terminal of the storage capacitor through the first node, the source of the first transistor is connected to the drain of the fifth transistor, and the drain of the first transistor is connected to the source of the third transistor. The gate of the second transistor is connected to the second scan signal, the source of the second transistor is connected to the data voltage, and the drain of the second transistor is connected to the drain of the fifth transistor. The gate of the third transistor is connected to the second scan signal, the source of the third transistor is connected to the source of the sixth transistor, and the drain of the third transistor is connected to the source of the fourth transistor. The gate of the fourth transistor is connected to the first scan signal, the source of the fourth transistor is connected to the second terminal of the storage capacitor at the first node, and the connection node between the drain of the fourth transistor and the drain of the ninth transistor is the second node. The gate of the fifth transistor is connected to a light-emitting signal, the source of the fifth transistor is connected to the first power supply voltage, and the drain of the fifth transistor is connected to the source of the first transistor. The gate of the sixth transistor is connected to the light-emitting signal, the source of the sixth transistor is connected to the drain of the first transistor, and the drain of the sixth transistor is connected to the first electrode of the light-emitting element. The gate of the seventh transistor is connected to the second scan signal, the source of the seventh transistor is connected to the second voltage, and the drain of the seventh transistor is connected to the first electrode of the light-emitting element. The gate of the eighth transistor is connected to the first scan signal, the source of the eighth transistor is connected to the first voltage, and the drain of the eighth transistor is connected to the drain of the fourth transistor. The gate of the ninth transistor is connected to a light-emitting signal, and the source of the ninth transistor is connected to a compensation voltage. The compensation voltage is determined based on the brightness of the screen image displayed by the light-emitting element driven by the pixel driving circuit. The step of determining the compensation voltage includes: The first display brightness value corresponding to the display panel is obtained when the pixel driving circuit writes data voltage at the currently existing first screen refresh rate. The second display brightness value corresponding to the display panel is obtained when the pixel driving circuit writes the data voltage at the second screen refresh rate, wherein there is no data voltage holding when writing the data voltage at the second screen refresh rate; Adjust the first display brightness value according to the second display brightness value; The magnitude of the compensation voltage is determined by adjusting the voltage value of the drain of the fourth transistor when adjusting the first display brightness value based on the second display brightness value.
9. A display panel, characterized in that, Includes the pixel driving circuit according to any one of claims 1 to 8.
10. An electronic device, characterized in that, Includes the display panel according to claim 9.
Citation Information
Patent Citations
Pixel circuit and driving method thereof and display device
CN111724745A