Memory read method, threshold voltage offset amount calculation method, and memory system

Abstract

The application provides a memory reading method, a threshold voltage offset calculation method and a storage system, wherein the memory comprises a target storage unit, the target storage unit has a default reading voltage and a fixed voltage offset, the memory reading method comprises the following steps: obtaining a target threshold voltage offset of the target storage unit, and then combining the default reading voltage with the target threshold voltage offset and the fixed voltage offset to perform a reading operation on the target storage unit. The reading method provided by the application can improve the reading speed and ensure the accuracy of the reading operation by using two voltage offsets with different sizes to repeatedly perform the reading operation on the target storage unit.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a memory reading method, a threshold voltage offset calculation method, and a memory system. Background Technology

[0002] With the development of multi-bit storage technology, data retention noise caused by charge loss in storage cells is becoming increasingly serious in 3D NAND flash memory.

[0003] Therefore, in determining the optimal read voltage after the threshold voltage shift of the storage cell due to charge loss, how to improve the speed of the above operation while ensuring its accuracy is a problem that needs to be solved. Summary of the Invention

[0004] To address the above-mentioned or other problems, the present invention provides the following technical solutions.

[0005] In a first aspect, the present invention provides a method for reading a memory, the memory including a target memory cell having a default read voltage and a fixed voltage offset, the reading method comprising:

[0006] Obtain the target threshold voltage offset of the target memory cell;

[0007] The default read voltage is combined with the target threshold voltage offset and the fixed voltage offset to perform a read operation on the target memory cell.

[0008] According to a reading method of an embodiment of the present invention, the target threshold voltage offset is greater than the fixed voltage offset.

[0009] According to a reading method of an embodiment of the present invention, the step of combining the default reading voltage with the target threshold voltage offset and the fixed voltage offset to perform a reading operation on the target memory cell specifically includes:

[0010] The default read voltage is offset by the target threshold voltage offset to obtain the read voltage to be adjusted;

[0011] The read voltage to be adjusted is offset by at least one of the fixed voltage offsets until the optimal read voltage is obtained, so as to complete the read operation performed on the target memory cell.

[0012] According to a reading method of an embodiment of the present invention, the step of obtaining the target threshold voltage offset of the target memory cell specifically includes:

[0013] Obtain the target operating temperature and target operating time of the memory;

[0014] The target operating temperature and the target operating time are calculated according to the target derivation formula to obtain the corresponding target threshold voltage offset.

[0015] In a second aspect, the present invention provides a method for calculating a threshold voltage offset, the calculation method comprising:

[0016] Acquire the threshold voltage offset of multiple identical devices under test placed in multiple test environments at multiple sampling times, wherein the operating temperature of each test environment is different;

[0017] Each threshold voltage offset, the corresponding operating temperature, and the sampling time are used as a conversion array, and a function transformation is performed on the threshold voltage offset and the operating temperature in each conversion array to obtain multiple converted arrays;

[0018] Based on the multiple converted arrays, the derived relationship between the threshold voltage offset and the operating temperature of the device under test at different sampling times is calculated.

[0019] According to a calculation method of an embodiment of the present invention, the same plurality of devices under test have the same number of erase / write cycles. The step of obtaining the threshold voltage offset of the plurality of identical devices under test placed in multiple test environments at multiple sampling times specifically includes:

[0020] At each sampling time, multiple derived voltage offsets are acquired for each of the multiple identical devices under test placed in multiple test environments;

[0021] The number of erasable and rewritable cycles are respectively calculated with the plurality of derived voltage offsets of each device under test according to the first preset relationship to obtain the threshold voltage offset of each device under test at each sampling time;

[0022] The plurality of derived voltage offsets include a first derived voltage offset caused by rapid charge decapture, a second derived voltage offset caused by defect-assisted tunneling, and a third derived voltage offset caused by lateral charge migration.

[0023] According to a calculation method of an embodiment of the present invention, each of the derived voltage offsets has multiple derivation factors, and the step of acquiring multiple derived voltage offsets of each of the multiple identical devices under test placed in multiple test environments at each sampling time specifically includes:

[0024] At each sampling time, the sampling time and the plurality of derivation factors of each of the derived voltage offsets of each of the devices under test are calculated according to the second preset relationship to obtain the plurality of derived voltage offsets of each of the devices under test at each sampling time;

[0025] The plurality of derivation factors for each of the derived voltage offsets include at least one of the corresponding saturation voltage offset, time constant, and shape parameter of the retained curve.

[0026] According to an embodiment of the calculation method of the present invention, after the step of taking each threshold voltage offset and the corresponding operating temperature and the sampling time as a conversion array, the method further includes:

[0027] Based on the multiple arrays to be converted and the charge loss model formula, a first curve is fitted to show the change of the threshold voltage offset of the device under test with operating time at different operating temperatures.

[0028] According to a calculation method of an embodiment of the present invention, the step of performing a function transformation on the threshold voltage offset and the operating temperature in each of the arrays to be transformed specifically includes:

[0029] Obtain the fitted threshold voltage offset on multiple first curves for different operating temperatures at any given operating time, and perform a function transformation on the fitted threshold voltage offset and the corresponding operating temperature.

[0030] According to a calculation method of an embodiment of the present invention, the function transformation includes:

[0031] Take the logarithm of the fitted threshold voltage offset as the transformed fitted threshold voltage offset; and,

[0032] The reciprocal of the operating temperature corresponding to the fitted threshold voltage offset is taken as the transformed operating temperature;

[0033] In any of the aforementioned operating times, the transformed fitted threshold voltage offset and the transformed operating temperature follow a second linear curve.

[0034] According to a calculation method of an embodiment of the present invention, the step of calculating the derived relationship between the threshold voltage offset and the operating temperature of the device under test at different sampling times based on a plurality of the converted arrays specifically includes:

[0035] Based on the linear second curve, the derived relationship of the threshold voltage offset of the device under test as a function of the operating temperature is calculated for any of the said operating times.

[0036] According to a calculation method of an embodiment of the present invention, the operating temperature in the plurality of test environments includes the highest operating temperature and the lowest operating temperature of the device under test.

[0037] Thirdly, the present invention provides a storage system, the storage system comprising:

[0038] Memory; and,

[0039] A controller, coupled to the memory, and configured to perform a read method on the memory as described in any of the preceding claims.

[0040] The beneficial effects of this invention are as follows: This invention provides a memory reading method, a threshold voltage offset calculation method, and a storage system, wherein the memory includes a target storage cell, the target storage cell has a default reading voltage and a fixed voltage offset, and the memory reading method includes: obtaining the target threshold voltage offset of the target storage cell, and then combining the default reading voltage with the target threshold voltage offset and the fixed voltage offset to perform a reading operation on the target storage cell. The reading method provided by this invention uses two voltage offsets of different sizes to repeatedly read the target storage cell, which not only improves the speed of the reading operation, but also ensures the accuracy of the reading operation. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the various embodiments made according to the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0042] Figures 1a to 1b This is a schematic diagram of the read voltage offset of the memory read method in some implementations.

[0043] Figure 2 This is a schematic flowchart of a memory reading method provided by an embodiment of the present invention.

[0044] Figure 3 This is a further flowchart illustrating the memory reading method provided by an embodiment of the present invention.

[0045] Figure 4 This is a schematic diagram of the read voltage offset of a memory read method provided according to an embodiment of the present invention.

[0046] Figure 5This is a flowchart illustrating a method for calculating the threshold voltage offset provided by an embodiment of the present invention.

[0047] Figure 6 This is a further flowchart illustrating the method for calculating the threshold voltage offset provided by an embodiment of the present invention.

[0048] Figures 7a to 7b This is a schematic diagram illustrating an application scenario of the threshold voltage offset calculation method provided by an embodiment of the present invention.

[0049] Figure 8 This is a schematic diagram of the structure of a storage system provided according to an embodiment of the present invention. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0051] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0052] First, please refer to Figures 1a to 1b The diagram illustrates the read voltage offset of the memory read method in some embodiments, specifically in... Figures 1a to 1b In the diagram, A1 represents the threshold voltage distribution of each order before the threshold voltage shift occurs in the memory cell, and A2 represents the threshold voltage distribution of each order after the threshold voltage shift occurs in the memory cell.

[0053] like Figures 1a to 1bAs shown, in this implementation, when it is necessary to determine the optimal read voltage after a memory cell experiences a threshold voltage shift due to charge loss, it is typically based on the default read voltage (Default Vread, denoted as Vread) before the threshold voltage shift. The default read voltage Vread is offset by a fixed voltage offset Va / Vb, and the memory cell is repeatedly read. During this repeated reading process, the optimal read voltage for the memory cell experiencing the threshold voltage shift due to charge loss is found using a method that counts the number of bit errors (FBC). Specifically, the read voltage corresponding to the point where the number of bit errors reaches its lowest value is the optimal read voltage.

[0054] However, during the repeated reading of the memory cell described above, if the set fixed voltage offset is too large, such as... Figure 1b If the fixed voltage offset Vb is set too low, the final optimal reading voltage will be inaccurate. Conversely, if the fixed voltage offset is set too low, such as... Figure 1a A fixed voltage offset Va in the data will increase the time required for repeated readings.

[0055] Now, please see Figure 2 and Figure 4 ,in, Figure 2 A schematic flowchart of a memory reading method provided by an embodiment of the present invention is shown. Figure 4 A schematic diagram of the read voltage offset of a memory read method provided by an embodiment of the present invention is shown.

[0056] Specifically, in Figure 4 In the diagram, A3 represents the threshold voltage distribution of each order before the memory cell experiences a threshold voltage shift, and A4 represents the threshold voltage distribution of each order after the memory cell experiences a threshold voltage shift. For example... Figure 2 and Figure 4 As shown, the reading method may include the following steps:

[0057] Step S101: Obtain the target threshold voltage offset of the target memory cell;

[0058] Reading step S102: Combine the default read voltage Vread with the target threshold voltage offset ΔVt and the fixed voltage offset V1 to perform a read operation on the target memory cell.

[0059] It should be noted that, in this embodiment of the invention, two voltage offsets of different magnitudes, a target threshold voltage offset ΔVt and a fixed voltage offset V1, are used to repeatedly read the target memory cell. Furthermore, the target threshold voltage offset ΔVt is greater than the fixed voltage offset V1, and the number of times the default read voltage Vread is offset using the target threshold voltage offset ΔVt is less than the number of times the default read voltage Vread is offset using the fixed voltage offset V1. In other words, in the process of adjusting the default read voltage Vread to the optimal read voltage of the memory cell, the process of offsetting the default read voltage Vread using the target threshold voltage offset ΔVt is a coarse adjustment of the default read voltage Vread, while the process of offsetting the default read voltage Vread using the fixed voltage offset V1 is a fine adjustment of the default read voltage Vread. Therefore, the memory reading method provided by this embodiment of the invention not only improves the speed of the read operation but also ensures the accuracy of the read operation.

[0060] Further, please refer to Figure 3 The diagram shows a further flow chart of the memory reading method provided by an embodiment of the present invention.

[0061] It should be noted that during the above reading step S102, the order in which the target threshold voltage offset ΔVt and the fixed voltage offset V1 are used to offset the default reading voltage Vread needs to be specified to ensure that the obtained optimal reading voltage has the best accuracy. For example, if... Figure 3 As shown, the above reading step S102 may specifically include the following steps:

[0062] First reading step S1021: Offset the default reading voltage Vread by the target threshold voltage offset ΔVt to obtain the reading voltage to be adjusted;

[0063] Second reading step S1022: Offset the read voltage to be adjusted by at least a fixed voltage offset V1 until the optimal read voltage is obtained, so as to complete the read operation performed on the target memory cell.

[0064] For further information, please refer to [link / reference]. Figure 3 In this embodiment of the invention, the above-mentioned obtaining step S101 may specifically include the following steps:

[0065] First acquisition step S1011: Acquire the target operating temperature and target operating time of the memory;

[0066] The second acquisition step S1012: Calculate the target operating temperature and target operating time according to the target derivation formula to obtain the corresponding target threshold voltage offset.

[0067] It should be noted that, in this embodiment of the invention, the above-mentioned target derivation formula is saved in the memory after it is initially generated. When the memory controller needs to perform the above-mentioned reading method on the memory, it directly retrieves the saved target derivation formula from the memory, and then substitutes the target operating temperature and target operating time of the memory at the current moment into the target derivation formula and calculates the target threshold voltage offset to be used in the subsequent reading step S102.

[0068] Based on the foregoing, embodiments of the present invention provide a method for reading a memory, wherein the memory includes a target memory cell, the target memory cell having a default read voltage and a fixed voltage offset, and the method for reading the memory includes: obtaining a target threshold voltage offset of the target memory cell, and then combining the default read voltage with the target threshold voltage offset and the fixed voltage offset to perform a read operation on the target memory cell. The reading method provided by the present invention uses two voltage offsets of different sizes to repeatedly read the target memory cell, which not only improves the speed of the read operation, but also ensures the accuracy of the read operation.

[0069] Next, the calculation method of the target derivation formula required for calculating the target threshold voltage offset will be explained.

[0070] Please see Figure 5 , Figure 5 A flowchart illustrating a method for calculating a threshold voltage offset according to an embodiment of the present invention is shown. The method for calculating the threshold voltage offset specifically includes: a first calculation step S201, a conversion step S202, and a second calculation step S203. The steps will be described in detail below.

[0071] First calculation step S201: Obtain the threshold voltage offset of multiple identical devices under test placed in multiple test environments at multiple sampling times, wherein the operating temperature of each test environment is different.

[0072] Please see Figure 7a It should be understood that in this embodiment, multiple identical devices under test are divided into six groups, and these six groups of devices under test are placed in six test environments with different operating temperatures (T1 to T6) for testing. Then, the threshold voltage offset (denoted as ΔVt) of each group of devices under test is obtained at multiple sampling time points.

[0073] Specifically, the operating temperatures in multiple test environments include the maximum and minimum operating temperatures of the device under test. That is, in this embodiment, the above six operating temperatures (T1 to T6) will cover the maximum and minimum operating temperatures of the device under test.

[0074] It should be noted that in NAND flash memory, charge loss due to long-term retention mainly includes: charge loss caused by fast charge de-trap, charge loss caused by defect-assisted tunneling (TAT), and charge loss caused by lateral charge migration (LM).

[0075] It is easy to understand that in the first calculation step S201, the threshold voltage offset of the device under test at different operating temperatures and at different sampling times is the result of the combined effect of multiple derived voltage offsets related to the causes of charge loss listed above.

[0076] Therefore, as Figure 6 As shown, the first calculation step S201 may specifically include the following steps:

[0077] Sub-step S2011: At each sampling time, acquire multiple derived voltage offsets for each device under test among multiple identical devices under test placed in multiple test environments, wherein the multiple derived voltage offsets include a first derived voltage offset caused by fast charge decapsulation, a second derived voltage offset caused by defect-assisted tunneling, and a third derived voltage offset caused by lateral charge migration.

[0078] Calculation sub-step S2012: Calculate the number of erasable and rewritable cycles and the multiple derived voltage offsets of each device under test according to the first preset relationship to obtain the threshold voltage offset of each device under test at each sampling time.

[0079] It should be noted that, in this embodiment, the first derived voltage offset caused by rapid charge decapsulation is denoted as ΔVt_De-trap, the second derived voltage offset caused by defect-assisted tunneling is denoted as ΔVt_TAT, and the third derived voltage offset caused by lateral charge migration is denoted as ΔVt_LM.

[0080] Furthermore, multiple identical devices under test (DUTs) have the same number of erasable / rewrite cycles (P / E cycles, denoted as N). The threshold voltage offset ΔVt of each DUT at each sampling time is also related to the correlation function f(N) of the number of erasable / rewrite cycles N. In calculation sub-step S2012, the expression for the threshold voltage offset ΔVt of each DUT at each sampling time, obtained according to the first preset relation, is as follows:

[0081] ΔVt=(ΔVt_De-trap+ΔVt_TAT+ΔVt_LM)*f(N).

[0082] It should be noted that the above expression is also the expression for the derived voltage shift ΔVt of each device under test at any operating time. Furthermore, each derived voltage shift of each device under test will change with time. Each derived voltage shift has multiple derivation factors, including: saturated voltage shift (denoted as ΔVt_sat), time constant (denoted as τmod), and shape parameter of retention curve (denoted as βmod). The value of each derivation factor is equal at any operating time point under the same operating temperature.

[0083] Therefore, in the acquisition sub-step S2011, the step of "acquiring multiple derived voltage offsets of each device under test among multiple identical devices under test placed in multiple test environments at each sampling time" can specifically include:

[0084] At each sampling time, the sampling time and multiple derivation factors of each derivation voltage offset of each device under test are calculated according to the second preset relationship to obtain multiple derivation voltage offsets of each device under test at each sampling time.

[0085] It should be noted that, taking the first derived voltage offset ΔVt_De-trap as an example, its expression for a certain sampling time at a certain operating temperature is as follows:

[0086] ΔVt_De-trap=ΔVt_sat*(1-exp(-(t / τmod)^βmod)).

[0087] Using the two expressions above, the threshold voltage offset ΔVt of the device under test at any sampling time at any operating temperature can be calculated.

[0088] Conversion step S202: Take each threshold voltage offset, the corresponding operating temperature, and the sampling time as a conversion array, and perform a function transformation on the threshold voltage offset and operating temperature in each conversion array to obtain multiple converted arrays.

[0089] Please continue reading. Figure 7a The array to be converted is a point on the curve corresponding to any operating temperature. For example, it could be... Figure 7a The points on the TI curve indicate the threshold voltage offset corresponding to the current operating temperature and sampling time.

[0090] It is easy to understand that multiple conversion data of each device under test can be fitted into a distribution curve of the threshold voltage offset over the operating time at the corresponding operating temperature. Then, based on the distribution curve and the transformation model, the relationship between the threshold voltage offset of the device under test and the operating temperature can be obtained at any operating time other than the sampling time.

[0091] Therefore, as Figure 6 As shown, conversion step S202 may specifically include the following steps:

[0092] Array acquisition sub-step S2021: Take each threshold voltage offset, the corresponding operating temperature, and the sampling time as a conversion array;

[0093] First curve fitting sub-step S2022: Based on multiple arrays to be converted and the charge loss model formula, fit the first curve of the threshold voltage offset of the device under test as a function of operating time at different operating temperatures;

[0094] Point acquisition step S2023: Obtain the fitting threshold voltage offset on multiple first curves corresponding to different operating temperatures at any operating time;

[0095] Second curve fitting sub-step S2024: Take the logarithm of the fitted threshold voltage offset as the transformed fitted threshold voltage offset and take the reciprocal of the operating temperature corresponding to the fitted threshold voltage offset as the transformed operating temperature. Wherein, at any operating time, the transformed fitted threshold voltage offset and the transformed operating temperature form a linear second curve.

[0096] It should be noted that, because the trend of the fitted threshold voltage offset with operating temperature at any operating time is curvilinear in the data obtained in step S2023, the relationship between the threshold voltage offset and operating temperature at any operating time cannot be calculated directly from this curvilinear trend graph. However, the Arrhenius model is the most typical and widely used acceleration model for temperature stress testing. Applying the Arrhenius model to the above data yields a linear relationship between the variable and the dependent variable. That is, in the second curve fitting sub-step S2024, a linear relationship between the transformed fitted threshold voltage offset and the transformed operating temperature is obtained, as shown below. Figure 7b As shown. It should be noted that the transformed fitted threshold voltage offset is denoted as Ln(ΔVt), and the transformed operating temperature is denoted as 1 / K*T (where K is the Boltzmann constant = 8.62 × 10⁻⁶). -5 eV / K).

[0097] Second calculation step S203: Based on multiple converted arrays, calculate the derived relationship between the threshold voltage offset and the operating temperature of the device under test at different sampling times.

[0098] It is easy to understand that, such as Figure 6 As shown, using the conversion method described above, the second calculation step S203 can specifically be:

[0099] Based on the linear second curve, the derived relationship between the threshold voltage offset of the device under test and the operating temperature is obtained for any operating time.

[0100] Specifically, the derived formula for the threshold voltage offset of the device under test as a function of operating temperature at any given operating time can be expressed as ΔVt=Ae B(1 / K*T) , where A and B are constant coefficients calculated from the second linear curve described above.

[0101] Based on the foregoing, this invention provides a method for calculating threshold voltage offset, comprising: acquiring the threshold voltage offset of multiple identical devices under test (DUTs) placed in multiple test environments at multiple sampling times, wherein the operating temperature of each test environment is different; then, taking each threshold voltage offset, the corresponding operating temperature, and the sampling time as a conversion array, and performing a function transformation on the threshold voltage offset and operating temperature in each conversion array to obtain multiple converted arrays; then, calculating the derivation relationship between the threshold voltage offset and operating temperature of the DUT at different sampling times based on the multiple converted arrays. This invention places multiple DUTs in test environments with different operating temperatures for testing, and calculates the derivation relationship between the threshold voltage offset and operating temperature of the DUT at different sampling times. This derivation relationship can be used during the reading of a memory cell by using the calculated target threshold voltage offset to initially offset the default read voltage of the memory cell, thereby accurately determining the optimal read voltage of the memory cell that has a threshold voltage offset due to charge loss in a short time.

[0102] Please see Figure 8 , Figure 8 A schematic diagram of the structure of a storage system 600 provided according to an embodiment of the present invention is shown, as follows: Figure 8 As shown, the storage system 600 includes a memory 601 and a controller 602. The components will now be described in detail.

[0103] The memory 601 can be a three-dimensional memory such as 3D NAND or 3D NOR memory. The controller 602 is coupled to the memory 601. The memory 601 can be subjected to operations such as storing or transmitting data based on the control of the controller 602. That is, the controller 602 can control the memory 601 to perform operations such as data storage or transmission. For example, the controller 602 can be configured to perform the memory reading method as described above on the memory 601.

[0104] It should be noted that, in some embodiments, the above-described storage system 600 may be implemented as the following devices: Universal Flash Storage (UFS), Solid State Drives (SSD), Multimedia Card (MMC), Secure Digital (SD) card, Peripheral Component Interconnect (PCI) type storage device, Compact Flash (CF) card, and smart media card, etc.

[0105] In addition to the embodiments described above, the present invention may have other implementations. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by the present invention.

[0106] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for reading from a memory, characterized in that, The memory includes a target memory cell, the target memory cell having a default read voltage and a fixed voltage offset, and the read method includes: Obtain the target threshold voltage offset of the target memory cell; The default read voltage is combined with the target threshold voltage offset and the fixed voltage offset to perform a read operation on the target memory cell; Wherein, the target threshold voltage offset is greater than the fixed voltage offset, and the number of times the target threshold voltage offset is used to offset the default read voltage is less than the number of times the fixed voltage offset is used to offset the default read voltage.

2. The reading method according to claim 1, characterized in that, The step of combining the default read voltage with the target threshold voltage offset and the fixed voltage offset to perform a read operation on the target memory cell specifically includes: The default read voltage is offset by the target threshold voltage offset to obtain the read voltage to be adjusted; The read voltage to be adjusted is offset by at least one of the fixed voltage offsets until the optimal read voltage is obtained, so as to complete the read operation performed on the target memory cell.

3. The reading method according to claim 1, characterized in that, The step of obtaining the target threshold voltage offset of the target memory cell specifically includes: Obtain the target operating temperature and target operating time of the memory; The target operating temperature and the target operating time are calculated according to the target derivation formula to obtain the corresponding target threshold voltage offset.

4. A method for calculating threshold voltage offset, characterized in that, The calculation method includes: Acquire the threshold voltage offset of multiple identical devices under test placed in multiple test environments at multiple sampling times, wherein the operating temperature of each test environment is different; Each threshold voltage offset, the corresponding operating temperature, and the sampling time are used as a conversion array, and a function transformation is performed on the threshold voltage offset and the operating temperature in each conversion array to obtain multiple converted arrays; Based on the multiple converted arrays, the derived relationship between the threshold voltage offset and the operating temperature of the device under test at different sampling times is calculated. The function transformation includes: The logarithm of the fitted threshold voltage offset is taken as the transformed fitted threshold voltage offset; and, The reciprocal of the operating temperature corresponding to the fitted threshold voltage offset is taken as the transformed operating temperature; Wherein, at any operating time, the transformed fitted threshold voltage offset and the transformed operating temperature form a second linear curve; The step of calculating the derived relationship between the threshold voltage offset and the operating temperature of the device under test at different sampling times based on multiple converted arrays specifically includes: Based on the linear second curve, the derived relationship of the threshold voltage offset of the device under test as a function of the operating temperature is calculated for any operating time.

5. The calculation method according to claim 4, characterized in that, The multiple identical devices under test (DUTs) have the same number of erase / write cycles. The step of obtaining the threshold voltage offset of the multiple identical DUTs placed in multiple test environments at multiple sampling times specifically includes: At each sampling time, multiple derived voltage offsets are acquired for each of the multiple identical devices under test placed in multiple test environments; The number of erasable and rewritable cycles are respectively calculated with the plurality of derived voltage offsets of each device under test according to the first preset relationship to obtain the threshold voltage offset of each device under test at each sampling time; The plurality of derived voltage offsets include a first derived voltage offset caused by rapid charge decapture, a second derived voltage offset caused by defect-assisted tunneling, and a third derived voltage offset caused by lateral charge migration.

6. The calculation method according to claim 5, characterized in that, Each of the derived voltage offsets has multiple derivation factors. The step of acquiring multiple derived voltage offsets for each of the multiple identical devices under test placed in multiple test environments at each sampling time specifically includes: At each sampling time, the sampling time and the plurality of derivation factors of each of the derived voltage offsets of each of the devices under test are calculated according to the second preset relationship to obtain the plurality of derived voltage offsets of each of the devices under test at each sampling time; The plurality of derivation factors for each of the derived voltage offsets include at least one of the corresponding saturation voltage offset, time constant, and shape parameter of the retained curve.

7. The calculation method according to claim 4, characterized in that, After the step of treating each threshold voltage offset, the corresponding operating temperature, and the sampling time as a conversion array, the method further includes: Based on the multiple arrays to be converted and the charge loss model formula, a first curve is fitted to show the change of the threshold voltage offset of the device under test with the operating time at different operating temperatures.

8. The calculation method according to claim 7, characterized in that, The step of performing a function transformation on the threshold voltage offset and the operating temperature in each of the arrays to be transformed specifically includes: Obtain the fitted threshold voltage offset on multiple first curves for different operating temperatures at any given operating time, and perform a function transformation on the fitted threshold voltage offset and the corresponding operating temperature.

9. The calculation method according to claim 4, characterized in that, The operating temperatures in the various test environments include the highest and lowest operating temperatures of the device under test.

10. A storage system, characterized in that, The storage system includes: Memory; and, A controller, coupled to the memory, and configured to perform the read method as described in any one of claims 1 to 3 on the memory.

Images