Silicon wafer diffusion method and battery cell preparation method

Abstract

The present invention discloses a silicon wafer diffusion method and a solar cell preparation method. The method loads single silicon wafers in the single-wafer area and the lower single-wafer area on a quartz boat, and loads double silicon wafers in the double-wafer area. During diffusion, the double silicon wafers are diffused on one side, while the single silicon wafers are diffused on both sides. The side of the silicon wafers in the upper and lower single-wafer areas facing the double-wafer area serves as the diffusion surface, while the side not facing the double-wafer area serves as the non-diffusion surface. The side of the silicon wafer not facing the double-wafer area is completely etched after diffusion to remove the diffusion resistance, thereby forming a non-diffusion surface. This eliminates the low square resistance effect caused by the proximity of this surface to the thermal field.

Description

Technical Field

[0001] The present invention belongs to the field of photovoltaic equipment and relates to a silicon wafer diffusion method and a battery slice preparation method. Background Art

[0002] With the development of the current silicon wafer market, larger wafers are more in line with current market trends, but this also poses greater challenges to equipment, especially thermal process equipment. Silicon wafers deform at high temperatures, especially 18xmm or 210mm wafers. As the size increases, the wafers bend due to heat, and adjacent wafers may even cling together. This seriously affects the uniformity of product diffusion, thereby restricting further improvements in the power generation efficiency of large-size products. The solution to this problem is to use horizontal diffusion instead of vertical diffusion.

[0003] However, the uniformity of diffusion is not only affected by the gas, but also by the temperature. In horizontal diffusion, since the thermal radiation of the upper and lower thermal fields is blocked by the silicon wafers layer by layer, there is a difference in the temperature of the upper and lower silicon wafers and the temperature of the middle silicon wafer. This will lead to the problem of low square resistance of the silicon wafers at the upper and lower ends, especially the square resistance of the first silicon wafer of the upper and lower ends in the quartz boat close to the thermal field is very low. Currently, the scheme of loading dummy wafers or controlling the thermal radiation power of the thermal field in stages is often used to improve the situation. The scheme of loading dummy wafers increases production costs. In addition, the dummy wafers need to be replaced regularly. As the number of diffusions increases, the source amount of the dummy wafers reaches saturation, and the effect of the dummy wafers will become worse and worse. The scheme of segmented control of thermal field power can alleviate the impact of thermal radiation from the thermal field, but it requires increasing the cost of the thermal field, and it is more expensive to change the thermal field on the existing diffusion equipment. Summary of the Invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides a relatively simple silicon wafer diffusion method and a battery cell preparation method that reduce the influence of thermal field heat radiation at the upper and lower ends.

[0005] In order to achieve the above object, the present invention adopts the following technical solution: a silicon wafer diffusion method, comprising the following steps:

[0006] S01: Loading the boat: inserting silicon wafers into a quartz boat in sections. The quartz boat includes an upper single-wafer area, a lower single-wafer area, and a double-wafer area. The double-wafer area is located between the upper single-wafer area and the lower single-wafer area. The upper single-wafer area and the lower single-wafer area are loaded with single silicon wafers, and the double-wafer area is loaded with double silicon wafers.

[0007] S02: Phosphorus diffusion, phosphorus is diffused into the silicon wafer to form a PN junction.

[0008] Furthermore, in step S02, the phosphorus diffusion includes the following steps:

[0009] S021: Place the quartz boat carrying the silicon wafer into the quartz furnace tube;

[0010] S022: Vacuum leak detection;

[0011] S023: After the furnace tube is heated to 770-790°C, oxygen and nitrogen are introduced at an oxygen flow rate of 1-1.5 L / min and a nitrogen flow rate of 3-3.5 L / min. The furnace tube pressure is 150-170 mbar and the time is 4-6 minutes.

[0012] S024: constant temperature 770-790℃, nitrogen carries phosphorus oxychloride, mixed oxygen and nitrogen are introduced from the furnace tail, oxygen flow rate is 0.8-1L / min, furnace tube pressure is 150-170mbar, time is 11-13min;

[0013] S025: ramp temperature from 770°C to 845°C, oxygen flow rate 1-1.5 L / min, nitrogen flow rate 3-3.5 L / min, furnace pressure 150-170 mbar, time 9-11 min;

[0014] S026: Maintain temperature at 845°C. During the temperature maintenance process, nitrogen is added at a flow rate of 3-3.5 L / min, the furnace pressure is 160 mbar, and the time is 9-11 minutes.

[0015] S027: Cool down to 800℃, pass nitrogen back to normal pressure, and take out of the furnace.

[0016] A silicon wafer diffusion method comprises the following steps:

[0017] S31: Loading the boat: inserting the silicon wafers into the quartz boat in sections. The quartz boat includes an upper single-wafer area, a lower single-wafer area, and a double-wafer area. The double-wafer area is located between the upper single-wafer area and the lower single-wafer area. The upper single-wafer area and the lower single-wafer area are loaded with single silicon wafers, and the double-wafer area is loaded with double silicon wafers.

[0018] S32: Boron diffusion, boron diffusion is performed on the silicon wafer to form a PN junction.

[0019] Furthermore, in step S32, the boron diffusion includes the following steps:

[0020] S3201: Place the quartz boat carrying the silicon wafer into the quartz furnace tube;

[0021] S3202: Vacuum leak detection;

[0022] S3203: Heating, ramping from 770°C to 800°C, introducing nitrogen, with a furnace pressure of 140-160 mbar, for 14-16 minutes;

[0023] S3204: Pre-oxidation, at 800°C, introduce nitrogen and oxygen, nitrogen flow rate 1-1.5 L / min, oxygen flow rate 2-2.5 L / min, time 9-11 min;

[0024] S3205: Raise the temperature from 800°C to 850°C, introducing nitrogen, oxygen and boron trichloride in a stepwise manner during the heating process;

[0025] S3206: Heating, ramping from 850°C to 950°C, introducing nitrogen during the heating process, with a nitrogen flow rate of 2-2.5 L / min, a furnace pressure of 390-410 mbar, and a heating time of 19-21 minutes;

[0026] S3207: Constant temperature at 950°C. During the constant temperature process, nitrogen is added at a flow rate of 2-2.5 L / min, the furnace pressure is 400 mbar, and the time is 19-21 minutes.

[0027] S3208: Heating, ramping from 950°C to 1050°C, introducing nitrogen and oxygen during the heating process, with a nitrogen flow rate of 1-1.5 L / min, an oxygen flow rate of 10-15 L / min, a furnace pressure of 590-610 mbar, and a heating time of 9-11 minutes;

[0028] S3209: Oxidation: dry oxidation at 1050°C for 2 minutes. Oxygen and nitrogen are introduced during the dry oxidation process. The nitrogen flow rate is 1-1.5 L / min, the oxygen flow rate is 10-15 L / min, the furnace pressure is 590-610 mbar, and the drying time is 115-125 minutes.

[0029] S3210: Cooling oxidation, the temperature is reduced from 1050℃ to 800℃, oxygen and nitrogen are introduced during the cooling process, the nitrogen flow rate is 0.1-0.15L / min, the oxygen flow rate is 10-15L / min, the furnace tube pressure is 590-610mbar, and the cooling time is 29-31min;

[0030] S3211: Break the vacuum by introducing nitrogen to break the vacuum to normal pressure;

[0031] S3212: Released.

[0032] A method for preparing a battery cell comprises the following steps:

[0033] S00: Texturing, etching the surface of the silicon wafer to form a velvet surface;

[0034] S01: Loading the boat: inserting silicon wafers into a quartz boat in sections. The quartz boat includes an upper single-wafer area, a lower single-wafer area, and a double-wafer area. The double-wafer area is located between the upper single-wafer area and the lower single-wafer area. The upper single-wafer area and the lower single-wafer area are loaded with single silicon wafers, and the double-wafer area is loaded with double silicon wafers.

[0035] S02: Phosphorus diffusion, phosphorus diffusion is performed on the silicon wafer to form a PN junction;

[0036] S03: Laser, laser grooves the textured surface of the silicon wafer, and laser local doping is performed on the grooved area;

[0037] S04: Etching: polishing the silicon wafer, removing the edge PN junction and the phosphorus silicon glass, so that the side of the silicon wafer loaded in the upper single-chip area and the lower single-chip area that is not facing the double-chip area forms a non-diffusion surface;

[0038] S05: Annealing, growing an oxide layer before the passivation layer on the silicon wafer surface;

[0039] S06: ALD, growing an aluminum oxide passivation layer on the back of the silicon wafer;

[0040] S07: Back film, growing a silicon nitride film on the back of the silicon wafer;

[0041] S08: positive film, growing silicon nitride thin film on the front side of the silicon wafer;

[0042] S09: Screen printing, printing the front and back electrodes, and sintering the printed silicon wafer.

[0043] A method for preparing a battery cell comprises the following steps:

[0044] S30: Texturing, etching the surface of the silicon wafer to form a velvet surface;

[0045] S31: Loading the boat: inserting the silicon wafers into the quartz boat in sections. The quartz boat includes an upper single-wafer area, a lower single-wafer area, and a double-wafer area. The double-wafer area is located between the upper single-wafer area and the lower single-wafer area. The upper single-wafer area and the lower single-wafer area are loaded with single silicon wafers, and the double-wafer area is loaded with double silicon wafers.

[0046] S32: Boron diffusion, boron diffusion is performed on the silicon wafer to form a PN junction;

[0047] S33: Etching, polishing the silicon wafer, removing the edge PN junction and removing the phosphorus silicon glass, so that the side of the silicon wafer loaded in the upper single-chip area and the lower single-chip area that is not facing the double-chip area forms a non-diffusion surface;

[0048] S34: LPCVD, growing oxide layer and amorphous silicon layer;

[0049] S35: Phosphorus doping: Phosphorus is diffused in the silicon wafer to form a phosphorus doped region;

[0050] S36: Cleaning, removing the dead layer BSG on the surface of the silicon wafer, and chemically polishing the back of the silicon wafer;

[0051] S37: ALD, growing an aluminum oxide passivation layer on a silicon wafer;

[0052] S38: positive film, growing silicon nitride film on the front side of the silicon wafer;

[0053] S39: Back film, growing silicon nitride film on the back of the silicon wafer;

[0054] S40: Screen printing, printing the front and back electrodes, and sintering the printed silicon wafer.

[0055] Furthermore, the quartz boat includes an upper single wafer area, a lower single wafer area and a double wafer area. The double wafer area is located between the upper single wafer area and the lower single wafer area. The upper single wafer area and the lower single wafer area are used to load single silicon wafers, and the double wafer area is used to load double silicon wafers.

[0056] Furthermore, the side of the upper single-chip region and the lower single-chip region where the silicon wafers are loaded and facing the double-chip region is a diffusion surface, and the side not facing the double-chip region is a non-diffusion surface.

[0057] Furthermore, the step S34 further includes the following steps:

[0058] Load the boat and insert the silicon wafers into the quartz boat in sections. The quartz boat includes an upper single-wafer area, a lower single-wafer area and a double-wafer area. The double-wafer area is located between the upper single-wafer area and the lower single-wafer area. The upper single-wafer area and the lower single-wafer area are loaded with single silicon wafers, and the double-wafer area is loaded with double silicon wafers.

[0059] Furthermore, the quartz boat includes a plurality of vertical rods, and the direction in which the silicon wafer is inserted into the quartz boat is parallel to the horizontal diffusion direction of the airflow.

[0060] Furthermore, the vertical rod located in the dual-chip area is provided with a plurality of second slots, which are distributed along the length direction of the vertical rod, and the second slots carry the dual silicon wafers.

[0061] Furthermore, the vertical rod located in the upper monolithic area is provided with at least one first slot, and several first slots are distributed along the length direction of the vertical rod, and the first slot carries a monolithic silicon wafer. The vertical rod located in the lower monolithic area is provided with at least one third slot, and several third slots are distributed along the length direction of the vertical rod, and the lower monolithic slot carries a monolithic silicon wafer.

[0062] In summary, the present invention is beneficial in that:

[0063] 1) The present invention does not require changes to the existing structure of the heat field and quartz furnace tubes. Silicon wafers are loaded in partitions in the quartz boat, eliminating the cost of hardware changes.

[0064] 2) The present invention does not require dummy sheets to be loaded on the upper and lower ends of the quartz boat, thus solving the technical problem that dummy sheets break after long-term use and need to be replaced.

[0065] 3) The present invention loads single silicon wafers in the single-wafer and lower single-wafer regions of a quartz boat, and double silicon wafers in the double-wafer region. During diffusion, the double silicon wafers are diffused on one side, while the single silicon wafers are diffused on both sides. The side of the silicon wafers loaded in the upper and lower single-wafer regions facing the double-wafer region serves as the diffusion surface, while the side not facing the double-wafer region serves as the non-diffusion surface. The side of the silicon wafer not facing the double-wafer region is completely etched after diffusion to remove any surrounding diffusion, thereby forming a non-diffusion surface and eliminating the low square resistance effect caused by the silicon wafer's proximity to the thermal field. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 This is an implementation method of the quartz boat carrying silicon wafers of the present invention.

[0067] Figure 2 This is another embodiment of the quartz boat carrying silicon wafers of the present invention.

[0068] Figure 3 This is a flow chart of the silicon wafer preparation process according to Example 1 of the present invention.

[0069] Figure 4 This is a flow chart of the silicon wafer preparation process of Example 2 of the present invention.

[0070] Markings in the figure: quartz boat 1, upper single-wafer area 11, first slot 110, double-wafer area 12, second slot 120, lower single-wafer area 13, third slot 130, vertical rod 14, end plate 15, silicon wafer 2, quartz furnace tube 3. DETAILED DESCRIPTION

[0071] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0072] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0073] All directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, horizontal, vertical...) are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0074] Example 1:

[0075] like Figure 1-2 As shown, the present invention provides a quartz boat for silicon wafer diffusion, comprising an upper single wafer area 11, a lower single wafer area 13, and a double wafer area 12. The double wafer area 12 is located between the upper single wafer area 11 and the lower single wafer area 13. The upper single wafer area 11 and the lower single wafer area 13 are loaded with single silicon wafers 2, while the double wafer area 12 is loaded with double silicon wafers 2. In S01, the upper single wafer area 11 and the lower single wafer area 13 of the quartz boat 1 are closer to the thermal field of the quartz furnace tube 3 than the double wafer area 12.

[0076] The silicon wafers loaded in the upper single-chip region 11 and the lower single-chip region 13 have their surfaces facing the double-chip region 12 as diffusion surfaces. Figure 1 and 2 The b-side shown is the side not facing the double-chip region 12 and is a non-diffusion side. Figure 1 and 2 The side of the silicon wafer that is not facing the double-chip region 12 is completely removed by etching after diffusion or other similar processes to form a non-diffusion surface, eliminating the low square resistance effect caused by the silicon wafer being close to the thermal field.

[0077] The quartz boat 1 includes a plurality of vertical rods 14 . End plates 15 are fixed to the upper and lower ends of the plurality of vertical rods 14 , respectively. The vertical rods 14 and the end plates 15 constitute the overall structure of the quartz boat 1 .

[0078] The length direction of the vertical rod 14 of the quartz boat 1 is perpendicular or approximately perpendicular to the axial direction of the quartz furnace tube 3, and the direction in which the silicon wafer is inserted into the quartz boat 1 is parallel or approximately parallel to the horizontal diffusion direction of the airflow. Figure 1 From a visual perspective, the upper and lower ends of the quartz boat 1 are closer to the thermal field of the quartz furnace tube 3. The upper end of the quartz boat 1 forms the upper single-wafer area 11, the lower end forms the lower single-wafer area 13, and the middle end of the quartz boat 1 forms the double-wafer area 12. Compared with the lower single-wafer area 13, the upper single-wafer area 11 of the quartz boat 1 is closer to the thermal field of the quartz furnace tube 3. The double-wafer area 12 is located between the upper single-wafer area 11 and the lower single-wafer area 13. The upper single-wafer area 11, the lower single-wafer area 13, and the double-wafer area 12 constitute the entire silicon wafer loading area of ​​the quartz boat 1.

[0079] The vertical rod 14 is provided with a plurality of second slots 120 at the position of the double-wafer area 12 . The plurality of second slots 120 are distributed along the length direction of the vertical rod 14 . The second slots 120 support the double silicon wafers 2 . The height of the second slots 120 is greater than the height of the two groups of silicon wafers 2 .

[0080] The vertical rod 14 is provided with a plurality of first slots 110 at a position located on the upper monolithic region 11. The plurality of first slots 110 are distributed along the length direction of the vertical rod 14. The first slots 110 carry the monolithic silicon wafer 2. The height of the first slots 110 is greater than the height of the monolithic silicon wafer 2. The number of the first slots 110 is at least one. Figure 2 As shown, it is preferably set to two, compared with setting one first slot 110, it not only further ensures that the silicon wafers 2 in the double-wafer area 12 are prevented from having a low square resistance, but also does not affect the production capacity of silicon wafers in a single furnace.

[0081] The vertical rod 14 is provided with a plurality of third slots 130 at the position of the lower single-chip area 13. The plurality of third slots 130 are distributed along the length direction of the vertical rod 14. The third slots 130 carry the single silicon wafer 2. The height of the third slots 130 is greater than the height of the single silicon wafer 2. The number of the third slots 130 is at least one. Figure 2 As shown, it is preferably set to two, and the reason is the same as setting the first slot 110.

[0082] The two silicon wafers 2 in the double-wafer area 12 are offset against each other to achieve single-sided diffusion.

[0083] In addition, the number of strips provided in the first slot 110 and the third slot 130 can be further adjusted according to actual conditions.

[0084] The inserting method of the silicon wafer in this embodiment is not limited to the horizontal diffusion method.

[0085] like Figure 3 As shown, taking P-type silicon wafer as an example:

[0086] The present invention provides a silicon wafer diffusion method using the quartz boat 1, comprising the following steps:

[0087] S01: Loading the boat: insert the silicon wafer 2 into the quartz boat 1 in sections. The quartz boat 1 includes an upper single-wafer area 11, a lower single-wafer area 13, and a double-wafer area 12. The double-wafer area 12 is located between the upper single-wafer area 11 and the lower single-wafer area 13. The upper single-wafer area 11 and the lower single-wafer area 13 are loaded with single silicon wafers 2, and the double-wafer area 12 is loaded with double silicon wafers 2.

[0088] S02: Phosphorus diffusion: Phosphorus is diffused into the silicon wafer 2 to form a PN junction.

[0089] The specific steps of phosphorus diffusion in SO2 are as follows:

[0090] S021: Place the quartz boat 1 carrying the silicon wafer 2 into the quartz furnace tube 3;

[0091] S022: Vacuum leak detection;

[0092] S023: After the furnace tube is heated to 770-790°C, preferably to 770°C, oxygen and nitrogen are introduced at an oxygen flow rate of 1-1.5 L / min, preferably 1 L / min, and a nitrogen flow rate of 3-3.5 L / min, preferably 3 L / min. The furnace tube pressure is 150-170 mbar, preferably 160 mbar, and the time is 4-6 min, preferably 5 min;

[0093] S024: constant temperature 770-790 ° C, nitrogen carries phosphorus oxychloride, mixed oxygen and nitrogen are introduced from the furnace tail, the nitrogen carrying phosphorus oxychloride is a small flow nitrogen, the flow rate of the small flow nitrogen is 1.2-1.5 L / min, preferably 1.2 L / min, the flow rate of oxygen is 0.8-1 L / min, preferably 0.8 L / min, and the nitrogen mixed with oxygen is a large flow nitrogen, the flow rate of the large flow nitrogen is 3-3.5 L / min, preferably 3 L / min, the furnace tube pressure is 150-170 mbar, preferably 160 mbar, the time is 11-13 min, preferably 12 min;

[0094] S025: ramp temperature from 770°C to 845°C, oxygen flow rate 1-1.5 L / min, preferably 1 L / min, nitrogen flow rate 3-3.5 L / min, preferably 3 L / min, furnace pressure 150-170 mbar, preferably 160 mbar, time 9-11 min, preferably 10 min;

[0095] S026: Maintaining the temperature at 845°C, supplementing nitrogen during the temperature-maintaining process, with a nitrogen flow rate of 3-3.5 L / min, preferably 3 L / min, and a furnace pressure of 160 mbar, for 9-11 minutes, preferably 10 minutes;

[0096] S027: Cooling, preferably to 800°C, returning to normal pressure through nitrogen, and taking the product out of the furnace.

[0097] The present invention provides a method for preparing a solar cell using the above-mentioned silicon wafer diffusion method, comprising the following steps:

[0098] S00: Texturing, etching the surface of the silicon wafer to form a velvet surface;

[0099] S01: Loading the boat: insert silicon wafers into the quartz boat 1 in sections. The quartz boat 1 includes an upper single-wafer area 11, a lower single-wafer area 13, and a double-wafer area 12. The double-wafer area 12 is located between the upper single-wafer area 11 and the lower single-wafer area 13. The upper single-wafer area 11 and the lower single-wafer area 13 are loaded with single silicon wafers 2, and the double-wafer area 12 is loaded with double silicon wafers 2.

[0100] S02: Phosphorus diffusion, phosphorus diffusion is performed on the silicon wafer to form a PN junction;

[0101] S03: Laser, laser grooves the textured surface of the silicon wafer, and laser local doping is performed on the grooved area;

[0102] S04: Etching: polishing the silicon wafer, removing the edge PN junction and the phosphorus silicon glass, so that the side of the silicon wafer loaded in the upper single-chip area and the lower single-chip area that is not facing the double-chip area forms a non-diffusion surface;

[0103] S05: Annealing, growing an oxide layer before the passivation layer on the silicon wafer surface;

[0104] S06: ALD, growing an aluminum oxide passivation layer on the back of the silicon wafer;

[0105] S07: Back film, growing a silicon nitride film on the back of the silicon wafer;

[0106] S08: positive film, growing silicon nitride thin film on the front side of the silicon wafer;

[0107] S09: Screen printing, printing the front and back electrodes, and sintering the printed silicon wafer.

[0108] In this embodiment, single silicon wafers are loaded into the upper single-wafer area 11 and lower single-wafer area 13 of the quartz boat 1, while dual silicon wafers are loaded into the dual-wafer area 12. During diffusion, dual silicon wafers are diffused on one side, while single silicon wafers are diffused on both sides. The side of the silicon wafers loaded into the upper single-wafer area 11 and lower single-wafer area 13 that does not face the dual-wafer area is completely etched after diffusion to remove any wraparound, thereby forming a non-diffusion surface and eliminating the low sheet resistance effect caused by the silicon wafer's proximity to the thermal field.

[0109] In this embodiment, the steps of texturing, laser, etching, annealing, ALD, back film, front film and screen printing are all conventional steps in the prior art, and the present invention will not elaborate on the specific details.

[0110] Example 2:

[0111] like Figure 4 As shown, taking N-type silicon wafer as an example:

[0112] The present invention provides a silicon wafer diffusion method using the quartz boat 1, comprising the following steps:

[0113] S30: Loading the boat: inserting the silicon wafers 2 into the quartz boat 1 in sections. The quartz boat 1 includes an upper single-wafer area 11, a lower single-wafer area 13, and a double-wafer area 12. The double-wafer area 12 is located between the upper single-wafer area 11 and the lower single-wafer area 13. The upper single-wafer area 11 and the lower single-wafer area 13 are loaded with single silicon wafers 2, and the double-wafer area 12 is loaded with double silicon wafers 2.

[0114] S3: Boron diffusion: Boron is diffused into the silicon wafer 2 to form a PN junction.

[0115] The structure of the quartz boat 1 in step S30 is the same as that in step S01 , and will not be described in detail here.

[0116] The specific steps of phosphorus diffusion in step S31 are as follows:

[0117] S3101: Place the quartz boat 1 carrying the silicon wafer 2 into the quartz furnace tube 3;

[0118] S3102: Vacuum leak detection;

[0119] S3103: Heating, ramping from 770°C to 800°C, introducing nitrogen, with a furnace pressure of 140-160 mbar, preferably 150 mbar, for 14-16 minutes, preferably 15 minutes;

[0120] S3104: Pre-oxidation, at 800°C, introducing nitrogen and oxygen, with a nitrogen flow rate of 1-1.5 L / min, preferably 1 L / min, and an oxygen flow rate of 2-2.5 L / min, preferably 2 L / min, for 9-11 min, preferably 10 min;

[0121] S3105: Raise the temperature from 800°C to 850°C, introducing nitrogen, oxygen and boron trichloride in a stepwise manner during the heating process:

[0122] S3106: heating from 850°C to 950°C with a ramp rate, introducing nitrogen during the heating process, with a nitrogen flow rate of 2-2.5 L / min, preferably 2 L / min, and a furnace pressure of 390-410 mbar, preferably 400 mbar, for 19-21 min, preferably 20 min;

[0123] S3107: Maintaining the temperature at 950°C, supplementing nitrogen during the temperature control process, with a nitrogen flow rate of 2-2.5 L / min, preferably 2 L / min, and a furnace pressure of 400 mbar for 19-21 minutes, preferably 20 minutes;

[0124] S3108: heating from 950°C to 1050°C with a ramp rate, introducing nitrogen and oxygen during the heating process, with a nitrogen flow rate of 1-1.5 L / min, preferably 1 L / min, and an oxygen flow rate of 10-15 L / min, preferably 10 L / min, and a furnace pressure of 590-610 mbar, preferably 600 mbar, for 9-11 min, preferably 10 min;

[0125] S3109: Oxidation: dry oxidation at 1050°C for 2 minutes, introducing oxygen and nitrogen during the dry oxidation process, with a nitrogen flow rate of 1-1.5 L / min, preferably 1 L / min, an oxygen flow rate of 10-15 L / min, preferably 10 L / min, a furnace pressure of 590-610 mbar, preferably 600 mbar, and a drying time of 115-125 minutes, preferably 120 minutes;

[0126] S3110: cooling oxidation, the temperature is reduced from 1050°C to 800°C, oxygen and nitrogen are introduced during the cooling process, the nitrogen flow rate is 0.1-0.15 L / min, preferably 0.1 L / min, the oxygen flow rate is 10-15 L / min, preferably 10 L / min, the furnace pressure is 590-610 mbar, preferably 600 mbar, and the time is 29-31 min, preferably 30 min;

[0127] S3111: Break the vacuum by introducing nitrogen to break the vacuum to normal pressure;

[0128] S3112: Released.

[0129] S3105 includes the following steps:

[0130] S31051: First stage: After the quartz furnace tube 3 is heated to 800°C, nitrogen, oxygen and boron trichloride are introduced. The nitrogen flow rate is 1.5-2 L / min, preferably 1.5 L / min, the oxygen flow rate is 0.54-1.04 L / min, preferably 0.54 L / min, and the boron trichloride flow rate is 0.2-0.7 L / min, preferably 0.2 L / min. The furnace tube pressure is 140-160 mbar, preferably 150 mbar. The time is 1.5-2.5 minutes, preferably 2 minutes.

[0131] S31052: Second stage: After the quartz furnace tube 3 is heated to 830°C, nitrogen, oxygen and boron trichloride are introduced. The nitrogen flow rate is 1.5-2 L / min, preferably 1.5 L / min, the oxygen flow rate is 0.54-1.04 L / min, preferably 0.54 L / min, and the boron trichloride flow rate is 0.2-0.7 L / min, preferably 0.2 L / min. The furnace tube pressure is 140-160 mbar, preferably 150 mbar. The time is 3.5-4.5 minutes, preferably 4 minutes.

[0132] S31053: The third stage: After the quartz furnace tube 3 is heated to 830°C, nitrogen, oxygen and boron trichloride are introduced, with a nitrogen flow rate of 1.5-2 L / min, preferably 1.5 L / min, an oxygen flow rate of 0.54-1.04 L / min, preferably 0.54 L / min, and a boron trichloride flow rate of 0.2-0.7 L / min, preferably 0.2 L / min. The furnace tube pressure is 140-160 mbar, preferably 150 mbar; the time is 3.5-4.5 min, preferably 4 min.

[0133] The present invention provides a method for preparing a solar cell using the above-mentioned silicon wafer diffusion method, comprising the following steps:

[0134] S30: Texturing, etching the surface of the silicon wafer to form a velvet surface;

[0135] S31: Loading the boat: inserting the silicon wafers into the quartz boat 1 in sections. The quartz boat 1 includes an upper single wafer area 11, a lower single wafer area 13, and a double wafer area 12. The double wafer area 12 is located between the upper single wafer area 11 and the lower single wafer area 13. The upper single wafer area 11 and the lower single wafer area 13 are loaded with single silicon wafers 2, and the double wafer area 12 is loaded with double silicon wafers 2.

[0136] S32: Boron diffusion, boron diffusion is performed on the silicon wafer to form a PN junction;

[0137] S33: Etching, polishing the silicon wafer, removing the edge PN junction and removing the phosphorus silicon glass, so that the side of the silicon wafer loaded in the upper single-chip area and the lower single-chip area that is not facing the double-chip area forms a non-diffusion surface;

[0138] S34: LPCVD, growing oxide layer and amorphous silicon layer;

[0139] Loading the boat: insert the silicon wafers into the quartz boat 1 in sections. The quartz boat 1 includes an upper single-wafer area 11, a lower single-wafer area 13, and a double-wafer area 12. The double-wafer area 12 is located between the upper single-wafer area 11 and the lower single-wafer area 13. The upper single-wafer area 11 and the lower single-wafer area 13 are loaded with single silicon wafers 2, and the double-wafer area 12 is loaded with double silicon wafers 2;

[0140] S35: Phosphorus doping: Phosphorus is diffused in the silicon wafer to form a phosphorus doped region;

[0141] S36: Cleaning, removing the dead layer BSG on the surface of the silicon wafer, and chemically polishing the back of the silicon wafer;

[0142] S37: ALD, growing an aluminum oxide passivation layer on a silicon wafer;

[0143] S38: positive film, growing silicon nitride film on the front side of the silicon wafer;

[0144] S39: Back film, growing silicon nitride film on the back of the silicon wafer;

[0145] S40: Screen printing, printing the front and back electrodes, and sintering the printed silicon wafer.

[0146] In this embodiment, single silicon wafers are loaded into the upper single-wafer area 11 and lower single-wafer area 13 of the quartz boat 1, while dual silicon wafers are loaded into the dual-wafer area 12. During diffusion, dual silicon wafers are diffused on one side, while single silicon wafers are diffused on both sides. The side of the silicon wafers loaded into the upper single-wafer area 11 and lower single-wafer area 13 that does not face the dual-wafer area is completely etched after diffusion to remove any wraparound, thereby forming a non-diffusion surface and eliminating the low sheet resistance effect caused by the silicon wafer's proximity to the thermal field.

[0147] In addition, during the LPCVD process, during deposition, single-sided deposition is used for the double-wafer silicon wafer, and double-sided deposition is used for the single-wafer silicon wafer. The side of the silicon wafer loaded in the upper single-wafer area 11 and the lower single-wafer area 13 that is not facing the double-wafer area is doped with phosphorus and then completely removed through a cleaning process, thereby eliminating the low square resistance effect of the silicon wafer caused by being close to the thermal field.

[0148] In this embodiment, the steps of texturing, etching, phosphorus doping, cleaning, ALD, positive film, back film and screen printing are all conventional steps in the prior art, and the present invention will not elaborate on the specific details.

[0149] The silicon wafers loaded in the upper monolithic area 11 and the lower monolithic area 13 using the cell preparation methods of Example 1 and Example 2 are used as examples. Each time the furnace tube detects the silicon wafer at the same position, the data of 5 silicon wafers are detected continuously. A dummy wafer is added to resist heat radiation, and the silicon wafer at the same detection position as the example is used as a comparative example. The example and the comparative example respectively detect the square resistance located on the diffusion surface of the silicon wafer. The other implementation methods in the comparative example are consistent with the example.

[0150] Comparative Example:

[0151] Dummy wafers were added to the upper and lower ends of the quartz boat 1 to block heat radiation, and the square resistance (ohm) of the silicon wafer was tested to obtain Table 1.

[0152] Table 1

[0153]

[0154] As shown in Table 1, the dummy wafer can improve the impact of thermal radiation in the thermal field. However, after the dummy wafer is used many times, the source amount on the dummy wafer reaches saturation and becomes ineffective, causing the silicon wafer close to the dummy wafer to absorb more diffusion sources, resulting in a gradual decrease in the surface resistance of the silicon wafer close to the dummy wafer. A new dummy wafer needs to be replaced, which increases the cost.

[0155] Example:

[0156] The upper single-wafer area 11 of the quartz boat 1 is loaded with a single silicon wafer, and the double-wafer area 12 of the quartz boat 1 is loaded with double silicon wafers. The square resistance (ohm) of the silicon wafers is tested to obtain Table 2;

[0157] Table 2

[0158]

[0159] Table 2 shows that the solution of the embodiment can mitigate the effects of thermal field radiation. After multi-tube testing, the sheet resistance of the silicon wafer diffusion surface is not affected by low sheet resistance and fluctuates within a very small range, maintaining a relatively stable state. Furthermore, the structure is simple and modification is easy. Compared with the technical solution of the comparative example that adds dummy sheets to resist thermal radiation, which fails after frequent use and reaches saturation of the source, requiring replacement, the solution of the embodiment is more effective in improving thermal field radiation and is less costly.

[0160] Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

Claims

1. A silicon wafer diffusion method, characterized in that: The following steps are involved: S01: Loading the boat: inserting silicon wafers into a quartz boat in sections. The quartz boat includes an upper single-wafer area, a lower single-wafer area, and a double-wafer area. The double-wafer area is located between the upper single-wafer area and the lower single-wafer area. The upper single-wafer area and the lower single-wafer area are loaded with single silicon wafers, and the double-wafer area is loaded with double silicon wafers. The direction in which the silicon wafer is inserted into the quartz boat is parallel or approximately parallel to the horizontal diffusion direction of the airflow; The side of the silicon wafers loaded in the upper single-chip area and the lower single-chip area facing the double-chip area is a diffusion surface, and the side not facing the double-chip area is a non-diffusion surface; S02: Phosphorus diffusion, phosphorus is diffused into the silicon wafer to form a PN junction.

2. The silicon wafer diffusion method according to claim 1, wherein: In step S02, phosphorus diffusion includes the following steps: S021: Place the quartz boat carrying the silicon wafer into the quartz furnace tube; S022: Vacuum leak detection; S023: After the furnace tube is heated to 770-790°C, oxygen and nitrogen are introduced at an oxygen flow rate of 1-1.5 L / min and a nitrogen flow rate of 3-3.5 L / min. The furnace tube pressure is 150-170 mbar and the time is 4-6 minutes. S024: constant temperature 770-790℃, nitrogen carries phosphorus oxychloride, mixed oxygen and nitrogen are introduced from the furnace tail, oxygen flow rate is 0.8-1L / min, furnace tube pressure is 150-170mbar, time is 11-13min; S025: ramp temperature from 770°C to 845°C, oxygen flow rate 1-1.5 L / min, nitrogen flow rate 3-3.5 L / min, furnace pressure 150-170 mbar, time 9-11 min; S026: Maintain temperature at 845°C. During the temperature maintenance process, nitrogen is added at a flow rate of 3-3.5 L / min, the furnace pressure is 160 mbar, and the time is 9-11 minutes. S027: Cool down to 800℃, pass nitrogen back to normal pressure, and take out of the furnace.

3. A silicon wafer diffusion method, characterized in that: The following steps are involved: S31: Loading the boat, inserting the silicon wafers into the quartz boat in sections, the quartz boat including an upper single wafer area, a lower single wafer area and a double wafer area, the double wafer area being located between the upper single wafer area and the lower single wafer area, The upper single-wafer area and the lower single-wafer area are loaded with single silicon wafers, and the double-wafer area is loaded with double silicon wafers; The direction in which the silicon wafer is inserted into the quartz boat is parallel or approximately parallel to the horizontal diffusion direction of the airflow; The side of the silicon wafers loaded in the upper single-chip area and the lower single-chip area facing the double-chip area is a diffusion surface, and the side not facing the double-chip area is a non-diffusion surface; S32: Boron diffusion, boron diffusion is performed on the silicon wafer to form a PN junction.

4. The silicon wafer diffusion method according to claim 3, wherein: In step S32, the boron diffusion includes the following steps: S3201: Place the quartz boat carrying the silicon wafer into the quartz furnace tube; S3202: Vacuum leak detection; S3203: Heating, ramping from 770°C to 800°C, introducing nitrogen, with a furnace pressure of 140-160 mbar, for 14-16 minutes; S3204: Pre-oxidation, at 800°C, introduce nitrogen and oxygen, nitrogen flow rate 1-1.5 L / min, oxygen flow rate 2-2.5 L / min, time 9-11 min; S3205: Raise the temperature from 800°C to 850°C, introducing nitrogen, oxygen and boron trichloride in a stepwise manner during the heating process; S3206: Heating, ramping from 850°C to 950°C, introducing nitrogen during the heating process, with a nitrogen flow rate of 2-2.5 L / min, a furnace pressure of 390-410 mbar, and a heating time of 19-21 minutes; S3207: Constant temperature 950℃, during the constant temperature process, nitrogen is added, and the nitrogen flow rate is 2-2.5L / min, The furnace tube pressure is 400 mbar and the time is 19-21 minutes; S3208: Heating, ramping from 950°C to 1050°C, introducing nitrogen and oxygen during the heating process. Nitrogen flow rate 1-1.5L / min, oxygen flow rate 10-15L / min, furnace tube pressure 590-610mbar, time 9-11min; S3209: Oxidation: dry oxidation at 1050°C for 2 minutes. Oxygen and nitrogen are introduced during the dry oxidation process. The nitrogen flow rate is 1-1.5 L / min, the oxygen flow rate is 10-15 L / min, the furnace pressure is 590-610 mbar, and the drying time is 115-125 minutes. S3210: Cooling oxidation, the temperature is reduced from 1050℃ to 800℃, oxygen and nitrogen are introduced during the cooling process, the nitrogen flow rate is 0.1-0.15L / min, the oxygen flow rate is 10-15L / min, the furnace tube pressure is 590-610mbar, and the cooling time is 29-31min; S3211: Break the vacuum by introducing nitrogen to break the vacuum to normal pressure; S3212: Released.

5. A method for preparing a battery cell, characterized in that: The following steps are involved: S00: Texturing, etching the surface of the silicon wafer to form a velvet surface; S01: Loading the boat: inserting silicon wafers into a quartz boat in sections. The quartz boat includes an upper single-wafer area, a lower single-wafer area, and a double-wafer area. The double-wafer area is located between the upper single-wafer area and the lower single-wafer area. The upper single-wafer area and the lower single-wafer area are loaded with single silicon wafers, and the double-wafer area is loaded with double silicon wafers. S02: Phosphorus diffusion, phosphorus diffusion is performed on the silicon wafer to form a PN junction; S03: Laser, laser grooves the textured surface of the silicon wafer, and laser local doping is performed on the grooved area; S04: Etching: polishing the silicon wafer, removing the edge PN junction and the phosphorus silicon glass, so that the side of the silicon wafer loaded in the upper single-chip area and the lower single-chip area that is not facing the double-chip area forms a non-diffusion surface; S05: Annealing, growing an oxide layer before the passivation layer on the silicon wafer surface; S06: ALD, growing an aluminum oxide passivation layer on the back of the silicon wafer; S07: Back film, growing a silicon nitride film on the back of the silicon wafer; S08: positive film, growing silicon nitride thin film on the front side of the silicon wafer; S09: Screen printing, printing the front and back electrodes, and sintering the printed silicon wafer.

6. A method for preparing a battery cell, characterized in that: The following steps are involved: S30: Texturing, etching the surface of the silicon wafer to form a velvet surface; S31: Loading the boat: inserting the silicon wafers into the quartz boat in sections. The quartz boat includes an upper single-wafer area, a lower single-wafer area, and a double-wafer area. The double-wafer area is located between the upper single-wafer area and the lower single-wafer area. The upper single-wafer area and the lower single-wafer area are loaded with single silicon wafers, and the double-wafer area is loaded with double silicon wafers. S32: Boron diffusion, boron diffusion is performed on the silicon wafer to form a PN junction; S33: Etching, polishing the silicon wafer, removing the edge PN junction and removing the phosphorus silicon glass, so that the side of the silicon wafer loaded in the upper single-chip area and the lower single-chip area that is not facing the double-chip area forms a non-diffusion surface; S34: LPCVD, growing oxide layer and amorphous silicon layer; S35: Phosphorus doping: Phosphorus is diffused in the silicon wafer to form a phosphorus doped region; S36: Cleaning, removing the dead layer BSG on the surface of the silicon wafer, and chemically polishing the back of the silicon wafer; S37: ALD, growing an aluminum oxide passivation layer on a silicon wafer; S38: positive film, growing silicon nitride film on the front side of the silicon wafer; S39: Back film, growing silicon nitride film on the back of the silicon wafer; S40: Screen printing, printing the front and back electrodes, and sintering the printed silicon wafer.

7. A silicon wafer diffusion method according to claim 1 or 3, characterized in that: The side of the upper single-chip area and the lower single-chip area where the silicon chips are loaded and facing the double-chip area is a diffusion surface, and the side not facing the double-chip area is a non-diffusion surface.

8. The method for preparing a battery cell according to claim 6, wherein: The step S34 further includes the following steps: Load the boat and insert the silicon wafers into the quartz boat in sections. The quartz boat includes an upper single-wafer area, a lower single-wafer area and a double-wafer area. The double-wafer area is located between the upper single-wafer area and the lower single-wafer area. The upper single-wafer area and the lower single-wafer area are loaded with single silicon wafers, and the double-wafer area is loaded with double silicon wafers.

9. The silicon wafer diffusion method according to claim 7, wherein: The quartz boat comprises a plurality of vertical rods along the vertical direction, and the direction in which the silicon slices are inserted into the quartz boat is parallel to the horizontal diffusion direction of the airflow.

10. The silicon wafer diffusion method according to claim 9, wherein: The vertical rod located in the double-chip area is provided with a plurality of second slots, which are distributed along the length direction of the vertical rod, and the second slots carry double silicon wafers. The vertical rod located in the upper single-chip area is provided with at least one group of first slots, which are distributed along the length direction of the vertical rod, and the first slots carry single silicon wafers. The vertical rod located in the lower single-chip area is provided with at least one group of third slots, which are distributed along the length direction of the vertical rod, and the lower single-chip slots carry single silicon wafers.

Images