3D Memory, Preparation Method and Storage System

Abstract

The present application provides a three-dimensional memory, a manufacturing method, and a storage system. The memory includes: a stacked structure including a plurality of stepped levels, each stepped level including an insulating layer and a gate layer disposed on the insulating layer. The gate layer includes a gate conductor layer and a gate dielectric layer that are adjacent to each other in a plane perpendicular to a first direction, and the first direction is the stacking direction of the stacked structure; a connection structure covers a partial surface of the gate dielectric layer of a corresponding stepped level and is electrically connected to a portion of the gate conductor layer that is outside the gate dielectric layer in a second direction, and the second direction is perpendicular to the first direction; a word line contact extends at least along the first direction to a connection conduction layer of the connection structure and is electrically connected to the corresponding gate conductor layer through the connection structure. The word line contact is located on a partial surface of the gate dielectric layer and is electrically connected to the corresponding gate conductor layer through the connection structure of the corresponding stepped level, which can avoid word line bridging between different gate layers and improve the reliability of the three-dimensional memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more particularly, to a structure of a three-dimensional memory, a method for manufacturing a three-dimensional memory, and a storage system. Background Art

[0002] The three-dimensional memory includes a stacked structure formed by alternately stacking gate layers and insulating layers, and word line contacts located in the stepped areas of the stacked structure can achieve electrical connection between the gates and external circuits.

[0003] With the improvement of the integration degree of three-dimensional memories and the increase in the number of stacked layers, the maximum depth of word line contacts is increasingly deepened. Therefore, during the process of forming contact holes for filling word line contacts, the corresponding gate layers are extremely likely to be penetrated.

[0004] Therefore, how to achieve effective electrical connection between word line contacts and gate layers without affecting the overall performance of three-dimensional memories is an urgent problem to be solved at present. Summary of the Invention

[0005] This application provides a three-dimensional memory, a manufacturing method, and a storage system that can at least partially solve the above problems existing in the related art.

[0006] On the one hand, this application provides a three-dimensional memory, which includes: a stacked structure including a plurality of stepped steps, each stepped step including an insulating layer and a gate layer disposed on the insulating layer, wherein the gate layer includes a gate conductor layer and a gate dielectric layer that are adjacent to each other in a plane perpendicular to a first direction, and the first direction is the stacking direction of the stacked structure; a connection structure covering a partial surface of the gate dielectric layer of the corresponding stepped step and electrically connecting to a portion of the gate conductor layer located outside the gate dielectric layer in a second direction, the second direction being perpendicular to the first direction; and a word line contact extending at least along the first direction to a connection conduction layer of the connection structure and electrically connecting to the corresponding gate conductor layer through the connection structure.

[0007] In one embodiment, the memory further includes a gate line gap structure penetrating the stacked structure along the first direction, and a plurality of the gate line gap structures are spaced apart from each other in the second direction; the gate dielectric layer located between two adjacent gate line gap structures includes a top surface, and two side surfaces adjacent to the top surface and opposite to each other in the second direction; and the connection structure covers the top surface and the side surfaces of the gate dielectric layer of the corresponding stepped step.

[0008] In one embodiment, the gate line gap structure includes a gate line gap and a gap filling dielectric layer filled in the gate line gap. Among them, the length D1 in the second direction of the portion of the gate conductor layer located outside the gate dielectric layer in the second direction satisfies: 20 nm ≤ D1 ≤ D2 / 2, where D2 is the width of the gate line gap in the second direction.

[0009] In one embodiment, the thickness H1 in the first direction of the portion of the connection structure covering the top surface satisfies: H1 ≥ 1.1 × H2, where H2 is the thickness of the gate dielectric layer in the first direction.

[0010] In one embodiment, the stacked structure is divided into a storage array region and a stepped region including a plurality of the stepped steps. Among them, the gate conductor layer is located in the storage array region and the stepped region, and the gate dielectric layer is located in the stepped region.

[0011] In one embodiment, the memory further includes: a channel structure located in the storage array region and penetrating the stacked structure along the first direction. Among them, the portion of the gate conductor layer located in the storage array region is located between the gate dielectric layer and the channel structure, and is located between adjacent channel structures and connected to the channel structure.

[0012] In one embodiment, the connection structure sequentially includes an insulating wrapping layer, a connection conduction layer, and a connection structure filling layer from outside to inside.

[0013] In one embodiment, the memory further includes: a first semiconductor layer; and a channel structure, the channel layer of which penetrates the stacked structure along the first direction and extends to the first semiconductor layer.

[0014] In one embodiment, the channel layer includes a first region and a second region along the first direction. The first region includes the portion of the channel layer extending into and adjacent to the first semiconductor layer, and the second region is located on the side of the first region away from the first semiconductor layer. Among them, the doping concentration of conductive impurities in the first region is greater than that in the second region.

[0015] In one embodiment, the memory further includes: a second semiconductor layer; a channel structure, the channel layer of which penetrates the stacked structure along the first direction and extends through the second semiconductor layer. Among them, the second semiconductor layer is connected to the side portion of the channel layer.

[0016] In one embodiment, the memory further includes a channel structure, and the channel structure includes: a channel hole penetrating the stacked structure along the first direction, an epitaxial layer located at the bottom of the channel hole, a functional layer located on the inner wall of the channel hole and the epitaxial layer, and a channel layer located on the surface of the functional layer and connecting to the epitaxial layer through the functional layer.

[0017] In one embodiment, the stacked structure includes a plurality of memory array regions and a plurality of step regions, the channel structure is located in the memory array region, each memory array region corresponds to at least one step region, and the at least one step region is located in the middle of the corresponding memory array region to divide the corresponding memory array region into at least two sub-memory array regions; alternatively, the at least one step region is located on the side of the corresponding memory array region.

[0018] In one embodiment, the memory further includes: at least one virtual channel structure located at the stepped terrace, wherein the virtual channel structure at least penetrates the corresponding stepped terrace.

[0019] On the other hand, the present application provides a method for manufacturing a three-dimensional memory, and the method includes: alternately stacking an insulating layer and a gate sacrificial layer to form an initial stacked structure; forming a plurality of initial stepped terraces in the step region of the initial stacked structure, and exposing a part of the upper surface of the gate sacrificial layer in each initial stepped terrace; forming a connection sacrificial structure on the exposed upper surface of the gate sacrificial layer, and the connection sacrificial structure includes a connection sacrificial layer; forming a gate line gap penetrating the initial stacked structure, and via the first gate line gap, removing a part of the first gate sacrificial layer adjacent to the first gate line gap to form a first groove, and removing the connection sacrificial layer to form a connection sacrificial void, wherein the first gate line gap is the part of the gate line gap located in the step region, and the first gate sacrificial layer is the part of the gate sacrificial layer located in the step region; and a gate conductor layer is located in the first part of the step region, and the first part is connected to the connection structure.

[0020] In one embodiment, the memory is divided into a storage array region and the step region along a third direction, the gate line gap extends along the third direction through the storage array region and the step region, the third direction is the extending direction of the initial stepped terrace, wherein forming the connection sacrificial void and forming the first groove includes: forming a sealing layer covering the second gate line gap, wherein the second gate line gap is the part of the gate line gap located in the storage array region; and via the first gate line gap, removing a part of the connection sacrificial layer adjacent to the first gate line gap to form a second groove, wherein the opening size of the second groove in a first direction is larger than that of the first groove, the first direction is the stacking direction of the initial stacked structure; filling the first groove and the second groove with a groove filling layer; removing a part of the groove filling layer to expose the remaining connection sacrificial layer; removing the remaining connection sacrificial layer to form the connection sacrificial void; and removing the remaining groove filling layer to expose the first groove.

[0021] In one embodiment, the opening size of the second groove is greater than or equal to 1.1 times that of the first groove.

[0022] In one embodiment, the extending length D12 of the first groove in a second direction satisfies: 20nm ≤ D12 ≤ D2 / 2; and the extending length D11 of the second groove in the second direction satisfies: 20nm ≤ D11 ≤ D2 / 2, wherein D2 is the width of the gate line gap in the second direction; and the second direction is perpendicular to the third direction and the first direction.

[0023] In one embodiment, the method further includes: before forming the connection sacrificial structure, the method further includes: forming an oxide cushion layer on the surface of the stepped terrace; and forming a connection sacrificial structure on the part of the oxide cushion layer corresponding to the exposed upper surface of each gate sacrificial layer; and after removing the connection sacrificial layer, the method further includes: removing the oxide cushion layer to form the connection sacrificial void.

[0024] In one embodiment, the method further includes: removing the sealing layer, and via the second gate line gap, removing the second gate sacrificial layer of the gate sacrificial layer located in the storage array region to form a gate sacrificial void; and forming the part of the gate conductor layer located in the storage array region in the gate sacrificial void, wherein the remaining part of the first gate sacrificial layer serves as a gate dielectric layer.

[0025] In one embodiment, before removing the encapsulation layer, the method further includes: forming a protective layer on the inner wall of the connection sacrificial void and the surface of the remaining groove filling layer via the first gate line gap; and after forming the gate sacrificial void, the method further includes: removing the protective layer.

[0026] In one embodiment, the method further includes: forming the gate conductor layer while forming the connection structure.

[0027] In one embodiment, the method further includes: forming a word line contact hole extending in the first direction, the word line contact hole extending at least to the portion of the conductive material in the connection structure; and filling the word line contact hole to form a word line contact electrically connected to the connection structure.

[0028] In one embodiment, the method further includes: forming a channel hole extending through the initial stacked structure in a first direction and extending to the initial substrate, where the first direction is the stacking direction of the initial stacked structure; sequentially forming a functional layer and a channel layer on the inner wall of the channel hole; removing the initial substrate and exposing the functional layer extending into the initial substrate; removing the exposed functional layer to expose the channel layer corresponding to the removed functional layer; and forming a first semiconductor layer covering the exposed channel layer.

[0029] In one embodiment, after exposing the channel layer corresponding to the removed functional layer, the method further includes: doping the exposed channel layer.

[0030] In one embodiment, the method further includes: forming the initial stacked structure on an initial substrate, the initial substrate including a substrate sacrificial layer; forming a channel hole extending through the initial stacked structure in a first direction and extending through the initial substrate sacrificial layer, where the first direction is the stacking direction of the initial stacked structure; sequentially forming a functional layer and a channel layer on the inner wall of the channel hole; removing the substrate sacrificial layer to form a substrate void, and via the substrate void, removing a partial side surface of the functional layer exposed in the substrate void to expose the channel layer corresponding to the removed functional layer; and filling the substrate void to form a second semiconductor layer extending through the exposed channel layer.

[0031] In one embodiment, the method further includes: forming a channel hole penetrating the initial stacked structure along a first direction, where the first direction is the stacking direction of the initial stacked structure; forming an epitaxial layer at the bottom of the channel hole; forming an initial functional layer on the inner wall of the channel hole and the surface of the epitaxial layer; removing a portion of the initial functional layer located on the surface of the epitaxial layer to form a functional layer and expose a portion of the epitaxial layer; and forming a channel layer connected to the epitaxial layer on the surface of the functional layer and the exposed surface of the epitaxial layer.

[0032] In one embodiment, the connection sacrificial structure further includes an insulating wrapping layer wrapping the connection sacrificial layer. Filling the connection sacrificial void with a conductive material to form a connection structure includes: forming the connection conduction layer on the inner wall of the connection sacrificial void; and filling the remaining space of the connection sacrificial void with the conductive material to form the connection structure.

[0033] In one embodiment, the initial stacked structure includes a plurality of memory array regions and a plurality of step regions. A channel structure is formed in the memory array regions, and each memory array region corresponds to at least one step region. The method further includes: disposing the at least one step region in the middle of the corresponding memory array region to divide the corresponding memory array region into at least two sub-memory array regions; or disposing the at least one step region on the side of the corresponding memory array region.

[0034] In one embodiment, the method further includes: forming at least one virtual channel hole at the initial step; and filling the virtual channel hole with a virtual channel dielectric layer, where the virtual channel hole penetrates at least the corresponding initial step.

[0035] Another aspect of the present application provides a storage system, which includes: a controller and the memory according to any one of the aspects of the present application. The controller is coupled to the memory and is configured to control the memory to store data.

[0036] In one embodiment, the memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0037] A three-dimensional memory, a manufacturing method, and a storage system provided according to at least one embodiment of the present application. The gate layer of the three-dimensional memory includes a gate dielectric layer and a gate conductor layer that are adjacent to each other in the same layer. By providing a connection structure on a partial surface of the gate dielectric layer corresponding to a stepped terrace, the connection structure can be connected to a portion of the gate conductor layer located in the stepped area. Thus, each word line contact can extend at least to the connection conduction layer of the connection structure along the stacking direction, and is electrically connected to the corresponding gate conductor layer through the connection structure, thereby preventing word line bridging between different gate layers (i.e., short circuit occurs between different gate layers), and improving the reliability of the three-dimensional memory.

[0038] In addition, according to at least one embodiment of the present application, only a part of the gate sacrificial layer in the initial stacked structure is removed, and the removed part is used to form the gate conductor layer. Thus, problems such as stress deformation and wafer warping caused by processes such as etching, filling, and heat treatment required for forming the gate layer (which can be understood as forming the gate conductor layer) can be reduced, and the overall performance of the three-dimensional memory is improved.

[0039] Furthermore, a three-dimensional memory, a manufacturing method thereof, and a storage system provided according to at least one embodiment of the present application can be provided with at least one virtual channel structure on the stepped terrace in the stepped area of the three-dimensional memory, and the virtual channel structure can penetrate at least its corresponding stepped terrace. On the one hand, in the case where the virtual channel structure includes a semiconductor material layer, since the stepped area only includes a gate dielectric layer and an insulating layer, there is no need to consider over-etching caused by forming a virtual channel hole, which may lead to word line bridging between gate layers through the semiconductor material layer formed in the virtual channel hole. On the other hand, considering that only a part of the gate sacrificial layer in the initial stacked structure is removed, only a smaller number of virtual channel structures are required to provide structural support for the operation of removing the gate sacrificial layer. Further, for the above reasons, the virtual channel structure provided according to at least one embodiment of the present application can also appropriately change its position and number set in the stepped area to be more suitable for different architectures of the three-dimensional memory.

[0040] In addition, according to at least one embodiment of the present application, the number of gate line gap structures located in the stepped area of the three-dimensional memory, and the ratio between the thickness of the connection structure and the thickness of the gate dielectric layer can be adjusted, so as to adjust the resistance of the connection structure, where the thickness of the connection structure can be understood as the size of the part of the connection structure covering the top surface of the gate dielectric layer along the stacking direction of the stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Other features, objects, and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings:

[0042] Figure 1is a top view of a three-dimensional memory according to an embodiment of the present application;

[0043] Figure 2A is a partial schematic cross-sectional view taken along line A-A' in Figure 1 ;

[0044] Figure 2B is a top view of a gate layer according to an embodiment of the present application;

[0045] Figure 3A is a partial schematic cross-sectional view taken along line B-B' in Figure 1 ;

[0046] Figure 3B is Figure 3A an enlarged schematic view at E in

[0047] Figure 4 is a top view of a three-dimensional memory according to another embodiment of the present application;

[0048] Figure 5 is a partial schematic cross-sectional view taken along line C-C' in Figure 4 ;

[0049] Figure 6 is a partial schematic cross-sectional view taken along line D-D' in Figure 4 ;

[0050] Figure 7 is a partial cross-sectional schematic view of a three-dimensional memory according to an embodiment of the present application;

[0051] Figure 8 is a partial cross-sectional schematic view of a three-dimensional memory according to another embodiment of the present application;

[0052] Figure 9 is a partial cross-sectional schematic view of a three-dimensional memory according to yet another embodiment of the present application;

[0053] Figure 10 is a top view schematic of a stacked structure according to an embodiment of the present application;

[0054] Figure 11 is a top view schematic of a stacked structure according to another embodiment of the present application;

[0055] Figure 12 is a flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present application;

[0056] Figures 13A to 35B are respectively process schematic diagrams of a method for manufacturing a three-dimensional memory according to an embodiment of the present application; and

[0057] Figure 36 It is a schematic structural diagram of a storage system according to an embodiment of the present application.

[0058] Specific manner

[0059] The present application will be described in detail below with reference to the accompanying drawings. The exemplary embodiments mentioned herein are only used to explain the present application and are not used to limit the scope of the present application. Throughout the specification, the same reference numerals refer to the same elements.

[0060] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used to indicate approximation, not degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0061] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprises", "comprising", "has", "having", and / or "having a" are open-ended rather than closed-ended expressions in this specification, which mean the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or their combinations. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than just an individual element in the list. When describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0062] In addition, in the present application, when using expressions such as "connected", "covered", and / or "formed on...", it may mean direct contact or indirect contact between the corresponding components, unless there are clear other limitations or can be deduced from the context.

[0063] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this application belongs. In addition, unless clearly stated in the present application, words defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0064] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. In addition, unless explicitly defined or contradictory to the context, the specific steps in the methods described in the present application do not have to be limited to the recorded order, but can be executed in any order or executed in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0065] Figure 1 is a top view of a three-dimensional memory 1000 according to an embodiment of the present application. Figure 2A is along Figure 1 a partial schematic cross-sectional view taken along line A-A' in Figure 2B is a top view of a gate layer 230 according to an embodiment of the present application. Figure 3A is along Figure 1 a partial schematic cross-sectional view taken along line B-B' in Figure 3B is Figure 3A an enlarged schematic view of E in Figure 4 is a top view of a three-dimensional memory 1000 according to another embodiment of the present application. Figure 5 is along Figure 4 a partial schematic cross-sectional view taken along line C-C' in Figure 6 is along Figure 4 a partial schematic cross-sectional view taken along line D-D' in

[0066] As Figures 1 to 6 shown, the three-dimensional memory 1000 may include: a stacked structure 200, a connection structure 500, and a word line contact 700. Specifically, the stacked structure 200 may include a plurality of stepped levels 201, each stepped level 201 including an insulating layer 210 and a gate layer 230 located on the insulating layer 210, wherein the gate layer 230 includes a gate dielectric layer 231 and a gate conductor layer 232 that are adjacent to each other and distributed in a plane perpendicular to the first direction (z direction). The stacked structure 200 is generally formed by alternately stacking the insulating layer 210 and the gate layer 230 along the stacking direction. Therefore, the first direction can be understood as the stacking direction of the stacked structure 200. The connection structure 500 covers a partial surface of the gate dielectric layer 231 of the corresponding stepped level 201 and is connected to a portion of the gate conductor layer 232 located outside the gate dielectric layer 231 in the second direction (y direction), and the second direction is perpendicular to the first direction. The word line contact 700 extends at least along the first direction to the connection conduction layer 502 of the connection structure 500, and the word line contact 700 is electrically connected to the corresponding gate conductor layer 232 through the connection structure 500.

[0067] 3D memories generally include a stacked structure formed by alternatingly stacking gate layers and insulating layers, where word line contacts located in the step regions of the stacked structure can achieve electrical connection between the gates and external circuits. As the integration density of 3D memories increases and the number of stacked layers increases, the maximum depth of the contact holes of the word line contacts becomes increasingly deeper. Therefore, during the process of forming the contact holes for filling the word line contacts, it is extremely easy to cause the corresponding gate layer to be penetrated. In addition, after filling the over-etched contact holes with a conductive material for forming the word line contacts, it will cause bridging between different gate layers, thereby triggering the failure of the 3D memory.

[0068] To achieve effective electrical connection between the word line contacts and the gate layers, a thickened portion protruding along the direction perpendicular to the substrate can usually be provided at the ends of the gate layers, so that during the connection process between the ends of the gate layers and the word line contacts, penetration will not occur due to the too thin thickness of the gate layers. However, the conductive thickened portion is usually formed in the same step as the gate layer. Since the thickened portion is too thick compared to the thickness of the gate layer, it is very difficult to be fully filled in this step, thereby causing the word line contacts to be unable to achieve effective electrical connection with the gate layers through the thickened portion. In addition, the too large thickened portion also affects the process window of the virtual channel structure formed in the same step region.

[0069] According to the 3D memory provided by at least one embodiment of the present application, the gate layer of the 3D memory may include a gate dielectric layer and a gate conductor layer that are adjacent to each other in the same layer. By providing a connection structure on a partial surface of the gate dielectric layer corresponding to the stepped terrace, the connection structure can be connected to a portion of the gate conductor layer located in the step region. Therefore, each word line contact can extend at least to the connection conduction layer of the connection structure along the stacking direction and achieve electrical connection with the corresponding gate conductor layer through the connection structure, which can prevent word line bridging between different gate layers and improve the reliability of the 3D memory.

[0070] Example 1

[0071] Specifically, as Figure 1 、 Figure 2A and Figure 3A shown, in one embodiment of the present application, the 3D memory may have a storage array region GB (Giant Block) and a step region SS (Staircase Structure) along the third direction (x direction), where the step region SS can be used to form a plurality of stepped terraces 201, and the storage array region GB can be used to form a storage array composed of a plurality of channel structures 300 arranged and distributed, where the storage array is as Figure 1 shown by the elliptical portion outlined by the dashed line in

[0072] As Figure 2A and 2BAs shown, in this embodiment, the stacked structure 200 may include a plurality of stacked layers (not shown) formed by an insulating layer 210 and a gate layer 230 stacked in the z direction. Each stacked layer may include an insulating layer 210 and a gate layer 230. As an option, a plurality of stepped steps 201 may be formed at the ends of the plurality of stacked layers (which can be understood as the part of the stacked layer located in the stepped area SS). In each stepped step 201, the gate layer 230 is located on the insulating layer 210 to facilitate electrical connection with the connection structure 500. The gate layer 230 includes a gate dielectric layer 231 and a gate conductor layer 232 that are adjacent to each other in a plane perpendicular to the z direction.

[0073] As an option, the gate conductor layer 232 may be located in the stepped area SS and the storage array area GB, and the gate dielectric layer 231 may be located in the stepped area SS. In other words, the gate conductor layer 232 may include a first portion 232-1 located in the stepped area SS ( Figure 2B the part circled by the white elliptical dotted line in the figure) and a second portion 232-2 located in the storage array area GB. The gate conductor layer 232 and the gate dielectric layer 231 are adjacent to each other in a plane perpendicular to the z direction. For example, in a plane perpendicular to the z direction, the first portion 232-1 is located outside the gate dielectric layer 231 in the y direction and is adjacent to it.

[0074] The gate conductor layer 232 may include a conductive material layer, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. The insulating layer 210 and the gate dielectric layer 231 may respectively include, for example, a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials for forming the insulating layer 210 and the gate dielectric layer 231 may include silicon oxide and silicon nitride respectively, and the insulating layer 210 may be used as an isolation layer for the stacked layers. In addition, the number of layers of the stacked structure 200 is not limited to the number of layers shown in the figure and can be set otherwise as needed, such as 32 layers, 64 layers, 128 layers, etc.

[0075] In addition, the gate conductor layer 232 further includes a wall dielectric layer (not shown) located between the insulating layer 210 and the above-mentioned conductive material layer. As an option, the wall dielectric layer may be a high-k dielectric layer. Further, the gate conductor layer 232 may also include an adhesion layer (for example, a titanium nitride TiN layer, not shown) located between the insulating layer 210 and the above-mentioned conductive material layer, or between the wall dielectric layer and the above-mentioned conductive material layer.

[0076] As Figure 2A shown, in an embodiment of the present application, the stacked structure 200 may further include an isolation layer 202 for isolating the stacked structure 200 from a substrate (not shown). The isolation layer 202 may include, but is not limited to, an insulating dielectric material layer such as a silicon oxide layer.

[0077] With the continuous increase in the demand for the storage capacity of three-dimensional memories, the above-mentioned storage stack layers are gradually increasing. The stack structure 200 may include a plurality of sub-stack structures formed by using, for example, double-stack technology or multi-stack technology. The plurality of sub-stack structures may be sequentially stacked in a direction perpendicular to their thickness direction to form the stack structure 200, where each sub-stack structure may include a plurality of insulating layers and gate layers alternately stacked. The number of layers of each sub-stack structure may be the same or different. The content described below for a single stack structure may be fully or partially applicable to the stack structure formed by a plurality of sub-stack structures, so the related or similar content will not be repeated.

[0078] In addition, as Figure 2A and 2B shown, the stack structure 200 may further include a channel structure 300 penetrating therethrough. The channel structure 300 may include a channel hole (not shown) filled with a semiconductor layer and a composite dielectric layer, such as a functional layer 320 and a channel layer 330 sequentially formed on the inner wall of the channel hole.

[0079] The functional layer 320 may include a blocking layer (not shown), a charge trapping layer (not shown), and a tunneling layer (not shown) sequentially provided on the inner wall of the channel hole. As an option, the channel hole may have a cylindrical or columnar shape penetrating the stack structure 200 in the z direction. The channel layer 330 may include silicon, such as amorphous silicon, polycrystalline silicon, or single-crystalline silicon. The material of the channel layer 330 includes but is not limited to N-type doped polycrystalline silicon. Similar to the channel hole, the functional layer 320 and the channel layer 330 may also have a cylindrical or columnar shape penetrating the stack structure 200.

[0080] The channel structure 300 and the plurality of gate layers 230 may form a stack of storage units in the three-dimensional memory 1000 in a series configuration manner. Specifically, in the present embodiment, the gate layer 230 may include two parts along the x direction, a gate conductor layer 232 and a gate dielectric layer 231 adjacent to each other and distributed in a plane perpendicular to the z direction. As an option, a part of the gate conductor layer 232, for example, the first part 232-1, is located outside the gate dielectric layer 231 and adjacent to it in the y direction. Another part of the gate conductor layer 232, for example, the second part 232-2, extends in the x direction and is located between the gate dielectric layer 231 and the channel structure 300, and between adjacent channel structures 300, and is connected to the channel structure 300.

[0081] Alternatively, the gate dielectric layer 231 can be a reserved partial gate sacrificial layer (not shown). Generally, in the method of fabricating a 3D memory, the gate layer (which can be understood as the gate conductor layer) can be formed by removing the gate sacrificial layer in the initial stacked structure (which can be understood to include the stacked layer formed by alternately stacking an insulating layer and a gate sacrificial layer). In an embodiment of the present application, only a part of the gate sacrificial layer in the initial stacked structure is removed, and the void formed by the removed part of the gate sacrificial layer can be used to form the gate conductor layer, and the reserved part of the gate sacrificial layer is used to form the gate dielectric layer. Thus, problems such as stress deformation and wafer warpage caused by processes such as etching, filling, and heat treatment required for forming the gate layer can be reduced, and the overall performance of the 3D memory can be improved.

[0082] In addition, the connection structure 500 can include an insulating encapsulation layer 501, a connection conduction layer 502, and a connection structure filling layer 505. The insulating encapsulation layer 501 can include an insulating dielectric layer of any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The connection conduction layer 502 can include a conductive material layer, for example, formed by any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. Optionally, the connection conduction layer 502 can include a tungsten layer. The connection structure filling layer 503 can be a filling dielectric material layer.

[0083] In addition, the connection structure 500 can further include an inter-wall dielectric layer 503 and an adhesion layer 504. The inter-wall dielectric layer 503 and the adhesion layer 504 can be sequentially located between the insulating encapsulation layer 501 and the connection conduction layer 502. As an option, the inter-wall dielectric layer 503 can be a high-k dielectric layer; and the adhesion layer 504 can be, for example, a titanium nitride TiN layer.

[0084] As an option, the inter-wall dielectric layer 503, the adhesion layer 504, and the connection conduction layer 502 of the connection conduction layer 502 can be formed simultaneously with the inter-wall dielectric layer, the adhesion layer, and the conductive material layer of the gate conductor layer 232, respectively, and the same materials can be selected for preparation. Thus, by simultaneously forming the connection conduction layer 502 and the gate conductor layer 232, the process steps for fabricating the 3D memory can be reduced, and the process cost for fabricating the 3D memory can be lowered.

[0085] In an embodiment of the present application, the 3D memory 1000 further includes a gate line gap structure 400.

[0086] Combined Figure 1 and Figure 2A, the gate line gap structure 400 can extend along the x direction and penetrate the stacked structure 200 along the z direction. In addition, multiple gate line gap structures 400 are spaced apart in the y direction. The gate line gap structure 400 can include a gate line gap 410 and a gap filling layer 420 filled in the gate line gap 410. The memory 1000 can be divided into multiple memory blocks 301 by the gate line gap structure 400.

[0087] Figure 3B Yes Figure 3A Partial schematic cross-sectional view at E in

[0088] Combined with Figure 1 、 Figure 2A And Figure 3B As shown, the gate dielectric layer 231 between two adjacent gate line gap structures 400 can include a top surface 231-1 and two side surfaces 231-2 and 231-3 opposite in the y direction, where the side surfaces 231-2 and 231-3 are both adjacent to the top surface 231-1.

[0089] The connection structure 500, or more specifically, at least the connection conduction layer 502 of the connection structure 500, can cover a partial surface of the gate dielectric layer 231 corresponding to the stepped step 201, and this partial surface is the top surface 231-1 and the two side surfaces 231-2 and 231-3. The connection structure 500 covering the top surface 231-1 and the two side surfaces 231-2 and 231-3 is connected to the first part 232-1 of the gate conductor layer 232 in the y direction.

[0090] In addition, referring to Figure 2A 、 Figure 3A And Figure 3B , the gate line gap 410 can be a process window for forming the gate conductor layer 232 and the connection structure 500. Specifically, the gate line gap 410 can serve as a passage (process window) for providing etchant and chemical precursors, and by using processes such as wet etching to remove the gate sacrificial layer (not shown) and the connection sacrificial layer (not shown) in the initial stacked structure (not shown), a gate sacrificial void (not shown) for accommodating the gate conductor layer 232 and a connection sacrificial void (not shown) for accommodating the connection structure 500 are formed. In addition, through the gate line gap 410, the gate sacrificial void and the connection sacrificial void can be filled to form the gate conductor layer 232 and the connection structure 500.

[0091] Therefore, based on the process window for forming the gate conductor layer 232 and the connection structure 500 being the gate line gap 410, by reasonably designing the ratio between the extension dimension D2 of the gate line gap 410 in the y direction and the length D1 of the first part 232-1 of the gate conductor layer 232 in the y direction, the above process requirements can be met, the above process window can be optimized, and a gate conductor layer 232 with good filling performance can be obtained. As an option, the extension length D1 of the first part 232-1 of the gate conductor layer 232 in the y direction and the width D2 of the gate line gap 410 in the y direction can satisfy: 20nm ≤ D1 ≤ D2 / 2.

[0092] In addition, in an embodiment of the present application, since only a part of the gate sacrificial layer in the initial stacked structure is removed, the number of the above gate line gaps in, for example, the step region SS can be adjusted, and the ratio between the thickness H1 of the part of the connection conduction layer 502 covering the top surface 231-1 in the z direction and the thickness H2 of the gate dielectric layer 231 in the z direction can be adjusted, so as to adjust the resistance of the connection structure 500. For example, the thickness H1 of the part of the connection conduction layer 502 covering the top surface 231-1 in the z direction and the thickness H2 of the gate dielectric layer 231 in the z direction can satisfy: H1 ≥ 1.1×H2.

[0093] Figure 7 is a partial cross-sectional schematic diagram of a three-dimensional memory 1000 according to an embodiment of the present application. Figure 8 is a partial cross-sectional schematic diagram of a three-dimensional memory 1000 according to another embodiment of the present application. Figure 9 is a partial cross-sectional schematic diagram of a three-dimensional memory 1000 according to yet another embodiment of the present application.

[0094] As shown in Figures 7 to 9 the three-dimensional memory 1000 provided by at least one embodiment of the present application further includes a substrate 100, and the stacked structure 200 can be located on the substrate 100. However, those skilled in the art should understand that without departing from the teachings of the present application, the substrate 100 may include different layer structures according to different three-dimensional memory architectures, and the present application does not limit this. For example, the substrate 100 may include a local structure connected to the channel layer 330, and this local structure is used to form a circuit loop for conducting the operation of the memory cell.

[0095] As an option, in an embodiment of the present application, in combination with Figure 2A and Figure 7 , the stacked structure 200 can be located on the substrate 100, and the substrate 100 includes a first semiconductor layer 110. The channel layer 330 can penetrate the stacked structure 200 along the z direction and extend to the first semiconductor layer 110, where the first semiconductor layer 110 is at least connected to the bottom surface part of the channel layer 330.

[0096] For example, the channel layer 330 may penetrate the stacked structure 200 along the z direction and extend into the first semiconductor layer 110, wherein the first semiconductor layer 110 may be connected to the bottom portion of the channel layer 330 and to a portion of the side portion of the channel layer 330, wherein the portion of the side portion is the portion of the side portion of the channel layer 330 connected to the bottom portion.

[0097] The first semiconductor layer 110 may be a highly doped semiconductor layer. For example, the first semiconductor layer 110 may be doped with any suitable N-type dopant (eg, phosphorus (P), arsenic (Ar) or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor.

[0098] In addition, in one embodiment of the present application, in order to achieve a good and stable electrical connection between the channel layer 330 and the first semiconductor layer 110 and improve the electrical performance of the three-dimensional memory, the exposed channel layer 330 may be highly doped before the step of forming the first semiconductor layer 110. The specific steps will be described below.

[0099] like Figure 7 As shown, the channel layer may include at least two regions with different doping concentrations along the first direction. For example, the channel layer 330 may include a first region 333 and a second region 334, wherein the first region 333 includes a portion of the channel layer 330 extending into the first semiconductor layer 110 and adjacent to the first semiconductor layer 110, and the second region 334 is located on the side of the first region 333 away from the first semiconductor layer 110. Compared with the two, the doping concentration of the conductive impurities in the first region 333 is greater than the doping concentration of the conductive impurities in the second region 334. The above arrangement can increase the doping concentration of the conductive impurities in the portion of the channel layer that is closer to the first semiconductor layer, achieve a good and stable electrical connection between the channel layer and the first semiconductor layer, and improve the electrical performance of the three-dimensional memory.

[0100] In addition, the first semiconductor layer 110 further includes a common source lead-out point 111 , which may be, for example, directly opposite to the channel structure, and this application does not limit this.

[0101] As another option, combine Figure 2A and Figure 8 In one embodiment of the present application, the stacked structure 200 may be located on the substrate 100, and the substrate 100 includes a second semiconductor layer 130. The channel layer 330 may penetrate the stacked structure 200 along the z direction and extend through the second semiconductor layer 130, wherein the second semiconductor layer 130 may be connected to a side portion of the channel layer 330.

[0102] The second semiconductor layer 130 may be a highly doped semiconductor layer. For example, the second semiconductor layer 130 may be doped with any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor.

[0103] As yet another alternative, in combination Figure 2A and Figure 9 , in one embodiment of the present application, the three-dimensional memory may also include a substrate 100, a stacked structure 200 may be located on the substrate 100, and the channel structure 300 may include a channel hole 310, a functional layer 320, an epitaxial layer 120, and a channel layer 330. The channel hole 310 penetrates the stacked structure 200' in a first direction; the epitaxial layer 120 is located at the bottom of the channel hole 310; the functional layer 320 is located on the inner wall of the channel hole 310 and the epitaxial layer 120; and the channel layer 330 is located on the surface of the functional layer 320 and is connected to the epitaxial layer 120 through the functional layer 320. The epitaxial layer 120 may be at least one of epitaxial silicon, silicon germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials.

[0104] Figure 10 is a top view schematic diagram of the stacked structure 200 according to one embodiment of the present application. Figure 11 is a top view schematic diagram of the stacked structure 200 according to another embodiment of the present application.

[0105] As Figure 10 and Figure 11 shown, according to some embodiments, the stacked structure 200 may have a plurality of stepped areas 01 and a plurality of memory array areas 02, each memory array area 02 corresponding to at least one stepped area 01, wherein the stepped area 01 may be used to form a plurality of stepped steps, the memory array area 02 may be used to form a memory array composed of a plurality of channel structures arranged and distributed, and in addition, the gate layers in the memory array may be connected and conducted one by one through the word line contacts formed on each stepped step.

[0106] As Figure 10 shown, according to some embodiments, at least one stepped area 01 may be provided at one side edge or multiple side edges of the stacked structure 200. As Figure 11 shown, according to some embodiments, at least one stepped area 01 may be provided in the middle of the stacked structure 200 and divide the memory array area 02 into at least two sub-memory array areas. The present application does not limit the relative positions and specific structures of the stepped area 01 and the memory array area 02. In addition, the stacked structure 200 may further include a peripheral circuit area for forming peripheral circuits.

[0107] Therefore, the three-dimensional memory provided by at least one embodiment of the present application has good scalability and compatibility. It can be adapted to different three-dimensional memory architectures and is not limited by the number of stacked layers in the stacked structure. In addition, the above descriptions of the local structure of the substrate, the step region, and the distribution of the memory array region are only for the embodiments of the present application and the explanation of the applied technical principles. Those skilled in the art should understand that the technical solutions of the present application regarding the local structure of the substrate, the step region, and the distribution of the memory array region are not limited to the technical solutions formed by the selected combination of the above technical features.

[0108] For the three-dimensional memory provided by at least one embodiment of the present application, the gate layer of the three-dimensional memory includes a gate dielectric layer and a gate conductor layer that are adjacent to each other in the same layer. By providing a connection structure on a partial surface of the gate dielectric layer corresponding to the stepped terrace, the connection structure can be connected to the part of the gate conductor layer located in the step region. Therefore, each word line contact can extend at least to the connection conduction layer of the connection structure along the stacking direction of the stacked structure, and is electrically connected to the corresponding gate conductor layer through the connection structure, thereby preventing word line bridging between different gate layers and improving the reliability of the three-dimensional memory.

[0109] In addition, according to at least one embodiment of the present application, only a part of the gate sacrificial layer in the initial stacked structure is removed, and the removed part is used to form the gate conductor layer. Therefore, problems such as stress deformation and wafer warping caused by processes such as etching, filling, and heat treatment required for forming the gate layer (which can be understood as forming the gate conductor layer) can be reduced, and the overall performance of the three-dimensional memory is improved.

[0110] In addition, according to at least one embodiment of the present application, the number of gate line gap structures located in the step region in the three-dimensional memory, and the ratio between the thickness of the connection structure and the thickness of the gate dielectric layer can be adjusted, so as to adjust the resistance of the connection structure, where the thickness of the connection structure can be understood as the dimension of the part of the connection structure covering the top surface of the gate dielectric layer along the stacking direction of the stacked structure.

[0111] Example 2

[0112] Next, the specific structure of the three-dimensional memory 1000 in another embodiment of the present application will be described in detail in conjunction with Figures 4 to 6 The specific structure of the three-dimensional memory 1000 in another embodiment of the present application will be described in detail.

[0113] Since the content and structure of the three-dimensional memory 1000 described above can be fully or partially applied to the three-dimensional memory described here, the related or similar content will not be repeated. In the following, the virtual channel structure 600 included in the three-dimensional memory 1000 in another embodiment of the present application will be described in detail.

[0114] As an option, as Figures 4 to 6As shown, the three-dimensional memory 1000 further includes a virtual channel structure 600. Specifically, a plurality of virtual channel structures 600 are usually provided in the step region SS of the three-dimensional memory 1000. The virtual channel structure 600 can provide strong structural support for the stacked structure 200 during the manufacturing process of forming the three-dimensional memory 1000, for example, at the stage of removing the gate sacrificial layer (not shown) to form the gate conductor layer 232, preventing the stacked structure 200 from collapsing or breaking.

[0115] In some embodiments of the present application, at least one virtual channel structure 600 can be provided on the stepped step 201 of the step region SS. In addition, the virtual channel structure 600 can penetrate at least along the z direction through the stepped step 201. The virtual channel structure 600 includes a virtual channel hole 610 and a virtual channel filling material layer 620. The virtual channel filling material layer 620 can include an insulating dielectric layer of any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, or can also include a semiconductor material layer such as polysilicon. The present application does not limit the material for preparing the virtual channel filling dielectric material layer.

[0116] Generally, in the method of manufacturing the virtual channel structure 600, the virtual channel hole 610 can be formed by processes such as etching. However, with the increase in the integration degree of the three-dimensional memory 1000 and the increase in the number of stacked layers, the maximum depth of the virtual channel hole 610 is increasingly deepened. Therefore, it is very easy to cause the gate layer 230 to be penetrated during the formation of the virtual channel hole 610.

[0117] In the three-dimensional memory provided in at least one embodiment of the present application, at least one virtual channel structure 600 can be provided on the stepped step 201 of the step region SS of the three-dimensional memory 1000. In addition, the virtual channel structure 600 can penetrate at least through its corresponding stepped step 201. On the one hand, in the case where the virtual channel structure includes a semiconductor material layer, since the step region only includes a gate dielectric layer and an insulating layer, there is no need to consider the word line bridging caused by the semiconductor material layer formed in the virtual channel hole due to over-etching during the formation of the virtual channel hole. On the other hand, considering that only a part of the gate sacrificial layer in the initial stacked structure is removed, only a small number of virtual channel structures are required to provide structural support for the operation of removing the gate sacrificial layer. Further, for the above reasons, the virtual channel structure provided in at least one embodiment of the present application can also appropriately change its position and number provided in the step region to be more suitable for different architectures of the three-dimensional memory.

[0118] Figure 12 It is a flowchart of a manufacturing method 2000 of a three-dimensional memory according to an embodiment of the present application. Figures 13A to 35B They are process schematic diagrams of a manufacturing method of a three-dimensional memory according to an embodiment of the present application.

[0119] As Figure 12 shown, the manufacturing method 2000 of the three-dimensional memory may include:

[0120] S1, alternately stacking an insulating layer and a gate sacrificial layer to form an initial stacked structure.

[0121] S2, forming a plurality of initial stepped steps in the stepped area of the initial stacked structure, and exposing a part of the upper surface of the gate sacrificial layer in each initial stepped step.

[0122] S3, forming a connection sacrificial structure on the exposed upper surface of the gate sacrificial layer, and the connection sacrificial structure includes a connection sacrificial layer.

[0123] S4, forming a gate line gap penetrating the initial stacked structure, and via the first gate line gap, removing a part of the first gate sacrificial layer adjacent to the first gate line gap to form a first groove, and removing the connection sacrificial layer to form a connection sacrificial void, wherein the first gate line gap is the part of the gate line gap located in the stepped area, and the first gate sacrificial layer is the part of the gate sacrificial layer located in the stepped area.

[0124] S5, filling the connection sacrificial void and the first groove with a conductive material to form a connection structure and a first part of the gate conductor layer located in the stepped area, and the first part is connected to the connection structure.

[0125] The following will combine with Figures 13A to 35B to detail the specific processes of each step of the above manufacturing method 2000 in an embodiment of the present application.

[0126] Step S1

[0127] Figure 13A is a partial cross-sectional schematic view taken along line A-A' in Figure 1 of the structure formed after forming the initial stepped step 201' according to an embodiment of the present application. Figure 13B is a partial cross-sectional schematic view taken along line B-B' in Figure 1 of the structure formed after forming the initial stepped step 201' according to an embodiment of the present application.

[0128] As Figure 13A and 13B shown, step S1 of alternately stacking an insulating layer and a gate sacrificial layer to form an initial stacked structure may for example include: providing an initial substrate (not shown); alternately stacking an insulating layer 210 and a gate sacrificial layer 220 to form an initial stacked structure 200'; and forming a channel structure 300 in the initial stacked structure 200'.

[0129] Specifically, in an embodiment of the present application, the material for preparing the initial substrate can be any suitable semiconductor material, such as single-crystalline silicon (Si), single-crystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), or group III-V compounds such as gallium arsenide. Further, the initial substrate can be single-crystalline silicon.

[0130] In an embodiment of the present application, the initial substrate can be, for example, a composite substrate for supporting the device structure thereon. Multiple layers made of different materials can be sequentially provided by a thin-film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the initial substrate.

[0131] The initial substrate can include a substrate sacrificial layer for subsequent formation of a semiconductor connection layer (e.g., forming a second semiconductor layer in subsequent steps). The substrate sacrificial layer can include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer can include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. As an option, the substrate sacrificial layer can be a high-k dielectric layer. As another option, the substrate sacrificial layer can include a dielectric layer, a sacrificial layer, and a dielectric layer arranged in sequence, where the dielectric layer can be a silicon nitride layer and the sacrificial layer can be a silicon oxide layer. As another option, the substrate sacrificial layer can include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer can be single-crystalline silicon or polycrystalline silicon. Specifically, in an embodiment of the present application, an exemplary material for forming the sacrificial layer can be polycrystalline silicon.

[0132] In some regions of the initial substrate, well regions can also be formed by doping with an N-type or P-type dopant through an ion implantation or diffusion process. The dopant can include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the well regions can be prepared with the same dopant or different dopants. Further, the doping concentrations of the well regions can be the same or different, and the present application does not limit this.

[0133] After forming the initial substrate, an initial stacked structure 200' can be formed on the initial substrate through one or more thin-film deposition processes. The thin-film deposition process can include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin-film deposition processes or any combination thereof, and the present application does not limit this.

[0134] The initial stacked structure 200' can include multiple pairs of insulating layers 210 and gate sacrificial layers 220 stacked alternately with each other. For example, the initial stacked structure 200 can include 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 210 and gate sacrificial layers 220.

[0135] In other words, the initial stack structure 200 may include a plurality of initial stacked layers (not shown) formed by stacking a gate insulating layer 210 and a gate sacrificial layer 220 along a first direction (z direction). In some embodiments, the insulating layer 210 and the gate sacrificial layer 220 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the insulating layer 210 and the gate sacrificial layer 220 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stacked layer, while the silicon nitride layer may be used as a sacrificial stacked layer. Subsequently, the sacrificial stacked layer may be etched away and replaced with a conductor layer including a conductive material to form a gate layer of the three-dimensional memory.

[0136] In addition, before forming the insulating layer 210 and the gate sacrificial layer 220, an isolation layer 202 may be formed on the initial substrate by one or more thin film deposition processes, which may include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin film deposition processes or any combination thereof, and this application does not limit this. The isolation layer 202 may include but is not limited to an insulating dielectric material layer such as a silicon oxide layer.

[0137] The preparation method of a single initial stack structure has been described above. In fact, as the storage capacity requirement of the three-dimensional memory continues to increase, the storage stack gradually increases. To break through the limitations of process limits, a dual-stack technology or a multi-stack technology may also be used to form an initial stack structure by sequentially stacking a plurality of sub-stack structures in the stacking direction of the stack structure, where each sub-stack structure may include a plurality of insulating layers and gate sacrificial layers alternately stacked. The number of layers of each sub-stack structure may be the same or different. Since the content and structure involved in the preparation process of the single initial stack structure described above can be fully or partially applied to the technical effects of the initial stack structure including a plurality of sub-stack structures described here, the related or similar content will not be repeated. However, those skilled in the art can understand that subsequent preparation processes can be carried out on the basis of a multi-stack structure or a single-stack structure.

[0138] The channel structure 300 may include a channel hole 310 filled with a semiconductor layer and a composite dielectric layer. Through thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, a functional layer 320 and a channel layer 330 may be sequentially formed on the inner wall of the channel hole 310.

[0139] Specifically, after forming the initial stack structure 200’, the channel holes 310 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc. The channel holes 310 can have a cylindrical or columnar shape that penetrates the initial stack structure 200’. As an option, the channel holes 310 can extend into the initial substrate.

[0140] The functional layer 320 can include a blocking layer formed on the inner wall of the channel hole 310 to block the outflow of charges, a charge trapping layer formed on the surface of the blocking layer to store charges during the operation of the 3D memory, and a tunneling layer formed on the surface of the charge trapping layer.

[0141] In some embodiments, the functional layer 320 can include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 320 can have a structure different from the ONO configuration. For example, the functional layer 320 can include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer. The channel layer 330 can be used to transport the required charges (electrons or holes).

[0142] However, those skilled in the art should understand that without departing from the teachings of this application, depending on the different 3D memory architectures, the functional layer can be formed on the inner wall of the channel hole (which can be understood as the sidewall and bottom surface of the channel hole), or on the inner wall of the channel hole (which can be understood as the sidewall of the channel hole), and this application does not limit this.

[0143] For example, as an option, in combination with Figure 7 、 Figure 8 and Figure 13A , according to an embodiment of this application, the functional layer 320 can be formed on the sidewall and bottom surface of the channel hole 310, and the channel layer 330 can be formed on the surface of the tunneling layer of the functional layer 320 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0144] As another option, in combination with Figure 9 and Figure 13A , according to an embodiment of this application, the functional layer 320 can also be formed only on the sidewall of the channel hole 310, and the channel layer 330 can be formed on the surface of the tunneling layer of the functional layer 320 and, for example, on the surface of an epitaxial layer formed subsequently by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0145] Specifically, an epitaxial layer 120 can be first formed at the bottom of the channel hole 310 through an epitaxial growth process. The manufacturing processes for epitaxially growing the epitaxial layer 120 can include but are not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. The epitaxial layer 120 can be at least one of epitaxial silicon, silicon germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials. After forming the epitaxial layer 120, an initial functional layer (not shown) can be formed on the inner wall of the channel hole 310 and the surface of the epitaxial layer 120 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Then, through, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove the part of the initial functional layer located on the surface of the epitaxial layer 120 and expose a part of the surface of the epitaxial layer 120. It can be understood that the functional layer 320 is formed only on the sidewall of the channel hole 310. After forming the functional layer 320, a channel layer 330 connected to the epitaxial layer 120 can be formed on the surface of the tunneling layer of the functional layer 320 and the exposed surface of the epitaxial layer 120 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0146] In some embodiments, the channel layer 330 can include silicon, such as polysilicon or single crystal silicon. The material of the channel layer 330 can include but is not limited to N-type doped polysilicon. Similar to the channel hole 310, the channel layer 330 can also penetrate the stacked structure 200 and have a cylindrical or columnar shape. As an option, the channel layer 330 can also extend into the initial substrate.

[0147] In addition, the channel structure 300 further includes a channel plug (not shown) formed at one end of the channel hole 310 away from the initial substrate (which can be understood as the top end of the channel structure 300). Specifically, the channel hole 310 can be filled with a filling dielectric layer. The filling dielectric layer can include an oxide dielectric layer, such as silicon oxide, etc. Further, during the filling process, multiple insulating gaps can be formed in the filling dielectric layer by controlling the channel filling process to relieve the structural stress. Then, a channel plug is formed in the part of the filling dielectric layer located at the top of the channel hole 310. The material of the channel plug can be selected to be the same as the material of the channel layer 330, such as N-type doped polysilicon, etc. The channel plug is electrically connected to the channel layer 330.

[0148] Step S2

[0149] Refer again to Figure 13A and Figure 13B, in step S2, a plurality of initial stepped steps are formed in the stepped region of the initial stack structure. Exposing a part of the upper surface of the gate sacrificial layer in each initial stepped step may include, for example: removing the insulating layer 210 located on the top surface of the initial stack structure 200', so that in each subsequently formed initial stepped step 201', the gate sacrificial layer 220 is located above the insulating layer 210, thereby exposing a part of the upper surface (not shown) of the gate sacrificial layer 220 in each initial stepped step 201'; and forming a plurality of initial stepped steps 201' in the stepped region SS.

[0150] Specifically, in an embodiment of the present application, after forming the channel structure 300, the initial stack structure 200' may be divided into two regions along the third direction (x direction, which can also be understood as the extending direction of the subsequently formed stepped steps), namely the storage array region GB and the stepped region SS. The stepped region SS may include a plurality of initial stepped steps 201' formed by a plurality of stepped dielectric layer pairs (insulating layer 210 and gate sacrificial layer 220).

[0151] Among the plurality of initial stacked layers formed by stacking the initial stack structure 200 along the z direction, the gate insulating layer 210 is usually the outermost film layer located farthest from the initial substrate in the initial stack structure 200. The insulating layer 210 located on the outermost side may be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes may also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, so that in the subsequently formed initial stepped steps 201', the gate sacrificial layer 220 can be located on the upper surface of each initial stepped step 201', thereby exposing a part of the upper surface (not shown) of the gate sacrificial layer 220 in each initial stepped step 201'.

[0152] As an option, a plurality of "trim-etch" cycles may be performed on, for example, the edge portion of the initial stack structure 200' to make the initial stack structure 200' have one or more inclined edges and a top (away from the initial substrate) dielectric layer pair shorter than the bottom (close to the initial substrate) dielectric layer pair (which can be understood as an initial stepped step 201'). Any suitable etching process (including any one or combination of dry etching process and wet etching process) can be used in the stepped formation process.

[0153] As an option, in some embodiments of the present application, the channel hole 310 may be formed after forming a plurality of initial stepped steps 201'. As another option, in some other embodiments, the channel hole 310 may also be formed before forming a plurality of initial stepped steps 201', and the present application does not limit this.

[0154] Step S3

[0155] Figure 14A is a partial cross-sectional schematic view taken along line A-A' in the structure formed after forming a first covering layer 203 covering the initial stepped terrace 201' according to an embodiment of the present application. Figure 1 Figure 14B is a partial cross-sectional schematic view taken along line B-B' in the structure formed after forming a first covering layer 203 covering the initial stepped terrace 201' according to an embodiment of the present application. Figure 1 Figure 15A is a partial cross-sectional schematic view taken along line A-A' in the structure formed after forming a sidewall covering layer 204 according to an embodiment of the present application. Figure 1 Figure 15B is a partial cross-sectional schematic view taken along line B-B' in the structure formed after forming a sidewall covering layer 204 according to an embodiment of the present application. Figure 1 Figure 16A is a partial cross-sectional schematic view taken along line A-A' in the structure formed after forming an oxide cushion layer 205 according to an embodiment of the present application. Figure 1 Figure 16B is a partial cross-sectional schematic view taken along line B-B' in the structure formed after forming an oxide cushion layer 205 according to an embodiment of the present application. Figure 1 Figure 17A is a partial cross-sectional schematic view taken along line A-A' in the structure formed after forming a connection sacrificial layer 206 according to an embodiment of the present application. Figure 1 Figure 17B is a partial cross-sectional schematic view taken along line B-B' in the structure formed after forming a connection sacrificial layer 206 according to an embodiment of the present application. Figure 1 Figure 18A is a partial cross-sectional schematic view taken along line A-A' in the structure formed after forming an insulating encapsulation layer 501 according to an embodiment of the present application. Figure 1 Figure 18B is a partial cross-sectional schematic view taken along line B-B' in the structure formed after forming an insulating encapsulation layer 501 according to an embodiment of the present application. Figure 1

[0156] As Figures 14A to 18B shown, in step S3, a connection sacrificial structure is formed on the exposed upper surface of the gate sacrificial layer. The connection sacrificial structure may include, for example: forming a first covering layer 203 covering the initial stepped terrace 201'; forming a sidewall covering layer 204 on the sidewalls of each initial stepped terrace 201'; forming an oxide cushion layer 205; forming a connection sacrificial layer 206 of the connection sacrificial structure 500'; and forming an insulating encapsulation layer 501 of the connection sacrificial structure 500'.

[0157] Specifically, as Figure 14A and Figure 14B shown, a first covering layer 203 covering the sidewalls and top surface of the initial stepped step 201' can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first covering layer 203 can include, but is not limited to, an insulating dielectric material layer such as a silicon oxide layer.

[0158] As Figure 15A and Figure 15B shown, after forming the first covering layer 203 (as Figure 14A shown), a portion of the first covering layer 203 located on the top surface of each initial stepped step 201' can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., to form a sidewall covering layer 204 on the sidewalls of each initial stepped step 201'.

[0159] As Figure 16A and Figure 16B shown, after forming the sidewall covering layer 204, an oxide cushion layer 205 covering the sidewall covering layer 204 and the top surface of each initial stepped step 201' can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The oxide cushion layer 205 can include, but is not limited to, an insulating dielectric material layer such as a silicon oxide layer. Compared with the first covering layer 203, the thickness of the oxide cushion layer 205 is relatively thin and is used to isolate the subsequently formed connection sacrificial layer (not shown) from the gate sacrificial layer 220.

[0160] As Figure 17A and Figure 17B shown, after forming the oxide cushion layer 205, a connection sacrificial layer 206 can be formed on each initial stepped step 201' by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The connection sacrificial layer 206 can be used to form a connection conduction layer of a connection structure in a subsequent step. The connection sacrificial layer 206 can include, but is not limited to, an insulating dielectric material layer such as a silicon nitride layer, a silicon oxynitride layer, etc. Optionally, the connection sacrificial layer 206 is a TS silicon nitride layer.

[0161] In an embodiment of the present application, the thickness of the connection sacrificial layer 206 in the z direction is greater than or equal to 1.1 times the thickness of the gate sacrificial layer 220 in the z direction, so as to facilitate the stepwise removal of the connection sacrificial layer 206 and the gate sacrificial layer 220 in subsequent steps.

[0162] Both the connecting sacrificial layer 206 and the partial gate sacrificial layer 220 will be removed in subsequent steps to form the connecting conduction layer and the gate conductor layer of the connecting structure. The oxide cushion layer 205 and the insulating layer 210 can be made of the same material. Optionally, the thickness of the oxide cushion layer 205 in the z direction can be less than or equal to the thickness of the insulating layer 210 in the z direction.

[0163] In addition, as an option, the materials for preparing the oxide cushion layer 205 and the connecting sacrificial layer 206 can be different, so that in the subsequent step of removing the connecting sacrificial layer 206, the etching rate of the connecting sacrificial layer 206 can be greater than the etching rate of the oxide cushion layer 205. Therefore, the loss and damage of the oxide cushion layer 205 during the process of removing the connecting sacrificial layer 206 are less. When the oxide cushion layer 205 is exposed, the step of removing the connecting sacrificial layer 206 can be stopped. In other words, the oxide cushion layer 205 can be an etching stop layer for the subsequent step of removing the connecting sacrificial layer 206.

[0164] As Figure 18A and Figure 18B shown, after forming the connecting sacrificial layer 206, an insulating encapsulation layer 501 wrapping the connecting sacrificial layer 206 can be formed through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The insulating encapsulation layer 501 can include, but is not limited to, an insulating dielectric material layer such as a silicon oxide layer. The insulating encapsulation layer 501 can be the insulating encapsulation layer for the connecting structure (not shown) formed in subsequent steps.

[0165] In addition, a covering layer 207 covering the step region SS can also be formed. The covering layer 207 can include, but is not limited to, an insulating dielectric material layer such as a silicon oxide layer, a TEOS layer.

[0166] Step S4

[0167] Figure 19A is a partial cross-sectional schematic view taken along line A-A' of the structure formed after forming the initial sealing layer (initial polysilicon layer 208' and initial dielectric covering 209') according to an embodiment of the present application. Figure 1 in Figure 19B is a partial cross-sectional schematic view taken along line B-B' of the structure formed after forming the initial sealing layer (initial polysilicon layer 208' and initial dielectric covering 209') according to an embodiment of the present application. Figure 1 in Figure 20A is a partial cross-sectional schematic view taken along line A-A' of the structure formed after forming the second groove 511 and the first groove 221 according to an embodiment of the present application. Figure 1 in Figure 20BA partial cross-sectional schematic view taken along line B-B' in Figure 1 of the structure formed after forming the second groove 511 and the first groove 221 according to an embodiment of the present application. Figure 1

[0168] As Figures 18A to 20B shown, in step S4, a gate line gap is formed through the initial stacked structure, and a part of the first gate sacrificial layer adjacent to the first gate line gap is removed via the first gate line gap to form the first groove, and the connection sacrificial layer is removed to form a connection sacrificial void. The first gate line gap is the part of the gate line gap located in the step region, and the first gate sacrificial layer is the part of the gate sacrificial layer located in the step region. For example, it may include: forming an initial sealing layer (not shown), the initial sealing layer may include an initial polysilicon layer 208' and an initial dielectric covering 209'); forming a sealing layer (not shown), the sealing layer may include a polysilicon layer 208 and a dielectric covering 209; forming the second groove 511 and the first groove 221; and forming a connection sacrificial void 512 or enlarging the connection sacrificial void 512'.

[0169] Specifically, as Figure 18A and Figure 18B shown, in an embodiment of the present application, a part of the initial stacked structure 200' may be removed, for example, by a dry etching process or a combination of dry and wet etching processes; other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to form a gate line gap 410 that penetrates the initial stacked structure 200' in the z direction. The gate line gap 410 extends in the x direction through the step region SS and the memory array region GB and may be located between the channel structures 300 in the y direction.

[0170] As Figure 19A and Figure 19B shown, the gate line gap 410 may include a second gate line gap 411 located in the memory array region GB and a first gate line gap 412 located in the step region SS. The gate line gap 410 can serve as a path (process window) for providing etchant and chemical precursors. By using a process such as wet etching, etc., the connection sacrificial layer 206 and a part of the gate sacrificial layer 220 in the initial stacked structure 220' are removed, thereby forming a gate sacrificial void (not shown) for accommodating a gate conductor layer (not shown) and a connection sacrificial void (not shown) for accommodating a connection conduction layer (not shown). In addition, the gate sacrificial void and the connection sacrificial void can also be filled through the gate line gap 410 to form a gate conductor layer and a connection conduction layer (not shown). Therefore, the gate line gap 410 is a process window for forming the gate conductor layer. Similarly, the gate line gap 410 is also a process window for forming the connection structure.

[0171] ​One of the inventive points of the present application lies in using the second gate line gap located in the memory array region and the first gate line gap located in the step region of the gate line gap respectively, so that only part of the gate sacrificial layer in the initial stacked structure is removed, and part of the gate sacrificial void located in the step region and the connection sacrificial void are formed simultaneously. Therefore, by removing part of the gate sacrificial layer, problems such as stress deformation and wafer warping caused by processes such as etching, filling, and heat treatment required for forming the gate conductor layer can be reduced, and the overall performance of the 3D memory can be improved. In addition, due to the gate sacrificial layer retained in the step region, it is formed into the subsequent gate dielectric layer. Therefore, during the formation of the word line contact, word line bridging between different gate layers can be avoided, and the reliability of the 3D memory can be improved.

[0172] Furthermore, considering that only part of the gate sacrificial layer in the initial stacked structure is removed, only a smaller number of dummy channel structures need to be set to provide structural support for the operation of removing the gate sacrificial layer. In addition, since the step region only includes the retained gate sacrificial layer and the insulating layer, the position and number of the dummy channel structures provided on the stepped terrace can be appropriately changed to be more suitable for different architectures of the 3D memory. The formation of the dummy channel structure will be described in detail below.

[0173] Refer again to Figure 19A and Figure 19B , after forming the gate line gap 410, an initial sealing layer (not shown) can be formed through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The initial sealing layer can include an initial polysilicon layer 208' and an initial dielectric covering 209'. The initial sealing layer can cover the gate line gap 410 and the insulating encapsulation layer 501.

[0174] As Figure 20A and Figure 20B shown, after forming the initial sealing layer, part of the initial sealing layer can be removed through, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to form a sealing layer, and the sealing layer includes a polysilicon layer 208 and a dielectric covering 209. The sealing layer only covers the second gate line gap 411 of the gate line gap 410 located in the memory array region GB. Thus, in subsequent steps, only part of the gate sacrificial layer 220 and the connection sacrificial layer 206 can be removed through the first gate line gap 412 of the gate line gap 410 located in the step region SS.

[0175] Specifically, in combination with Figures 19A to 20B , the gate sacrificial layer 220 includes two parts along the x direction, the first gate sacrificial layer 220-1 is located in the step region SS; and the second gate sacrificial layer 220-2 is located in the memory array region GB.

[0176] After forming the encapsulation layer, for example, a dry etching process or a combination of dry and wet etching processes can be used; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. Through the first gate line gap 412, a part of the first gate sacrificial layer 220-1 adjacent to the first gate line gap 412 is removed to form a first groove 221, and the remaining part of the first gate sacrificial layer 220-1 is formed into the remaining first gate sacrificial layer 220-1'; similarly through the first gate line gap 412, a part of the connection sacrificial layer 206 adjacent to the first gate line gap 412 is removed using the same or similar process as above to form a second groove 511 and the remaining connection sacrificial layer 206', where along the z direction, the opening size H3 of the second groove 511 is larger than the opening size H4 of the first groove 412.

[0177] As an option, the opening size H3 of the second groove 511 along the z direction is greater than or equal to 1.1 times the opening size H4 of the first groove 221 along the z direction.

[0178] Since the opening size H3 of the second groove 511 is larger than the opening size H4 of the first groove 221, when the second groove 511 and the first groove 221 are filled with a groove filling layer (not shown) subsequently, the filling thickness of the part of the groove filling layer filled in the second groove 511 is different from the filling thickness of the part of the groove filling layer filled in the first groove 221. Thus, when the groove filling layer is removed subsequently, the remaining connection sacrificial layer 206' corresponding to the second groove 511 can be exposed first.

[0179] In addition, referring again to Figure 20B , in an embodiment of the present application, along the y direction, the extension length D11 of the second groove 511 satisfies: 20 nm ≤ D11 ≤ D2 / 2; and the extension length D12 of the first groove 221 satisfies: 20 nm ≤ D12 ≤ D2 / 2, where D2 is the width of the gate line gap 410 in the y direction.

[0180] As described above, the gate line gap is a process window for forming the gate conductor layer and the connection conduction layer. In subsequent processes, the first groove and the second groove can be filled as part of the gate conductor layer and the connection conduction layer. Therefore, by reasonably designing the ratio between the width D2 of the gate line gap 410 and the extension length D11 of the second groove 511, and the ratio between the width D2 of the gate line gap 410 and the extension length D12 of the first groove 221, the above process window can be optimized, and a gate conductor layer and a connection conduction layer with good filling performance can be obtained.

[0181] Figure 21A is the structure formed after forming the groove filling layer 222 according to an embodiment of the present application along Figure 1Partial cross-sectional schematic diagram taken along line A-A'. Figure 21B is a partial cross-sectional schematic diagram taken along line B-B' of the structure formed after forming the groove filling layer 222 according to an embodiment of the present application. Figure 1 Partial cross-sectional schematic diagram taken along line B-B' in

[0182] As Figures 21A to 21B shown, after forming the second groove 511 and the first groove 221, a groove filling layer 222 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The groove filling layer 222 can be a material with a high deposition rate to facilitate rapid filling of the second groove 511 and the first groove 221, and the groove filling layer 222 should be any material with a relatively high dry etching selectivity ratio with respect to the insulating layer 210 and the gate sacrificial layer 220 to facilitate removal of the groove filling layer 222 in subsequent steps. In an embodiment of the present application, the groove filling layer 222 can be a polysilicon layer.

[0183] Combined with Figure 20B and Figure 21B , the opening size H3 of the second groove 511 is greater than the opening size H4 of the first groove 221. When filling the second groove 511 and the first groove 221 with the groove filling layer 222, the filling thickness D5 of the part of the groove filling layer 222 filled in the second groove 511 is different from the filling thickness D6 of the part of the groove filling layer 222 filled in the first groove 221, and the filling thickness D5 is less than the filling thickness D6. Thus, when removing a part of the groove filling layer 222 in subsequent steps, the remaining connecting sacrificial layer 206' corresponding to the second groove 511 can be exposed first.

[0184] Figure 22A is a partial cross-sectional schematic diagram taken along line A-A' of the structure formed after forming the remaining groove filling layer 222' according to an embodiment of the present application. Figure 1 Partial cross-sectional schematic diagram taken along line A-A' in Figure 22B is a partial cross-sectional schematic diagram taken along line B-B' of the structure formed after forming the remaining groove filling layer 222' according to an embodiment of the present application. Figure 1 Partial cross-sectional schematic diagram taken along line B-B' in

[0185] As Figures 21A to 22B shown, in an embodiment of the present application, a part of the groove filling layer 222 can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, until the remaining connecting sacrificial layer 206' is exposed.

[0186] In other words, during the process of removing a part of the groove filling layer 222 by using the above process, since the filling thickness D5 is smaller than the filling thickness D6, the part of the groove filling layer 222 filled in the second groove 511 is removed first. However, for the part of the groove filling layer 222 filled in the first groove 221, since its filling thickness is relatively thick, a part of it remains and forms the remaining groove filling layer 222'.

[0187] As an option, the connecting sacrificial layer 206 can be used as the stopping layer for the above removal process. The materials for preparing the connecting sacrificial layer 206 and the groove filling layer 222 can be different, and in the above removal process, the etching rate of the groove filling layer 222 can be greater than that of the connecting sacrificial layer 206. Therefore, the loss and damage to the connecting sacrificial layer 206 during the process of removing a part of the groove filling layer 222 are relatively small. When the connecting sacrificial layer 206 is exposed, the above removal process can be stopped.

[0188] Figure 23A is a partial cross-sectional schematic view taken along line A-A' of the structure formed after forming the connecting sacrificial void 512 according to an embodiment of the present application. Figure 1 in. Figure 23B is a partial cross-sectional schematic view taken along line B-B' of the structure formed after forming the connecting sacrificial void 512 according to an embodiment of the present application. Figure 1 in. Figure 24A is a partial cross-sectional schematic view taken along line A-A' of the structure formed after forming the enlarged connecting sacrificial void 512' according to an embodiment of the present application. Figure 1 in. Figure 24B is a partial cross-sectional schematic view taken along line B-B' of the structure formed after forming the enlarged connecting sacrificial void 512' according to an embodiment of the present application. Figure 1 in.

[0189] As Figures 22A to 24B shown, after removing a part of the groove filling layer 222, the exposed remaining connecting sacrificial layer 206' can be removed to form the connecting sacrificial void 512; further, in the case where the oxide cushion layer 205 is formed in the previous step, the oxide cushion layer 205 can also be removed to form the enlarged connecting sacrificial void 512'.

[0190] Specifically, it can be achieved through at least one process, such as a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to remove the exposed remaining connecting sacrificial layer 206' to form the connecting sacrificial void 512; and to remove the oxide cushion layer 205 to form the enlarged connecting sacrificial void 512'.

[0191] By removing the connection sacrificial layer 206 and the oxide cushion layer 205, the subsequently formed connection structure (or connection conduction layer) can be directly formed on the surface of the remaining gate sacrificial layer 220.

[0192] Step S5

[0193] After forming the enlarged connection sacrificial void or the connection sacrificial void, a conductive material can be used to fill the connection sacrificial void and the first groove to form a first part of the connection structure and the gate conductor layer located in the step region, and the first part is connected to the connection structure.

[0194] As an option, in some embodiments, the gate layer can be formed while forming the connection structure. As another option, in some embodiments, the connection structure and the gate conductor layer can also be formed separately.

[0195] Hereinafter, taking the simultaneous formation of the connection structure and the gate conductor layer as an example, the specific processes of each step of preparing the connection structure and the gate layer in an embodiment of the present application will be described in detail. In addition, since the content and structure involved in separately forming the connection structure and the gate conductor layer can be fully or partially applied to the specific processes described in the following embodiments, the related or similar content will not be repeated.

[0196] As Figures 23A to 35B shown, as an option, the method of forming the gate layer 230 can include: removing the capping layer, and via the second gate line gap 411, removing the second gate sacrificial layer 220-2 of the gate sacrificial layer 210 located in the storage array region GB to form a partial gate sacrificial void 240; and forming a second part 232-2 of the gate conductor layer located in the storage array region GB in the partial gate sacrificial void 240, and forming a first part 232-1 of the gate conductor layer located in the step region SS in the first groove 221. In addition, the remaining first gate sacrificial layer 220-1' can be used as the gate dielectric layer 231. The first part 232-1 is located outside the gate dielectric layer 231 in the y direction.

[0197] Further, a method for simultaneously forming the connection structure 500 and the gate layer 230 may include: before removing the second gate sacrificial layer 220-2, forming a protective layer 513 on the inner wall of the enlarged connection sacrificial gap 512' or the connection sacrificial gap 512 and the surface of the remaining groove filling layer 222'; removing the sealing layer (polycrystalline silicon layer 208 and dielectric cover 209) to open the gate line gap 410 and the second gate line gap 411 located in the storage array region GB; via the second gate line gap 411, removing the second gate sacrificial layer 220-2 to form a partial gate sacrificial gap 240; removing the protective layer 513; and simultaneously filling the partial gate sacrificial gap 240, the enlarged connection sacrificial gap 512' (or the connection sacrificial gap 512) and the first groove 221 with a conductive material to form a gate conductor layer 232 and a connection conductor layer 502, thereby forming the gate layer 230 and the connection structure 500, wherein the gate conductor layer 232 includes a first portion 232-1 formed in the first groove 221 and a second portion 232-2 formed in the partial gate sacrificial gap 240.

[0198] Figure 25A is a partial cross-sectional schematic view taken along line A-A' of the structure formed after forming the initial protective layer 513' according to an embodiment of the present application. Figure 1 in. Figure 25B is a partial cross-sectional schematic view taken along line B-B' of the structure formed after forming the initial protective layer 513' according to an embodiment of the present application. Figure 1 in.

[0199] As Figures 24A to 25B shown, as an option, before removing the second gate sacrificial layer 220-2, an initial protective layer 513' may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The initial protective layer 513' covers the top surface 1001 of the three-dimensional memory intermediate, the inner wall of the enlarged connection sacrificial gap 512' (or the connection sacrificial gap 512), and the surface of the remaining groove filling layer 222' that faces the side surface of the remaining first gate sacrificial layer 220-1'. The initial protective layer 513' may include, but is not limited to, a semiconductor material layer such as polycrystalline silicon.

[0200] Figure 26A is a partial cross-sectional schematic view taken along line A-A' of the structure formed after forming the protective layer 513 according to an embodiment of the present application. Figure 1 in. Figure 26B is a partial cross-sectional schematic view taken along line B-B' of the structure formed after forming the protective layer 513 according to an embodiment of the present application. Figure 1 in.

[0201] As Figures 25A to 26B shown, after forming the initial protective layer 513', through at least one time, such as a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., to remove the part of the initial protective layer 513' located on the top surface 1001 of the three-dimensional memory intermediate to form the protective layer 513. The protective layer 513 is located on the inner wall of the enlarged connection sacrificial void 512' (or the connection sacrificial void 512) and the surface of the remaining groove filling layer 222', and this surface faces the side surface of the remaining first gate sacrificial layer 220-1'. During the subsequent removal of the second gate sacrificial layer 220-2, the protective layer 513 can protect the remaining first gate sacrificial layer 220-1' and the insulating wrapping layer 501 from being removed.

[0202] Figure 27A is a partial cross-sectional schematic view taken along line A-A' in Figure 26A as shown, of the structure formed after removing the dielectric covering 209 of the encapsulation layer according to an embodiment of the present application. Figure 1 Figure 27B is a partial cross-sectional schematic view taken along line B-B' in Figure 26A as shown, of the structure formed after removing the dielectric covering 209 of the encapsulation layer according to an embodiment of the present application. Figure 1 Figure 28A is a partial cross-sectional schematic view taken along line A-A' in Figure 27A as shown, of the structure formed after removing the polysilicon layer 208 according to an embodiment of the present application. Figure 1 Figure 28B is a partial cross-sectional schematic view taken along line B-B' in Figure 27A as shown, of the structure formed after removing the polysilicon layer 208 according to an embodiment of the present application. Figure 1

[0203] As Figures 26A to 28B shown, after forming the protective layer 513, through multiple times, such as a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., to remove the dielectric covering 209 of the encapsulation layer (as Figure 26A shown), and then remove the polysilicon layer 208 of the encapsulation layer (as Figure 27A shown) to open the second gate line gap 411 of the gate line gap 410 located in the memory array region GB.

[0204] Figure 29A is a partial cross-sectional schematic view taken along line A-A' in Figure 1 as shown, of the structure formed after forming a part of the gate sacrificial void 240 according to an embodiment of the present application.​​​​Figure 29B is a partial cross-sectional schematic view taken along line B-B' in the structure formed after forming the partial gate sacrificial void 240 according to an embodiment of the present application. Figure 1

[0205] As Figures 28A to 29B shown, after opening the second gate line gap 411, the gate line gap 410 can be used as a passage for providing etchant and chemical precursors, and the second gate sacrificial layer 220-2 in the initial stack structure 200' is removed by a process such as wet etching to form the partial gate sacrificial void 240. The remaining first gate sacrificial layer 220-1' and the insulating encapsulation layer 501 (which can be understood as an enlarged connection sacrificial void 512' or a connection sacrificial void 512) are not removed under the protection of the protective layer 513.

[0206] Figure 30A is a partial cross-sectional schematic view taken along line A-A' in the structure formed after exposing the first groove 221 according to an embodiment of the present application. Figure 1 Figure 30B is a partial cross-sectional schematic view taken along line B-B' in the structure formed after exposing the first groove 221 according to an embodiment of the present application. Figure 1

[0207] As Figures 29A to 30B shown, after forming the partial gate sacrificial void 240, the protective layer 513 can be removed by at least one time, such as a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to expose the remaining groove filling layer 222'. Continuing with the above-mentioned removal process for forming the remaining groove filling layer 222', the remaining groove filling layer 222' is removed, the first groove 221 can be exposed, and at the same time, the remaining first gate sacrificial layer 220-1' is also exposed.

[0208] Figure 31A is a partial cross-sectional schematic view taken along line A-A' in the structure formed after forming the initial connection structure filling layer 505' according to an embodiment of the present application. Figure 1 Figure 31B is a partial cross-sectional schematic view taken along line B-B' in the structure formed after forming the initial connection structure filling layer 505' according to an embodiment of the present application. Figure 1 Figure 32A is a partial cross-sectional schematic view taken along line A-A' in the structure formed after forming the connection structure filling layer 505 according to an embodiment of the present application. Figure 1 Figure 32B is a partial cross-sectional schematic view taken along line A-A' in the structure formed after forming the connection structure filling layer 505 according to an embodiment of the present application.Figure 1 Partial cross-sectional schematic diagram taken along line B-B' in Figure 33A It is a partial cross-sectional schematic diagram taken along line A-A' of the structure formed after forming the gate conductor layer 232 according to an embodiment of the present application Figure 1 in Figure 33B It is a partial cross-sectional schematic diagram taken along line B-B' of the structure formed after forming the gate conductor layer 232 according to an embodiment of the present application Figure 1 in

[0209] As shown in Figures 30A to 33B , the enlarged connection sacrificial void 512' (or connection sacrificial void 512), the first groove 221, and part of the gate sacrificial void 240 can be filled with a conductive material to form the connection structure 500. At the same time, the gate layer 230 can also be formed. The gate layer 230 includes a gate dielectric layer 231 and a gate conductor layer 232 that are adjacent to each other in a plane perpendicular to the z direction. The gate conductor layer 232 includes a first part 232-1 located in the step region SS and a second part 232-2 located in the memory array region GB.

[0210] Specifically, in some embodiments of the present application, the connection structure 500 may include an insulating encapsulation layer 501, a connection conduction layer 502, an inter-wall dielectric layer 503, and an adhesion layer 504. The inter-wall dielectric layer 503 may be located between the insulating encapsulation layer 501 and the connection conduction layer 502. As an option, the inter-wall dielectric layer 503 may be a high-k dielectric layer; and the adhesion layer 504 may be located between the insulating encapsulation layer 501 and the connection conduction layer 502, or between the inter-wall dielectric layer 503 and the connection conduction layer 502. The adhesion layer 504 may be, for example, a titanium nitride TiN layer. In addition, the gate conductor layer 232 may also include an inter-wall dielectric layer (not shown), an adhesion layer (not shown), and a conductive material layer (not shown).

[0211] As an option, the inter-wall dielectric layer 503, the adhesion layer 504, and the connection conduction layer 502 of the connection structure 500 may be formed simultaneously with the inter-wall dielectric layer, the adhesion layer, and the conductive material layer of the gate conductor layer 232, respectively, and the same materials may be selected for preparation. Therefore, by forming the connection conduction layer 502 and the gate conductor layer 232 simultaneously, the process steps for manufacturing the 3D memory can be reduced, and the process cost of manufacturing the 3D memory can be reduced.

[0212] In addition, the connection structure 500 further includes a connection structure filling layer 505 for filling the remaining space after forming the conductive material layer.

[0213] Specifically, as shown in Figures 30A to 31BAs shown, through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, on the partial gate sacrifice void 240, the extended connection sacrifice void 512', or the connection sacrifice void 512, the first groove 221, the gate line gap 410 including the first gate line gap 412 and the second gate line gap 411, and the top surface 1001 of the three-dimensional memory intermediate, an initial inter-wall dielectric layer 232-1', an initial adhesion layer 232-2', an initial conductive material layer 232-3', and an initial connection structure filling layer 505' are sequentially formed. By setting the above layers prepared from different materials, an initial gate conductor layer 232' as shown by the Figure 31A dashed box and an initial connection structure 500' as shown by the Figure 31B dashed box can be formed.

[0214] As shown by the Figures 31A to 32B figure, through at least one time, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove the part of the initial connection structure filling layer 505' located on the top surface 1001 of the three-dimensional memory intermediate and in the gate line gap 410, where the gate line gap 410 includes the first gate line gap 412 and the second gate line gap 411, so as to form the connection structure filling layer 505.

[0215] As shown by the Figures 32A to 33B figure, through multiple times, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to sequentially remove the part of the initial conductive material layer 232-3', the initial adhesion layer 232-2', and the initial inter-wall dielectric layer 232-1' located on the top surface 1001 of the three-dimensional memory intermediate.

[0216] After that, the part of the initial conductive material layer 232-3' and the initial adhesion layer 232-2' located in the gate line gap 410 (including the first gate line gap 412 and the second gate line gap 411) can continue to be removed through the above process, so as to form a connection structure 500 including a connection conduction layer 502, an adhesion layer 504, and an inter-wall dielectric layer 503. The conductive material layer and the adhesion layer 504 included in each stacked layer in the initial stacked structure 202' are spaced apart from the conductive material layer and the adhesion layer 504 included in the adjacent stacked layer through the insulating layer 210.

[0217] As an option, after removing the part of the initial inter-wall dielectric layer 232-1' located on the top surface 1001 of the three-dimensional memory intermediate, the part located in the gate line gap 410 (including the first gate line gap 412 and the second gate line gap 411) can also continue to be removed, and this application does not limit this.

[0218] Through the above process, while forming the connection structure 500, the gate conductor layer 232 is also formed. The gate conductor layer 232 may include a conductive material layer (not shown), an adhesive layer (not shown), and an inter-wall dielectric layer (not shown) that are formed simultaneously through the above process. After forming the gate conductor layer 232, the gate layer 230 is formed.

[0219] Refer again to Figures 30A to 33B As shown, the gate layer 230 includes two parts, the gate dielectric layer 231 and the gate conductor layer 232, which are adjacent to each other in a plane perpendicular to the first direction. The gate dielectric layer 231 is located in the step region SS. The gate conductor layer 232 includes a first part 232-1 formed by filling the first groove 221 and located in the step region SS; and a second part 232-2 formed by filling a part of the gate sacrificial void 240 and located in the memory array region GB. The first part 232-1 is located outside the gate dielectric layer 231 in the y direction, and the second part 232-2 extends in the x direction and is located between the gate dielectric layer 231 and the channel structure 300, and between adjacent channel structures 300, and is connected to the channel structure 300.

[0220] After forming the gate layer 230, the stepped terrace 201 is formed. Each stepped terrace includes an insulating layer 210 and the gate layer 230 located on the insulating layer 210.

[0221] In addition, after forming the connection conduction layer 502, the connection structure 500 is formed. The connection structure 500 may at least include an insulating wrapping layer 501 that initially wraps the connection sacrificial layer 206 (as Figure 18A shown); the connection conduction layer 502 formed on the inner wall of the filled enlarged connection sacrificial void 512' (or the connection sacrificial void 512); and the connection structure filling layer 505.

[0222] According to the manufacturing method provided by at least one embodiment of the present application, the gate layer of the three-dimensional memory includes a gate dielectric layer and a gate conductor layer that are adjacent to each other in the same layer. By providing a connection structure on a part of the surface of the gate dielectric layer corresponding to the stepped terrace, the connection structure can be connected to the part of the gate conductor layer located in the step region. Therefore, each word line contact can extend along the stacking direction of the stacked structure of the word line contact to at least the connection conduction layer of the connection structure, and realize electrical connection with the corresponding gate conductor layer through the connection structure, which can prevent word line bridging between different gate layers and improve the reliability of the three-dimensional memory.

[0223] In addition, according to at least one embodiment of the present application, only a part of the gate sacrificial layer in the initial stacked structure is removed, and the removed part is used to form the gate conductor layer. Therefore, problems such as stress deformation and wafer warping caused by processes such as etching, filling, and heat treatment required for forming the gate conductor layer can be reduced, and the overall performance of the 3D memory is improved.

[0224] In addition, by forming the connection structure and the gate conductor layer simultaneously, the process steps for manufacturing the 3D memory can be reduced, and the process cost for manufacturing the 3D memory can be lowered.

[0225] Figure 34A is a partial cross-sectional schematic view taken along line Figure 1 A-A' in the structure formed after forming the gate line gap structure 400 according to one embodiment of the present application. Figure 34B is a partial cross-sectional schematic view taken along line Figure 1 B-B' in the structure formed after forming the gate line gap structure 400 according to one embodiment of the present application. Figure 35A is a partial cross-sectional schematic view taken along line Figure 1 A-A' in the structure formed after performing planarization processing on the top surface of the stacked structure 200 according to one embodiment of the present application. Figure 35B is a partial cross-sectional schematic view taken along line Figure 1 B-B' in the structure formed after performing planarization processing on the top surface of the stacked structure 200 according to one embodiment of the present application.

[0226] As Figures 33A to 34B shown, in some embodiments of the present application, after forming the gate layer 230 and the connection structure 500, the gate line gap structure 400 can be formed by filling the gate line gap 410. Specifically, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the first gate line gap 411 and the second gate line gap 412 with a gap filling layer 420 to form the gate line gap structure 400. The gap filling layer 420 can be selected from insulating dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, or semiconductor materials such as polysilicon. The present application does not limit this. In addition, before forming the gap filling layer 420, an inner wall high-k dielectric layer (not shown) can be formed on the inner walls of the first gate line gap 411 and the second gate line gap 412.

[0227] After forming the gate line gap structure 400, the stacked structure 200 is formed.

[0228] As Figures 34A to 35BAs shown, in some embodiments of the present application, after forming the gate line gap structure 400, a planarization process may also be performed on the top surface 200-1 of the stacked structure 200. For example, a planarization process such as a chemical mechanical polishing process (Buffer CMP) with a relatively low polishing rate may be performed on the top surface 200-1. Through the planarization process, it is easier to make the stacked structure have a planar surface, which is beneficial for the subsequent formation of word line contacts to form good connectivity with the peripheral circuit and the gate layer.

[0229] Referring again to Figure 2A and Figure 3A , after forming the gate line gap structure 400, word line contacts 700 may be formed in the step region SS of the stacked structure 200. Forming the word line contacts 700 may include:

[0230] Forming a word line contact hole (not shown) extending in the z direction, the word line contact hole at least extending to the portion of the conductive material located in the connection structure 500; and filling the word line contact hole to form a word line contact 700 electrically connected to the connection structure 500. The process of the word line contact 700 may adopt existing conventional processes and be prepared according to actual needs, which will not be elaborated here.

[0231] According to the method for manufacturing a three-dimensional memory provided by at least one embodiment of the present application, the gate layer of the three-dimensional memory includes a gate dielectric layer and a gate conductor layer adjacent to each other in the same layer. By providing a connection structure on a partial surface of the gate dielectric layer corresponding to the stepped terrace, the connection structure can be connected to the portion of the gate conductor layer located in the stepped region. Thus, each word line contact can extend at least to the connection conduction layer of the connection structure along the stacking direction of the stacked structure, and is electrically connected to the corresponding gate conductor layer through the connection structure, which can prevent word line bridging between different gate layers and improve the reliability of the three-dimensional memory.

[0232] In addition, referring again to Figure 4 and Figure 5 , in the method for manufacturing a three-dimensional memory provided by at least one embodiment of the present application, a method for forming a dummy channel structure 600 is also included. Specifically, a plurality of dummy channel structures 600 are usually provided in the step region SS of the three-dimensional memory 1000. The dummy channel structures 600 may be formed after forming the initial stepped terrace 201' in step S1 and before forming the gate line gap 410 in step S4. During the process of manufacturing the three-dimensional memory 1000, when removing the gate sacrificial layer (not shown) to form the gate conductor layer 232, the dummy channel structures 600 provide strong structural support for the stacked structure 200, preventing the stacked structure 200 from collapsing or breaking.

[0233] Forming the virtual channel structure 600 may include: forming a virtual channel hole 610 extending in the z direction through at least one gate dielectric layer 231 on an initial stepped terrace (not shown); and filling the virtual channel hole 610 with an insulating dielectric material layer 620 to form the virtual channel structure 600. The process of the virtual channel structure 600 can adopt existing conventional processes and be prepared according to actual needs, which will not be elaborated here.

[0234] In the preparation method of a conventional three-dimensional memory, the virtual channel hole 610 can be formed through processes such as etching. However, with the improvement of the integration degree of the three-dimensional memory and the increase in the number of stacked layers, the maximum depth of the virtual channel hole 610 is increasingly deepened. Therefore, during the formation of the virtual channel hole 610, it is extremely easy to cause the gate layer 230 to be penetrated. If the insulating dielectric material layer 620 is not filled completely during the filling process, and the virtual channel hole 610 extends through more than one initial stepped terrace due to over-etching in the z direction, word line bridging will occur between the gate layers due to the over-etching of the virtual channel hole and the incomplete filling of the insulating dielectric material layer. Or, in the case where the virtual channel structure includes a semiconductor material layer, the semiconductor material layer formed in the virtual channel hole may cause word line bridging between the gate layers due to over-etching during the formation of the virtual channel hole.

[0235] In the three-dimensional memory preparation method provided by at least one embodiment of the present application, at least one virtual channel structure 600 can be disposed on the stepped terrace 201 of the stepped area SS of the three-dimensional memory 1000. In addition, the virtual channel structure 600 can at least penetrate its corresponding stepped terrace 201. On the one hand, in the case where the virtual channel structure includes a semiconductor material layer, since the stepped area only includes a gate dielectric layer and an insulating layer, there is no need to consider the word line bridging that occurs between the gate layers through the semiconductor material layer formed in the virtual channel hole due to over-etching during the formation of the virtual channel hole. On the other hand, considering that only a part of the gate sacrificial layer in the initial stacked structure is removed, only a smaller number of virtual channel structures are required to provide structural support for the operation of removing the gate sacrificial layer. Further, for the above reasons, the virtual channel structure provided by at least one embodiment of the present application can also appropriately change its position and number set in the stepped area to be more suitable for different architectures of the three-dimensional memory.

[0236] Refer again to Figure 1 、 Figure 2A 、 Figure 3A and Figures 7 to 9 , the method for preparing the channel structure further includes forming a local structure connected to the channel layer, and this local structure is used to form a circuit loop for the operation of the conducting memory cell.

[0237] As an option, in combination with Figure 1 、Figure 2A , Figure 3A and Figure 7 , in one embodiment of the present application, the method 2000 for manufacturing a 3D memory further includes: providing an initial substrate (not shown), on which the stack structure 200 can be formed. However, those skilled in the art should understand that without departing from the teachings of the present application, the initial substrate may include different layer structures according to different 3D memory architectures, and the present application does not limit this. For example, a local structure connected to the channel layer 330 can be formed through the initial substrate, and this local structure is used to form a circuit loop for conducting the operation of the memory cell.

[0238] Therefore, forming the channel structure 300 further includes: removing the initial substrate and exposing the part of the functional layer 320 extending into the initial substrate; removing the exposed functional layer 320 to expose a part of the channel layer 330 corresponding to the removed functional layer 320; forming a first semiconductor layer 110, and the first semiconductor layer 110 covers the exposed part in the channel layer 330.

[0239] Furthermore, after exposing a part of the channel layer 330 corresponding to the removed functional layer 320, the exposed channel layer 330 can be, for example, N-type doped by processes such as ion implantation IMP. The above N-type doping can include any suitable N-type dopant (for example, phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor. As Figure 7 shown, after re-high doping the exposed channel layer 330, the channel layer 330 can include a first region 333 formed by a secondary doping process. Compared with other adjacent regions of the first region 333, for example, compared with a second region 334 located on one side of the first region 333 and away from the first semiconductor layer 110, the doping concentration of the conductive impurities in the first region 333 is greater than the doping concentration of the conductive impurities in the second region 334. Therefore, by increasing the doping concentration of the conductive impurities in the part of the channel layer closer to the first semiconductor layer, a good and stable electrical connection between the channel layer and the first semiconductor layer can be achieved, improving the electrical performance of the 3D memory.

[0240] As another option, in combination with Figure 1 , Figure 2A , Figure 3A and Figure 8, in an embodiment of the present application, the method for manufacturing a 3D memory further includes: providing an initial substrate (not shown) including a substrate sacrificial layer (not shown); removing the substrate sacrificial layer in the initial substrate to form a substrate void (not shown); the substrate void may expose a side portion of the functional layer 320, and a part of the side of the exposed functional layer 32 is removed via the substrate void to expose a part of the channel layer 330 corresponding to the removed functional layer 320; and filling the above substrate void with a second semiconductor layer 130, and the second semiconductor layer 130 forms an extension in the initial substrate through the exposed part in the channel layer 330.

[0241] As another option, in combination with Figure 1 , Figure 2A , Figure 3A and Figure 9 , in an embodiment of the present application, the method for manufacturing a 3D memory further includes: forming a plurality of channel holes 310 penetrating an initial stacked structure (not shown) in the z direction; forming an epitaxial layer 120 at the bottom of the channel holes 310; forming an initial functional layer (not shown) on the inner walls of the channel holes 310 and the surface of the epitaxial layer 120; removing the part of the initial functional layer located on the surface of the epitaxial layer 120 to form a functional layer 320 and expose a part of the epitaxial layer 120; and forming a channel layer 330 connected to the epitaxial layer 120 on the surface of the functional layer 320 and the surface of the exposed epitaxial layer 120.

[0242] In addition, as Figure 10 and Figure 11 shown, in the method 2000 for manufacturing a 3D memory provided in at least one embodiment of the present application, the stacked structure 200 may have a plurality of stepped areas 01 and a plurality of memory array areas 02, each memory array area 02 corresponds to at least one stepped area 01, wherein the stepped area 01 can be used to form a plurality of stepped steps, and the memory array area 02 can be used to form a memory array composed of a plurality of channel structures arranged and distributed. Subsequently, the gate layers in the memory array can be connected and conducted in one-to-one correspondence through the word line contacts formed on each stepped step.

[0243] As Figure 10 shown, according to some embodiments, at least one stepped area 01 can be provided at one side edge or multiple side edges of the stacked structure 200. As Figure 11As shown, according to some embodiments, at least one step region 01 may be provided in the middle of the stacked structure 200, and the corresponding memory array region 02 may be divided into at least two sub-memory array regions. The present application does not limit the relative positions and specific structures of the step region 01 and the memory array region 02. In addition, the stacked structure 200 may further include a peripheral circuit region for forming a peripheral circuit. Although exemplary fabrication methods and structures of the three-dimensional memory are described herein, it can be understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. In addition, the materials of the exemplified layers are merely exemplary.

[0244] Figure 36 FIG. 4 is a schematic structural diagram of a storage system 30000 according to an embodiment of the present application.

[0245] As Figure 36 shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a memory 20000 and a controller 32000. The memory 20000 may be the same as the memory described in any of the above embodiments, and the present application will not repeat it here. The storage system 30000 may be a two-dimensional storage system or a three-dimensional storage system. Hereinafter, a three-dimensional storage system will be taken as an example for description.

[0246] As an option, the three-dimensional memory may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0247] Specifically, the three-dimensional storage system 30000 may include a three-dimensional memory 20000 and a controller 32000. The three-dimensional memory 20000 may be the same as the three-dimensional memory described in any of the above embodiments, and the present application will not repeat it here. The controller 32000 may control the three-dimensional memory 20000 through a channel CH, and the three-dimensional memory 20000 may perform operations in response to requests from a host 31000 based on the control of the controller 32000. The three-dimensional memory 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access a region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 20000 may perform internal operations corresponding to the command on the region selected by the address.

[0248] In some embodiments, the three-dimensional storage system can be implemented as, for example, a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a storage device of the personal computer memory card international association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card, or a memory stick, etc. This application provides peripheral circuits, memories, and storage systems, which have the same beneficial effects as the three-dimensional memory provided in this application due to the provision of the three-dimensional memory provided in this application, and will not be elaborated here.

[0249] The above description is only a preferred embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by the selected combination of the above technical features, but also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solution formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A three-dimensional memory, characterized in that, Comprising: A stacked structure including a plurality of stepped levels, each of the stepped levels including an insulating layer and a gate layer disposed on the insulating layer, wherein the gate layer includes a gate conductor layer and a gate dielectric layer that are adjacent to each other in a plane perpendicular to a first direction, and the first direction is the stacking direction of the stacked structure; A connection structure covering a partial surface of the gate dielectric layer of a corresponding one of the stepped levels and electrically connected to a first portion of the gate conductor layer that is outside the gate dielectric layer in a second direction, wherein the stacked structure is divided into a stepped area and a memory array area in a third direction, the stepped area includes a plurality of the stepped levels, and the first direction, the second direction, and the third direction are perpendicular to each other; And A word line contact extending at least along the first direction to a connection conduction layer of the connection structure and electrically connected to a corresponding gate conductor layer through the connection structure.

2. The memory according to claim 1, wherein The memory further includes a gate line gap structure penetrating the stacked structure along the first direction, and a plurality of the gate line gap structures are spaced apart in the second direction; The gate dielectric layer between two adjacent ones of the gate line gap structures includes a top surface, and two side surfaces adjacent to the top surface and opposite to each other in the second direction; and The connection structure covers the top surface and the side surfaces of the gate dielectric layer of a corresponding one of the stepped levels.

3. The memory according to claim 2, wherein, The gate line gap structure includes a gate line gap and a gap filling dielectric layer filled in the gate line gap, wherein a length D1 of a portion of the gate conductor layer that is outside the gate dielectric layer in the second direction in the second direction satisfies: 20nm ≤ D1 ≤ D2 / 2, wherein D2 is a width of the gate line gap in the second direction.

4. The memory according to claim 2, wherein A thickness H1 of a portion of the connection structure covering the top surface in the first direction satisfies: H1 ≥ 1.1×H2, wherein H2 is a thickness of the gate dielectric layer in the first direction.

5. The memory according to claim 1, wherein, The gate conductor layer is located in the memory array area and the stepped area, and the gate dielectric layer is located in the stepped area.

6. The memory according to any one of claims 1 to 5, wherein The connection structure sequentially includes an insulating wrapping layer, a connection conduction layer, and a connection structure filling layer from outside to inside.

7. A method for fabricating a three-dimensional memory, characterized in that, The method includes: Alternately stacking an insulating layer and a gate sacrificial layer along a first direction to form an initial stacked structure, wherein the initial stacked structure is divided into a stepped area and a memory array area in a third direction perpendicular to the first direction; Forming a plurality of initial stepped levels in the stepped area of the initial stacked structure, and exposing a part of an upper surface of the gate sacrificial layer in each of the initial stepped levels; Forming a connection sacrificial structure on the exposed upper surface of the gate sacrificial layer, the connection sacrificial structure including a connection sacrificial layer; Form a gate line gap penetrating the initial stacked structure. Through the first gate line gap, remove a part of the first gate sacrificial layer adjacent to the first gate line gap to form a first groove, and remove the connection sacrificial layer to form a connection sacrificial void, where the first gate line gap is the part of the gate line gap located in the step region, and the first gate sacrificial layer is the part of the gate sacrificial layer located in the step region; Fill the connection sacrificial void and the first groove with a conductive material to form a connection structure and a first part of the gate conductor layer located in the step region, and the first part is connected to the connection structure. Wherein, only a part of the first gate sacrificial layer is removed, and the remaining part of the first gate sacrificial layer is formed into a gate dielectric layer, and the gate dielectric layer is adjacent to the gate conductor layer in a plane perpendicular to the first direction; and The connection structure covers a part of the surface of the gate dielectric layer, and the first part is located outside the gate dielectric layer in a second direction, and the second direction is perpendicular to both the first direction and the third direction.

8. The method according to claim 7, wherein, The gate line gap extends through the storage array region and the step region in the third direction, and the third direction is the extending direction of the initial stepped step. Wherein, forming the connection sacrificial void and forming the first groove include: Form a closed layer covering the second gate line gap, where the second gate line gap is the part of the gate line gap located in the storage array region; and Through the first gate line gap, remove a part of the connection sacrificial layer adjacent to the first gate line gap to form a second groove, where the opening size of the second groove in the first direction is larger than that of the first groove, and the first direction is the stacking direction of the initial stacked structure; Fill the first groove and the second groove with a groove filling layer; Remove a part of the groove filling layer to expose the remaining connection sacrificial layer; Remove the remaining connection sacrificial layer to form the connection sacrificial void; and Remove the remaining groove filling layer to expose the first groove.

9. The method according to claim 8, wherein, The opening size of the second groove is greater than or equal to 1.1 times the opening size of the first groove.

10. The method according to claim 8, wherein, The extension length D12 of the first groove in the second direction satisfies: 20nm ≤ D12 ≤ D2 / 2; and The extension length D11 of the second groove in the second direction satisfies: 20nm ≤ D11 ≤ D2 / 2, Wherein, D2 is the width of the gate line gap in the second direction; and the second direction is perpendicular to the third direction and the first direction.

11. The method according to claim 7, wherein, The method further includes: Before forming the connection sacrificial structure, the method further includes: Form an oxide cushion layer on the surface of the stepped step; and Form the connection sacrificial structure on the part of the oxide cushion layer corresponding to the exposed upper surface of each gate sacrificial layer; and After removing the connection sacrificial layer, the method further includes: Remove the oxide cushion layer to form the connection sacrificial void.

12. The method according to claim 8, wherein The method further includes: Remove the capping layer and, via the second gate line gap, remove the second gate sacrificial layer of the gate sacrificial layer located in the storage array region to form a partial gate sacrificial void; and Form a second portion of the gate conductor layer located in the storage array region within the partial gate sacrificial void.

13. The method according to claim 12, wherein Before removing the capping layer, the method further includes: Via the first gate line gap, form a protective layer on the inner wall of the connection sacrificial void and the surface of the remaining trench fill layer; and After forming the gate sacrificial void, the method further includes: Remove the protective layer.

14. The method according to claim 12, wherein The method further includes: While forming the connection structure, form the gate conductor layer.

15. The method according to claim 12, wherein Forming a word line contact electrically connected to the connection structure includes: Forming a word line contact hole extending in the first direction, the word line contact hole extending at least to the portion of the conductive material located in the connection structure; and Filling the word line contact hole to form the word line contact electrically connected to the connection structure.

16. The method according to any one of claims 8 to 15, wherein The method further includes: Form a channel hole that penetrates the initial stacked structure in a first direction and extends to the initial substrate, wherein the first direction is the stacking direction of the initial stacked structure; Sequentially form a functional layer and a channel layer on the inner wall of the channel hole; Remove the initial substrate and expose the functional layer extending into the initial substrate; Remove the exposed functional layer to expose the channel layer corresponding to the removed functional layer; Dope the exposed channel layer; and Form a first semiconductor layer that covers the exposed channel layer.

17. The method according to any one of claims 8 to 15, wherein The connection sacrificial structure further includes an insulating wrapping layer that wraps the connection sacrificial layer, wherein filling the connection sacrificial void with a conductive material to form a connection structure includes: On the inner wall of the connection sacrificial void, form a connection conduction layer; and Fill the remaining space of the connection sacrificial void with a connection structure fill layer to form the connection structure.

18. A storage system, characterized in that, The storage system includes: a controller and the memory according to any one of claims 1 to 6, the controller being coupled to the memory and configured to control the memory to store data.

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