RC Coupled Silicon Controlled Rectifier Structure with High Holding Voltage and Low Trigger Voltage

Abstract

The present invention provides an RC-coupled silicon-controlled rectifier structure with a high holding voltage and a low trigger voltage, which includes a P-type substrate, on which an adjacent N-well and a P-well are formed; a first shallow trench isolation is provided at the junction of the N-well and the P-type substrate, and a second shallow trench isolation is provided on the N-well. A first N-type ion implantation layer and a first P-type ion implantation layer are sequentially formed in the N-well from the first shallow trench isolation to the second shallow trench isolation; a first connection structure is provided on the first N-type ion implantation layer for leading out the anode; a second P-type ion implantation layer spanning the junction of the N-well and the P-type substrate is formed on the P-type substrate, and a gate is formed on the N-well between the second shallow trench isolation and the second P-type ion implantation layer. The present invention can regulate the trigger voltage by changing the value of RC; has a relatively high holding voltage; the lower trigger voltage and the higher holding voltage enable the new structure to have higher latch-up resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an RC-coupled silicon controlled rectifier structure with a high holding voltage and a low trigger voltage. Background Art

[0002] With the development of integrated circuits, the operating voltage is getting lower and lower, and the on-chip ESD (low-capacitance electrostatic) protection ability is increasingly difficult to meet the requirements, and the latching risk is also gradually increasing. With the continuous reduction of the manufacturing process, the thickness of the gate oxide layer of transistors is getting thinner and thinner, and the gate oxide breakdown voltage and operating voltage are both continuously decreasing. In addition, the rate of decrease in the chip operating voltage is lower than the rate of decrease in the gate oxide breakdown voltage and the source-drain breakdown voltage of transistors. Therefore, when performing ESD design, a 10% safety margin must be considered, resulting in an increasingly narrow ESD design window and extremely limited ESD options. The silicon controlled rectifier (SCR) is the most robust ESD protection device per unit area and can be regarded as a positive feedback loop composed of two parasitic transistors, PNP and NPN. Its IV (current-voltage) characteristic shows an obvious hysteresis characteristic, and the holding voltage is often very low, which is extremely likely to cause the latching effect.

[0003] The GGNMOS (grounded NMOS transistor) is triggered by the breakdown voltage of the junction between the N-type implanted ions and the P-well, and has a relatively low trigger voltage. And research shows that embedding the GGNMOS into the SCR can effectively reduce the trigger voltage, and this new structure is named the low trigger voltage silicon controlled rectifier (LVTSCR). The GGNMOS accelerates the trigger process of the LVTSCR, but the strong hysteresis of the SCR results in the holding voltage of the LVTSCR still being very low, facing a high latching risk. Therefore, by introducing an N-type or P-type cross-connected region at the N-well and P-well junction contact, the formed modified lateral silicon controlled rectifier (MLSCR) can also reduce the trigger voltage of the SCR. In addition, the cross-connected region in the MLSCR provides an ESD shunt path, which can reduce the ESD current of the in-body parasitic SCR path, thereby increasing the holding voltage of the MLSCR. However, the trigger voltage of the MLSCR may be higher than the breakdown voltage of the gate oxide under low-voltage operation, and it is still not sufficient to protect the internal circuit from failure.

[0004] To solve the above problems, a new type of silicon controlled rectifier structure with adjustable low trigger voltage and high holding voltage is needed. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an RC-coupled silicon-controlled rectifier structure with a high holding voltage and a low trigger voltage, which is used to solve the problems in the prior art that the low-capacitance electrostatic design window becomes narrower and narrower, and the available low-capacitance electrostatic solutions are extremely limited; the current-voltage characteristics of the silicon-controlled rectifier show an obvious hysteresis characteristic, and the holding voltage is often very low, which is extremely prone to the problem of latch-up effect.

[0006] To achieve the above object and other related objects, the present invention provides an RC-coupled silicon-controlled rectifier structure with a high holding voltage and a low trigger voltage, including:

[0007] A P-type substrate, on which an adjacent N-well and a P-well are formed;

[0008] A first shallow trench isolation is provided at the junction of the N-well and the P-type substrate, and a second shallow trench isolation is provided on the N-well. An adjacent first N-type ion implantation layer and a first P-type ion implantation layer are sequentially formed in the N-well from the first shallow trench isolation to the second shallow trench isolation;

[0009] A first connection structure is provided on the first N-type ion implantation layer for leading out the anode;

[0010] A second P-type ion implantation layer is formed on the P-type substrate across the junction of the N-well and the P-type substrate, and a gate is formed on the N-well between the second shallow trench isolation and the second P-type ion implantation layer;

[0011] A second connection structure for electrically connecting the gate and the second P-type ion implantation layer is formed;

[0012] A fifth shallow trench isolation is provided at the junction of the P-well and the P-type substrate. The P-well from the second P-type ion implantation layer to the fifth shallow trench isolation is sequentially provided with a third shallow trench isolation, a second N-type ion implantation layer, a fourth shallow trench isolation, and a third P-type ion implantation layer;

[0013] A third connection structure for connecting the second N-type ion implantation layer and the third P-type ion implantation layer is provided for leading out the cathode.

[0014] Preferably, it is a silicon substrate.

[0015] Preferably, the areas of the second P-type ion implantation layer located in the N-well and the P-well are equal.

[0016] Preferably, the ions doped in the N-well are boron ions.

[0017] Preferably, the ions doped in the N-well are boron ions.

[0018] Preferably, the ions doped in the N well are boron ions.

[0019] Preferably, the ions doped in the first N-type ion implantation layer and the second N-type ion implantation layer are both arsenic ions.

[0020] Preferably, the ions doped in the first P-type ion implantation layer, the second P-type ion implantation layer, and the third P-type ion implantation layer are all boron ions.

[0021] Preferably, the material of the gate is doped polysilicon.

[0022] As described above, the RC-coupled silicon-controlled rectifier structure of the present invention with a high holding voltage and a low trigger voltage has the following beneficial effects:

[0023] Due to the existence of the well resistance Rp and the gate capacitance C coupling effect in the present invention, the trigger voltage of its structure is lower, and the trigger voltage can be regulated by changing the value of RC; since the P-type ion implantation layer of the anode is floating, it is equivalent to connecting an anti-parallel diode in series, and the current needs to conduct the anti-parallel diode to conduct the silicon-controlled rectifier path, so it has a higher holding voltage; the lower trigger voltage and the higher holding voltage make the new structure have higher latch-up resistance; without changing the original layout area, it has a certain process compatibility. Description of the Drawings

[0024] Figure 1 It shows a schematic diagram of the silicon-controlled rectifier structure of the present invention;

[0025] Figure 2 It shows a schematic diagram of the parasitic circuit of the silicon-controlled rectifier structure of the present invention.

[0026] Reference Numerals:

[0027] P-type substrate - 01

[0028] N well - 02

[0029] P well - 03

[0030] First shallow trench isolation - 04

[0031] Second shallow trench isolation - 05

[0032] Third shallow trench isolation - 06

[0033] Fourth shallow trench isolation - 07

[0034] Fifth shallow trench isolation - 08

[0035] First N-type ion implantation layer - 09

[0036] First P-type ion implantation layer - 10

[0037] Gate - 11

[0038] Second P - type ion implantation layer - 12

[0039] Second N - type ion implantation layer - 13

[0040] Third P - type ion implantation layer - 14

[0041] First connection structure - 15

[0042] Second connection structure - 16

[0043] Third connection structure - 17 Detailed implementation manners

[0044] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] Please refer to Figure 1 , the present invention provides an RC - coupled silicon - controlled rectifier structure with a high holding voltage and a low trigger voltage, including:

[0046] A P - type substrate 01, on which an adjacent N - well 02 and P - well 03 are formed;

[0047] A first shallow trench isolation 04 is provided at the junction of the N - well 02 and the P - type substrate 01. A second shallow trench isolation 05 is provided on the N - well 02. Adjacent first N - type ion implantation layer 09 and first P - type ion implantation layer 10 are sequentially formed on the N - well 02 from the first shallow trench isolation 04 to the second shallow trench isolation 05;

[0048] In an embodiment of the present invention, the P - type substrate 01 is a silicon substrate. The N - well 02 and P - well 03 can be first formed by ion implantation on the silicon substrate, and then grooves for forming shallow trench isolation (STI) are formed on the substrate through photolithography and etching. Then, a shallow trench isolation structure is formed by depositing an insulating material and polishing in the grooves. In an embodiment of the present invention

[0049] A first connection structure 15 is provided on the first N - type ion implantation layer 09 for leading out the anode;

[0050] In an embodiment of the present invention, after the device fabrication is completed in the front-end process, the interconnection between devices is carried out through the back-end process to form the first connection structure 15. Specifically, an interlayer dielectric layer can be deposited layer by layer on the device after ion implantation by chemical vapor deposition. The material of the interlayer dielectric layer can be silicon dioxide. Then, the interlayer dielectric layer is etched to form a contact hole communicating with the first N-type ion implantation layer 09. Then, a conductive material is filled in the contact hole. The filling material can be tungsten (W), and the interconnection can be made of Al.

[0051] A second P-type ion implantation layer 12 is formed on the P-type substrate 01 across the junction of the N-well 02 and the P-type substrate 01. A gate 11 is formed on the N-well 02 between the second shallow trench isolation 05 and the second P-type ion implantation layer 12.

[0052] A second connection structure 16 for electrically connecting the gate 11 and the second P-type ion implantation layer 12 is formed on the gate 11 and the second P-type ion implantation layer 12.

[0053] In an embodiment of the present invention, after the device fabrication is completed in the front-end process, the interconnection between devices is carried out through the back-end process to form the second connection structure 16. Specifically, an interlayer dielectric layer can be deposited layer by layer on the device after ion implantation by chemical vapor deposition. The material of the interlayer dielectric layer can be silicon dioxide. Then, the interlayer dielectric layer is etched to form a contact hole communicating with the gate 11 and the second P-type ion implantation layer 12. Then, a conductive material is filled in the contact hole. The filling material can be tungsten (W), and the interconnection can be made of Al.

[0054] In an embodiment of the present invention, the areas of the second P-type ion implantation layer 12 located in the N-well 02 and the P-well 03 are equal.

[0055] A fifth shallow trench isolation 08 is provided at the junction of the P-well 03 and the P-type substrate 01. In the P-well 03 from the second P-type ion implantation layer 12 to the fifth shallow trench isolation 08, a third shallow trench isolation 06, a second N-type ion implantation layer 13, a fourth shallow trench isolation 07, and a third P-type ion implantation layer 14 are provided in sequence.

[0056] A third connection structure 17 for connecting the second N-type ion implantation layer 13 and the third P-type ion implantation layer 14 is provided on the second N-type ion implantation layer 13 and the third P-type ion implantation layer 14 for leading out the cathode.

[0057] In an embodiment of the present invention, after the device fabrication is completed in the front-end process, the interconnection between devices is carried out through the back-end process to form the second connection structure 17. Specifically, an interlayer dielectric layer can be deposited layer by layer on the device after ion implantation by chemical vapor deposition. The material of the interlayer dielectric layer can be silicon dioxide. Then, the interlayer dielectric layer is etched to form a contact hole communicating with the second N-type ion implantation layer 13 and the third P-type ion implantation layer 14. Then, a conductive material is filled in the contact hole. The filling material can be tungsten (W), and the interconnection can be made of Al.

[0058] Please refer to Figure 2 , that is to say, in the embodiment of the present invention, the well resistance Rp and the gate capacitance C are combined to form an RC circuit and embedded into the LVTSCR structure. The values of the well resistance Rp and the gate capacitance C are mainly determined by the doping concentration of the P well and the thickness of the local field oxide; the P-type ion implantation region of the anode is in a floating state, and at the same time, the gate is connected to the across P-type ion implantation region through metal interconnection, which is equivalent to generating a P well resistance. Due to the RC coupling effect, the trigger voltage of the new structure is reduced; the floating of the P-type ion implantation region of the anode will result in the need for more hole-electron pairs to maintain the opening of the reverse-biased junction, thereby keeping the SCR conducting and further increasing the holding voltage.

[0059] In the embodiment of the present invention, the ions doped in the N well 02 are boron ions.

[0060] In the embodiment of the present invention, the ions doped in the N well 02 are boron ions.

[0061] In the embodiment of the present invention, the ions doped in the N well 02 are boron ions.

[0062] In the embodiment of the present invention, the ions doped in the first N-type ion implantation layer 09 and the second N-type ion implantation layer 13 are both arsenic ions.

[0063] In the embodiment of the present invention, the ions doped in the first P-type ion implantation layer 10, the second P-type ion implantation layer 12, and the third P-type ion implantation layer 14 are all boron ions.

[0064] In the embodiment of the present invention, the material of the gate 11 is doped polysilicon.

[0065] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0066] In summary, due to the existence of the coupling effect of the well resistance Rp and the gate capacitance C in the present invention, the trigger voltage of its structure is lower, and at the same time, the trigger voltage can be regulated by changing the value of RC; due to the floating of the P-type ion implantation layer of the anode, it is equivalent to connecting a reverse-biased diode in series, and the current needs to conduct the reverse-biased diode to conduct the silicon-controlled rectifier path, so it has a higher holding voltage; the lower trigger voltage and the higher holding voltage make the new structure have higher latch-up resistance; without changing the original layout area, it has a certain process compatibility. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0067] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An RC-coupled silicon controlled rectifier structure with a high holding voltage and a low trigger voltage, characterized in that, Including: A P-type substrate, on which an adjacent N-well and a P-well are formed; A first shallow trench isolation is provided at the junction of the N-well and the P-type substrate, and a second shallow trench isolation is provided on the N-well. An adjacent first N-type ion implantation layer and a first P-type ion implantation layer are sequentially formed in the N-well from the first shallow trench isolation to the second shallow trench isolation; A first connection structure is provided on the first N-type ion implantation layer for leading out the anode, and the first P-type ion implantation layer is not connected to the first connection structure; A second P-type ion implantation layer is formed on the P-type substrate across the junction of the N-well and the P-well, and a gate is formed on the N-well between the second shallow trench isolation and the second P-type ion implantation layer; A second connection structure is formed on the gate and the second P-type ion implantation layer for electrically connecting the two; A fifth shallow trench isolation is provided at the junction of the P-well and the P-type substrate. In the P-well from the second P-type ion implantation layer to the fifth shallow trench isolation, a third shallow trench isolation, a second N-type ion implantation layer, a fourth shallow trench isolation, and a third P-type ion implantation layer are sequentially provided; A third connection structure for connecting the second N-type ion implantation layer and the third P-type ion implantation layer is provided for leading out the cathode.

2. The RC-coupled silicon controlled rectifier structure with a high holding voltage and a low trigger voltage according to claim 1, characterized in that: The P-type substrate is a silicon substrate.

3. The RC-coupled silicon-controlled rectifier structure with a high holding voltage and a low trigger voltage according to claim 1, characterized in that: The area of the second P-type ion implantation layer located in the N-well and the P-well is equal.

4. The RC-coupled silicon controlled rectifier structure with a high holding voltage and a low trigger voltage according to claim 1, wherein: The ions doped in the N-well are phosphorus ions.

5. The RC-coupled silicon controlled rectifier structure with a high holding voltage and a low trigger voltage according to claim 1, wherein: The ions doped in the P-well are boron ions.

6. The RC-coupled silicon controlled rectifier structure with a high holding voltage and a low trigger voltage according to claim 1, characterized in that: The ions doped in the first N-type ion implantation layer and the second N-type ion implantation layer are both arsenic ions.

7. The RC-coupled silicon-controlled rectifier structure with a high holding voltage and a low trigger voltage according to claim 1, wherein: The ions doped in the first P-type ion implantation layer, the second P-type ion implantation layer, and the third P-type ion implantation layer are all boron ions.

8. The RC-coupled silicon-controlled rectifier structure with a high holding voltage and a low trigger voltage according to claim 1, characterized in that: The material of the gate is doped polysilicon.

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