CMOS Devices Based on GaN / YAlN / GaN Heterojunctions and Their Manufacturing Methods

Abstract

The present invention discloses a CMOS device based on a GaN / YAlN / GaN heterojunction and a manufacturing method thereof, mainly solving the problem of low carrier concentration and mobility of existing GaN-based CMOS. It includes, from bottom to top: a substrate, a buffer layer, a GaN n-type channel layer, a YAlN barrier layer, a GaN p-type channel layer, a p-GaN layer, and an insulating gate dielectric layer, and an isolation groove with a depth reaching the middle of the n-type channel layer is provided in the middle; a right gate electrode is provided on the p-GaN layer on the right side of the isolation groove, and right source and drain electrodes are provided at both ends of the YAlN barrier layer to form an n-type field effect transistor; a left gate electrode is provided on the insulating gate dielectric layer on the left side of the isolation groove, and left source and drain electrodes are provided at both ends of its p-GaN layer to form a p-type field effect transistor, and these two field effect transistors are interconnected. The present invention can improve the carrier concentration and mobility of the CMOS device, increase the operating frequency and output power of the device, and can be used in all-GaN power systems.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a GaN-based complementary metal oxide semiconductor field effect transistor (CMOS), which can be used for monolithic integration of power switches and other peripheral circuits, namely a "fully GaN" power system. Technical Background

[0002] Compared with Si materials applied to traditional electronic power devices, group III nitride semiconductor materials have superior properties such as a large bandgap, a high breakdown electric field strength, a high saturated electron mobility, a large thermal conductivity, a small dielectric constant, and a strong anti-radiation ability. In addition, the carrier density induced by polarization in gallium nitride is independent of temperature. Therefore, GaN is considered to be a good candidate material for power integrated circuits applied under harsh environmental conditions.

[0003] In current power modules involving GaN devices, the peripheral logic control and drive circuits are still realized by separate SiCMOS integrated circuits. This solution will occupy a large amount of circuit board space and generate parasitic inductance, which greatly limits the advantages of the high switching frequency of GaN HEMT devices, so the frequency of the system is affected. The monolithic integration of GaN drive logic and GaN power switch devices is extremely important for realizing a small-sized power module with low parasitic inductance and high switching speed. The "fully GaN" solution helps to release the full potential of GaN power electronic devices, especially the high-speed switching ability, which can greatly suppress the parasitic inductance generated by off-chip interconnections and can also enhance the system-level functions and reliability. In the past two years, GaN-based complementary logic circuits have been studied and demonstrated, and monolithic GaN CL gates with true "CMOS-like" behavior have also been obtained. GaN-based complementary logic integrated circuits are currently just in their infancy and need to further optimize the performance of the devices. The carrier concentration and mobility both need to be improved. In particular, the channel mobility of current GaN-based p-channel MOSFETs is low and the on-resistance is high.

[0004] The conventional CMOS device structure using a GaN / AlGaN / GaN heterojunction is as Figure 1 shown. From bottom to top, it is a substrate, a buffer layer, a GaN n-channel layer, an AlGaN barrier layer, a p-GaN layer, and an isolation groove is provided in the middle; a right gate electrode is provided on the p-GaN layer on the right side of the isolation groove, and a right source electrode and a right drain electrode are provided at both ends of the barrier layer on the right side of the isolation groove to form an n-type field effect transistor (n-FET); a left gate electrode is provided on the insulating gate dielectric layer on the left side of the isolation groove, and a left source electrode and a left drain electrode are provided at both ends of the p-GaN layer on the left side of the isolation groove to form a p-type field effect transistor (p-FET). This device has the following three disadvantages:

[0005] First, the lattice mismatch between the AlGaN material and the GaN material will cause the generation of tensile strain. The large strain will lead to the deterioration of crystal quality and reduce the device performance.

[0006] Second, the polarization intensity of the AlGaN barrier layer is limited. The two-dimensional hole gas concentration and mobility generated by the polarization effect are not high enough, which limits the device response speed.

[0007] Third, enhancing the polarization intensity of the barrier layer can only be achieved by increasing the Al component of AlGaN, which will not only further increase the lattice mismatch between layers, but also increase the difficulty of epitaxial technology. In addition, the critical relaxation thickness of the material will also decrease sharply, affecting the two-dimensional electron gas and two-dimensional hole gas concentrations, resulting in the deterioration of the device output characteristics. Summary of the Invention

[0008] The object of the present invention is to propose a CMOS device based on a GaN / YAlN / GaN heterojunction and its manufacturing method in view of the deficiencies of the existing technologies, so as to effectively reduce the strain of the barrier layer, improve the crystal quality, enhance the polarization intensity of the barrier layer, increase the carrier concentration and mobility, improve the device operating frequency and output power, and improve the device reliability.

[0009] The technical solution to achieve the object of the present invention is as follows:

[0010] 1. A CMOS device based on a GaN / YAlN / GaN heterojunction, which includes, from bottom to top: a substrate, a buffer layer, a GaN n-type channel layer, a barrier layer, a p-GaN layer, an insulating gate dielectric layer. There is an isolation groove in the middle of the p-GaN layer, the barrier layer and the GaN n-type channel layer, and the depth of the isolation groove reaches the middle of the GaN n-type channel layer; a right gate electrode is provided on the p-GaN layer on the right side of the isolation groove, and right source and drain electrodes are provided at both ends of the barrier layer on the right side of the isolation groove to form an n-type field effect transistor n-FET; a left gate electrode is provided on the insulating gate dielectric layer on the left side of the isolation groove, and left source and drain electrodes are provided at both ends of the p-GaN layer on the left side of the isolation groove to form a p-type field effect transistor p-FET, and its characteristics are:

[0011] An undoped GaN p-type channel layer with a thickness of 20nm - 40nm is additionally provided between the p-GaN layer and the barrier layer on both sides of the isolation groove to improve the carrier mobility;

[0012] The barrier layer uses a YAlN material with an Al component of 85% - 94% and a thickness of 15nm - 30nm to reduce the strain of the barrier layer and enhance the polarization intensity of the barrier layer.

[0013] Further, the substrate uses <111>-oriented Si.

[0014] Further, the buffer layer is made of GaN material with a thickness of 3μm - 4.5μm.

[0015] Further, the p-GaN layer has a thickness of 70nm - 80nm and a doping concentration of 3×10 19 cm -3 -4×10 19 cm -3 。

[0016] Further, the thickness of the GaN n-channel layer is 150nm - 480nm.

[0017] Further, the insulating gate dielectric layer is made of Al2O3 material with a thickness of 10nm - 20nm.

[0018] 2. A preparation method of a CMOS device based on a GaN / YAlN / GaN heterojunction, characterized by comprising the following steps:

[0019] 1) On a substrate, grow a buffer layer with a thickness of 3μm - 4.5μm by using the MOCVD process;

[0020] 2) On the buffer layer, grow a GaN n-channel layer with a thickness of 150nm - 480nm by using the MOCVD process;

[0021] 3) On the GaN n-channel layer, grow a YAlN barrier layer with an Al composition of 85% - 94% and a thickness of 15nm - 30nm by using the MOCVD process;

[0022] 4) On the YAlN barrier layer, grow an undoped GaN p-channel layer with a thickness of 20nm - 40nm by using the MOCVD process;

[0023] 5) On the GaN p-channel layer, grow a p-GaN layer with a thickness of 70nm - 80nm by using the MOCVD process;

[0024] 6) Perform selective dry etching on the p-GaN layer, and the etching depth is from the surface to the interface between the GaN p-channel layer and the YAlN barrier layer;

[0025] 7) At both ends of the etched YAlN barrier layer, deposit a Ti / Al / Ni / Au metal stack with thicknesses of 20nm / 120nm / 40nm / 50nm in sequence by using the electron beam evaporation process, and then perform rapid thermal annealing in an N2 environment at 830°C - 900°C to form a right source electrode and a right drain electrode;

[0026] 8) Perform step etching on the YAlN barrier layer on the left side of the right drain electrode by using the plasma reactive ion etching process to form an isolation groove with a depth of 150nm;

[0027] 9) The Ni / Au metal stack with thicknesses of 15 nm / 20 nm is deposited on both ends of the p-GaN layer on the left side of the isolation groove by electron beam evaporation process, and annealed in an O2 environment at 550 °C to form the left source electrode and the left drain electrode. At the same time, the same electron beam evaporation deposition of the metal stack is carried out on the p-GaN layer on the right side of the isolation groove to fabricate the right gate electrode, so as to form an n-type field effect transistor n-FET on the right side of the isolation groove;

[0028] 10) The p-GaN layer on the left side of the isolation groove is etched by using a low-damage GaN etching technique, and the etching depth is 55 nm - 68 nm, and annealed in an N2 atmosphere at 450 °C - 500 °C to form a gate groove;

[0029] 11) An insulating gate dielectric layer with a thickness of 10 nm - 20 nm is deposited on the gate groove by atomic layer deposition process;

[0030] 12) The Ti / Au metal stack with thicknesses of 20 nm / 100 nm is deposited on the insulating gate dielectric layer by electron beam evaporation process to fabricate the left gate electrode, so as to form a p-type n-type field effect transistor p-FET on the left side of the isolation groove;

[0031] 13) The Ti / Au metal stack is evaporated on the electrodes of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET respectively by electron beam evaporation process to realize the interconnection of these two field effect transistors n-FET and p-FET, and complete the device fabrication.

[0032] Compared with the prior art, the present invention has the following advantages:

[0033] 1. Since an undoped GaN p-channel layer is inserted between the YAlN barrier layer and the p-GaN layer in the present invention, the influence of ionized impurity scattering on carriers can be effectively weakened, the mobility of the two-dimensional hole gas 2DHG can be improved, and the speed of the p-type field effect transistor p-FET can be effectively improved.

[0034] 2. Since YAlN is used as the barrier layer in the present invention, this material belongs to transition metal nitrides and has a strong polarization effect, which can produce various effects:

[0035] First, it can significantly increase the carrier density in the GaN n-channel layer and the p-channel layer, thereby improving the current and power characteristics of the device.

[0036] Second, stress-free epitaxial growth with lattice matching can be achieved by adjusting the alloy composition and GaN. This stress-free growth can not only effectively improve the crystal quality, but also greatly reduce the difficulty of the epitaxial process.

[0037] Thirdly, lattice matching can be achieved between YAlN and GaN, effectively improving the state of the heterointerface, weakening the influence of interface scattering on carriers, increasing the mobility of two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG), and effectively improving the switching characteristics of the device. Description of the Drawings

[0038] Figure 1 is a structural diagram of an existing CMOS device based on a GaN / AlGaN / GaN heterojunction;

[0039] Figure 2 is a structural diagram of a CMOS device based on a GaN / YAlN / GaN heterojunction according to the present invention;

[0040] Figure 3 is a schematic flow diagram of manufacturing a CMOS device based on a GaN / YAlN / GaN heterojunction according to the present invention. Detailed Description of the Invention

[0041] The following further describes the embodiments of the present invention in detail with reference to the drawings.

[0042] Referring to Figure 2 , the CMOS device based on a GaN / YAlN / GaN heterojunction according to the present invention includes, from bottom to top: a substrate 1, a buffer layer 2, a GaN n-type channel layer 3, a barrier layer 4, a GaN p-type channel layer 5, a p-GaN layer 6, and an insulating gate dielectric layer 7. The three layers of the GaN n-type channel layer 3, the barrier layer 4, and the GaN p-type channel layer 5 form a GaN / YAlN / GaN heterojunction; an isolation groove 8 is provided in the middle of the p-GaN layer 6, the GaN p-type channel layer 5, the barrier layer 4, and the GaN n-type channel layer 3, and the depth of the isolation groove 8 reaches the middle of the GaN n-type channel layer 3; a right gate electrode 9 is provided on the p-GaN layer 6 on the right side of the isolation groove 8, and a right source electrode 10 and a right drain electrode 11 are provided at both ends of the barrier layer 4 on the right side of the isolation groove 8 to form an n-type field effect transistor (n-FET); a left gate electrode 12 is provided on the insulating gate dielectric layer 7 on the left side of the isolation groove 8, and a left source electrode 13 and a left drain electrode 14 are provided at both ends of the p-GaN layer 6 on the left side of the isolation groove 8 to form a p-type field effect transistor (p-FET). Among them:

[0043] The substrate 1 is made of <111>-oriented Si;

[0044] The buffer layer 2 is made of GaN material with a thickness of 3 μm - 4.5 μm;

[0045] The GaN n-type channel layer 3 has a thickness of 150 nm - 480 n;

[0046] The barrier layer 4 is made of YAlN material with an Al component of 85%-94% and a thickness of 15nm-30nm to reduce the strain of the barrier layer and enhance the polarization intensity of the barrier layer. It is located on the GaN n-type channel layer 3 on both sides of the isolation groove 8.

[0047] The GaN p-type channel layer 5 has a thickness of 20nm-40nm and is undoped. It is located on the barrier layer 4 on both sides of the isolation groove 8.

[0048] The p-GaN layer 6 has a thickness of 70nm-80nm and a doping concentration of 3×10 19 cm -3 -4×10 19 cm -3 and is located on the GaN p-type channel layer 5 on both sides of the isolation groove 8.

[0049] The insulating gate dielectric layer 7 is made of Al2O3 material with a thickness of 10nm-20nm. It is located on the p-GaN layer 6 on the left side of the isolation groove 8.

[0050] Referring to Figure 3 Three embodiments of the CMOS structure based on the GaN / YAlN / GaN heterojunction and its manufacturing method are given in the present invention.

[0051] Embodiment 1: Fabricate a CMOS device with a GaN buffer layer thickness of 3μm, a GaN n-channel layer thickness of 150nm, a Y 0.15 Al 0.85 N barrier layer thickness of 15nm, a GaN p-channel layer thickness of 20nm, an Al2O3 insulating gate dielectric layer thickness of 10nm, and a p-GaN layer thickness of 70nm with a doping concentration of 3×10 19 cm -3 .

[0052] Step 1: Epitaxially grow a GaN buffer layer, as shown in Figure 3 (a).

[0053] Place the <111>-oriented Si substrate in the MOCVD reaction chamber. Set the temperature of the reaction chamber to 950°C and the pressure to 20 Torr. At the same time, introduce a nitrogen source with a flow rate of 2500 sccm and a gallium source with a flow rate of 20 sccm to grow a GaN buffer layer 2 with a thickness of 3μm on the Si substrate.

[0054] Step 2: Epitaxially grow a GaN n-channel layer, as shown in Figure 3 (b).

[0055] Maintain the temperature of the reaction chamber at 950 °C, maintain the pressure of the reaction chamber at 20 Torr, and then simultaneously introduce a nitrogen source with a flow rate of 2500 sccm and a gallium source with a flow rate of 20 sccm to grow a GaN n-channel layer 3 with a thickness of 150 nm on the GaN buffer layer.

[0056] Step 3, epitaxially grow a YAlN barrier layer, as Figure 3 (c) shows.

[0057] Maintain the temperature of the reaction chamber at 950 °C, maintain the pressure of the reaction chamber at 20 Torr, and then simultaneously introduce a nitrogen source with a flow rate of 2500 sccm, a yttrium source with a flow rate of 60 sccm, and an aluminum source with a flow rate of 300 sccm to grow a Y 0.15 Al 0.85 N barrier layer 4 with a thickness of 15 nm on the GaN n-channel layer.

[0058] Step 4, epitaxially grow a GaN p-channel layer, as Figure 3 (d) shows.

[0059] Maintain the temperature of the reaction chamber at 950 °C, maintain the pressure of the reaction chamber at 20 Torr, and then simultaneously introduce a nitrogen source with a flow rate of 2500 sccm and a gallium source with a flow rate of 20 sccm to grow a GaN p-channel layer 5 with a thickness of 20 nm on the YAlN barrier layer.

[0060] Step 5, epitaxially grow a p-GaN layer, as Figure 3 (e) shows.

[0061] Maintain the temperature of the reaction chamber at 950 °C, maintain the pressure of the reaction chamber at 20 Torr, and then simultaneously introduce a nitrogen source with a flow rate of 2500 sccm, a gallium source with a flow rate of 150 sccm, and a magnesium source with a flow rate of 100 sccm to grow a p-GaN layer 6 with a thickness of 70 nm on the GaN p-channel layer.

[0062] Step 6, dry-etch the p-GaN layer, as Figure 3 (f) shows.

[0063] Use dry etching with Cl2 / BCl3 plasma to selectively etch the p-GaN layer, and control the etching depth from the surface to the interface between the GaN p-type channel layer and the YAlN barrier layer through time.

[0064] Step 7, fabricate the right source electrode and the right drain electrode, as Figure 3 (g) shows.

[0065] Deposit metal on the etched YAlN barrier layer using an electron beam evaporation process. The metal stack is Ti / Al / Ni / Au with thicknesses of 20 nm / 120 nm / 40 nm / 50 nm. Perform rapid thermal annealing for 30 s in an N2 environment at 830 °C to form the right source electrode 10 and the right drain electrode 11.

[0066] Step eight, perform a step etch to form isolation trenches, as Figure 3 (h) shows.

[0067] Use a photolithography mask to define the active regions of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET. Use inductively coupled plasma reactive ion etching based on Cl2 / BCl3 to perform a step etch on the right drain electrode (the left YAlN barrier layer), with an etch depth of 150 nm, to form the isolation trench 8 from the p-GaN layer to the middle of the n-channel layer.

[0068] Step nine, fabricate the left source electrode, the left drain electrode, and the right gate electrode, as Figure 3 (i) shows.

[0069] Deposit Ni / Au metal stacks with thicknesses of 15 nm / 20 nm respectively on the p-GaN layer on the left side of the isolation trench and the p-GaN layer on the right side of the isolation trench using an electron beam evaporation process. After annealing for 5 minutes in an O2 environment at 550 °C, fabricate the left source electrode 13 and the left drain electrode 14 on the p-GaN layer on the left side of the isolation trench, and fabricate the right gate electrode 9 on the p-GaN layer on the right side of the isolation trench.

[0070] Step ten, etch the gate recess, as Figure 3 (j) shows.

[0071] Use a low-damage Cl2 / BCl3 slow etching process to etch the p-GaN on the left side of the isolation trench at an etching rate of 2.4 nm / min and an etch depth of 55 nm. Then treat the surface of the sample with NH3:H2O (1:6) at 55 °C for 5 minutes to remove surface contaminants and residual photoresist, and anneal in an N2 environment at 450 °C for 5 minutes to reduce surface damage caused by etching, obtaining the gate recess.

[0072] Step eleven, deposit the insulating gate dielectric layer, as Figure 3 (k) shows.

[0073] Deposit using atomic layer deposition, and deposit an Al2O3 insulating gate dielectric layer 7 with a thickness of 10 nm on the gate recess.

[0074] Step twelve, fabricate the left gate electrode, as Figure 3 (l) shows.

[0075] Deposit a Ti / Au metal stack with a thickness of 20 nm / 100 nm on the insulating gate dielectric layer by electron beam evaporation process to form the left gate electrode 12.

[0076] So far, a p-type field effect transistor p-FET is formed on the left side of the isolation trench, and an n-type field effect transistor n-FET is formed on the right side of the isolation trench.

[0077] Step thirteen, device interconnection, as Figure 3 (m) shown.

[0078] Deposit a Ti / Au metal stack on the electrodes of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET by electron beam evaporation process to realize the interconnection of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET, and complete the device fabrication.

[0079] Example 2, fabricate a CMOS device with a GaN buffer layer thickness of 4 μm, a GaN n-channel layer thickness of 420 nm, a Y 0.1 Al 0.9 N barrier layer thickness of 25 nm, a GaN p-channel layer thickness of 30 nm, a p-GaN layer thickness of 75 nm and a doping concentration of 3.5×10 19 cm -3 、and an Al2O3 insulating gate dielectric layer thickness of 15 nm.

[0080] Step 1, epitaxially grow a GaN buffer layer, as Figure 3 (a) shown.

[0081] Place the <111>-oriented Si substrate in the MOCVD reaction chamber, set the conditions of the reaction chamber, the temperature is set to 1000 °C, the pressure is set to 40 Torr, and at the same time introduce a nitrogen source with a flow rate of 2800 sccm and a gallium source with a flow rate of 40 sccm into the reaction chamber. Under these process conditions, grow a GaN buffer layer 2 with a thickness of 4 μm on the Si substrate, as Figure 3 (a).

[0082] Step 2, epitaxially grow a GaN n-channel layer, as Figure 3 (b) shown.

[0083] Maintain the reaction chamber temperature at 1000 °C and the reaction chamber pressure at 40 Torr, and then introduce a nitrogen source with a flow rate of 2800 sccm and a gallium source with a flow rate of 40 sccm into the reaction chamber at the same time. Use the MOCVD method to grow a GaN n-channel layer 3 with a thickness of 420 nm on the GaN buffer layer.

[0084] Step 3, epitaxially grow a YAlN barrier layer, as Figure 3 (c) shown.

[0085] Maintain the reaction chamber temperature at 1000 °C and the reaction chamber pressure at 40 Torr. Then, simultaneously introduce a nitrogen source with a flow rate of 2800 sccm, a yttrium source with a flow rate of 40 sccm, and an aluminum source with a flow rate of 320 sccm into the reaction chamber. Use the MOCVD method to grow a Y 0.1 Al 0.9 N barrier layer 4 on the GaN n-channel layer with a thickness of 25 nm.

[0086] Step 4, epitaxially grow the GaN p-channel layer, as shown in Figure 3 (d).

[0087] Maintain the reaction chamber temperature at 1000 °C and the reaction chamber pressure at 40 Torr. Then, simultaneously introduce a nitrogen source with a flow rate of 2800 sccm and a gallium source with a flow rate of 40 sccm into the reaction chamber. Use the MOCVD method to grow a GaN p-channel layer 5 with a thickness of 30 nm on the YAlN barrier layer.

[0088] Step 5, epitaxially grow the p-GaN layer, as shown in Figure 3 (e).

[0089] Maintain the reaction chamber temperature at 1000 °C and the reaction chamber pressure at 40 Torr. Then, simultaneously introduce a nitrogen source with a flow rate of 2800 sccm, a gallium source with a flow rate of 160 sccm, and a magnesium source with a flow rate of 190 sccm into the reaction chamber. Use the MOCVD method to grow a p-GaN layer 6 with a thickness of 75 nm on the GaN p-channel layer.

[0090] Step 6, dry-etch the p-GaN layer, as shown in Figure 3 (f).

[0091] Perform selective etching on the p-GaN layer using dry etching with Cl2 / BCl3 plasma. The etching depth is from the surface to the interface between the GaN p-type channel layer and the YAlN barrier layer.

[0092] Step 7, fabricate the right source electrode and the right drain electrode, as shown in Figure 3 (g).

[0093] Deposit metal on the etched YAlN barrier layer using the electron beam evaporation process. The metal stack is Ti / Al / Ni / Au with a thickness of 20 nm / 120 nm / 40 nm / 50 nm. Perform rapid thermal annealing in an N2 environment at 850 °C for 30 s to form the right source electrode 10 and the right drain electrode 11.

[0094] Step 8, perform step etching to form isolation trenches, as shown in Figure 3 (h).

[0095] A photolithography mask is used to define the active areas of the n-type field-effect transistor (n-FET) and the p-type field-effect transistor (p-FET). The YAlN barrier layer on the left side of the right drain electrode is step-etched using Cl2 / BCl3-based inductively coupled plasma reactive ion etching to a depth of 150 nm to form an isolation trench 8 from the p-GaN layer to the middle of the n-channel layer.

[0096] Step 9, make the left source electrode, the left drain electrode and the right gate electrode, as shown in Figure 3 (i) shown.

[0097] Ni / Au metal stacks with thicknesses of 15 nm / 20 nm are deposited on the p-GaN layer on the left side of the isolation trench and the p-GaN layer on the right side of the isolation trench using an electron beam evaporation process. After annealing in an O2 environment at 550°C for 5 minutes, a left source electrode 13 and a left drain electrode 14 are fabricated on the p-GaN layer on the left side of the isolation trench, and a right gate electrode 9 is fabricated on the p-GaN layer on the right side of the isolation trench.

[0098] Step 10: fabricate an insulating gate dielectric layer and a left gate electrode.

[0099] 10.1) Etch the p-GaN on the left side of the isolation trench using a low-damage Cl2 / BCl3 slow etch process at an etch rate of 2.4 nm / min and an etch depth of 58 nm. The sample is then treated with NH3:H2O (1:6) at 55°C for 5 minutes to remove surface contaminants and residual photoresist. The sample is then annealed at 470°C in a N2 environment for 5 minutes to reduce surface damage caused by etching, resulting in a gate recess. Figure 3 (j) shown.

[0100] 10.2) Deposit a 15 nm thick Al2O3 insulating gate dielectric layer 7 on the gate groove using an atomic layer deposition process. Figure 3 (k) shown.

[0101] 10.3) Using electron beam evaporation, a Ti / Au metal stack with a thickness of 20 nm / 100 nm is deposited on the insulating gate dielectric layer 7 to form the left gate electrode 12, as shown in FIG. Figure 3 (l)

[0102] Thus, a p-type field effect transistor p-FET is formed on the left side of the isolation trench, and an n-type field effect transistor n-FET is formed on the right side of the isolation trench.

[0103] Step 11: Ti / Au metal stack is deposited on the electrodes of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET by electron beam evaporation process to realize the interconnection between the n-type field effect transistor n-FET and the p-type field effect transistor p-FET. Figure 3 As shown in (m), the device fabrication is completed.

[0104] Example 3, fabricate a CMOS device with a GaN buffer layer thickness of 4.5 μm, a GaN n-channel layer thickness of 480 nm, a Y 0.05 Al 0.95 N barrier layer thickness of 30 nm, a GaN p-channel layer thickness of 40 nm, a p-GaN layer thickness of 80 nm and a doping concentration of 4×10 19 cm -3 and an Al2O3 insulating gate dielectric layer thickness of 20 nm.

[0105] Step A, epitaxially grow a GaN buffer layer, as shown in Figure 3 (a).

[0106] Place a <111>-oriented Si substrate in an MOCVD reaction chamber, set the temperature of the reaction chamber to 1300 °C and the pressure to 60 Torr. At the same time, introduce a nitrogen source with a flow rate of 4000 sccm and a gallium source with a flow rate of 50 sccm, and grow a GaN buffer layer 2 with a thickness of 4.5 μm on the Si substrate.

[0107] Step B, epitaxially grow a GaN n-channel layer, as shown in Figure 3 (b).

[0108] Under the process conditions that the temperature of the reaction chamber is maintained at 1300 °C, the pressure of the reaction chamber is maintained at 60 Torr, and a nitrogen source with a flow rate of 4000 sccm and a gallium source with a flow rate of 50 sccm are introduced simultaneously, grow a GaN n-channel layer 3 with a thickness of 480 nm on the GaN buffer layer.

[0109] Step C, epitaxially grow a YAlN barrier layer, as shown in Figure 3 (c).

[0110] Under the process conditions that the temperature of the reaction chamber is maintained at 1300 °C, the pressure of the reaction chamber is maintained at 60 Torr, and a nitrogen source with a flow rate of 4000 sccm, a yttrium source with a flow rate of 30 sccm and an aluminum source with a flow rate of 350 sccm are introduced simultaneously, grow a Y 0.05 Al 0.95 N barrier layer 4 with a thickness of 30 nm on the GaN n-channel layer.

[0111] Step D, epitaxially grow a GaN p-channel layer, as shown in Figure 3 (d).

[0112] Under the process conditions that the temperature of the reaction chamber is maintained at 1300 °C, the pressure of the reaction chamber is maintained at 60 Torr, and a nitrogen source with a flow rate of 4000 sccm and a gallium source with a flow rate of 50 sccm are introduced simultaneously, grow a GaN p-channel layer 5 with a thickness of 40 nm on the YAlN barrier layer.

[0113] Step E, epitaxial growth of p-GaN layer, as shown in Figure 3 (e).

[0114] Under the process conditions of maintaining the reaction chamber temperature at 1300 °C, maintaining the reaction chamber pressure at 60 Torr, and simultaneously introducing a nitrogen source with a flow rate of 3000 sccm, a gallium source with a flow rate of 180 sccm, and a magnesium source with a flow rate of 300 sccm, a p-GaN layer 6 with a thickness of 80 nm is grown on the GaN p-channel layer.

[0115] Step F, dry etching of the p-GaN layer, as shown in Figure 3 (f).

[0116] The p-GaN layer is selectively etched by dry etching with Cl2 / BCl3 plasma, and the etching depth is controlled by time from the surface to the interface between the GaN p-type channel layer and the YAlN barrier layer.

[0117] Step G, fabricating the right source electrode and the right drain electrode, as shown in Figure 3 (g).

[0118] Metal is deposited on the etched YAlN barrier layer by electron beam evaporation process. The metal stack is Ti / Al / Ni / Au with a thickness of 20 nm / 120 nm / 40 nm / 50 nm, and rapid thermal annealing is performed at 900 °C for 30 s in an N2 environment to form the right source electrode 10 and the right drain electrode 11.

[0119] Step H, performing step etching to form isolation trenches, as shown in Figure 3 (h).

[0120] The active regions of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET are defined using a photolithography mask, and step etching is performed on the YAlN barrier layer on the left side of the right drain electrode using inductively coupled plasma reactive ion etching based on Cl2 / BCl3. The etching depth is 150 nm to form isolation trenches 8 from the p-GaN layer to the middle of the n-channel layer.

[0121] Step I, fabricating the left source electrode, the left drain electrode, and the right gate electrode, as shown in Figure 3 (i).

[0122] Ni / Au metal stacks with thicknesses of 15 nm / 20 nm are deposited on the p-GaN layer on the left side of the isolation trench and the p-GaN layer on the right side of the isolation trench by electron beam evaporation process. After annealing in an O2 environment at 550 °C for 5 minutes, the left source electrode 13 and the left drain electrode 14 are fabricated on the p-GaN layer on the left side of the isolation trench, and the right gate electrode 9 is fabricated on the p-GaN layer on the right side of the isolation trench.

[0123] Step J, fabricating the left gate electrode.

[0124] J1) The left side of the isolation trench was etched to a depth of 68 nm in the p-GaN at a rate of 2.4 nm / min using a low-damage Cl2 / BCl3 slow etch process. The etched sample was then treated with NH3:H2O (1:6) at 55°C for 5 minutes to remove surface contaminants and residual photoresist. The sample was then annealed in a N2 environment at 450°C for 5 minutes to reduce surface damage caused by etching, resulting in a gate groove image (see Figure 3(j)).

[0125] J2) Using atomic layer deposition process, deposit Al2O3 insulating gate dielectric layer 7 with a thickness of 20nm on the gate groove, as shown in FIG. Figure 3 (k)

[0126] J3) Using electron beam evaporation technology, a Ti / Au metal stack is deposited on the insulating gate dielectric layer 7 with a thickness of 20nm / 100nm to produce the left gate electrode 12. Figure 3 (l) shown.

[0127] Thus, a p-type field effect transistor p-FET is formed on the left side of the isolation trench, and an n-type field effect transistor n-FET is formed on the right side of the isolation trench.

[0128] Step K, device interconnection, such as Figure 3 (m) shown.

[0129] Ti / Au metal stacks are deposited on the electrodes of the n-type field effect transistor (n-FET) and the p-type field effect transistor (p-FET) using an electron beam evaporation process to achieve interconnection between the n-type field effect transistor (n-FETp) and the p-type field effect transistor (p-FET), completing device fabrication.

[0130] The above descriptions are merely three specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, after understanding the content and principles of the present invention, professionals in this field may make various modifications and changes in form and details without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A CMOS device based on a GaN / YAlN / GaN heterojunction, which includes, from bottom to top: Substrate (1), buffer layer (2), GaN n-channel layer (3), barrier layer (4), p-GaN layer (6), insulating gate dielectric layer (7). An isolation groove (8) is provided between the p-GaN layer (6), the barrier layer (4) and the GaN n-channel layer (3), and the depth of the isolation groove (8) reaches the middle of the GaN n-channel layer (3); a right gate electrode (9) is provided on the p-GaN layer (6) on the right side of the isolation groove (8), and right source electrode (10) and right drain electrode (11) are provided at both ends of the barrier layer (4) on the right side of the isolation groove (8) to form an n-type field effect transistor n-FET; a left gate electrode (12) is provided on the insulating gate dielectric layer (7) on the left side of the isolation groove (8), and left source electrode (13) and left drain electrode (14) are provided at both ends of the p-GaN layer (6) on the left side of the isolation groove (8) to form a p-type field effect transistor p-FET, characterized in that: An undoped GaN p-channel layer (5) with a thickness of 20 nm - 40 nm is additionally provided between the p-GaN layer (6) and the barrier layer (4) on both sides of the isolation groove (8) to improve the carrier mobility; The barrier layer (4) uses a YAlN material with an Al component of 85% - 94% and a thickness of 15 nm - 30 nm to reduce the barrier layer strain and enhance the polarization intensity of the barrier layer.

2. The device according to claim 1, characterized in that: The substrate (1) uses <111>-oriented Si.

3. The device according to claim 1, characterized in that: The buffer layer (2) uses GaN material with a thickness of 3 μm - 4.5 μm.

4. The device according to claim 1, characterized in that: The thickness of the GaN n-channel layer (3) is 150 nm - 480 nm.

5. The device according to claim 1, characterized in that: The p-GaN layer (6) has a thickness of 70 nm - 80 nm and a doping concentration of 3×10 19 cm -3 -4×10 19 cm -3 .

6. The device according to claim 1, characterized in that: The insulating gate dielectric layer (7) uses Al2O3 material with a thickness of 10 nm - 20 nm.

7. A method for fabricating a CMOS device based on a GaN / YAlN / GaN heterojunction, comprising the following steps: 1) On the substrate (1), a buffer layer (2) with a thickness of 3 μm - 4.5 μm is grown by using the MOCVD process; 2) On the buffer layer, a GaN n-channel layer (3) with a thickness of 150 nm - 480 nm is grown by using the MOCVD process; 3) On the GaN n-channel layer, a YAlN barrier layer (4) with an Al component of 85% - 94% and a thickness of 15 nm - 30 nm is grown by using the MOCVD process; 4) On the YAlN barrier layer, an undoped GaN p-channel layer (5) with a thickness of 20 nm - 40 nm is grown by using the MOCVD process; 5) On the GaN p-channel layer, a p-GaN layer (6) with a thickness of 70 nm - 80 nm is grown by using the MOCVD process; 6) The p-GaN layer is selectively dry-etched, and the etching depth is from the surface to the interface between the GaN p-channel layer and the YAlN barrier layer; 7) At both ends of the etched YAlN barrier layer, a metal stack of Ti / Al / Ni / Au with thicknesses of 20 nm / 120 nm / 40 nm / 50 nm in sequence is deposited by using the electron beam evaporation process, and then rapid thermal annealing is performed in an N2 environment at 830 °C - 900 °C to form the right source electrode (10) and the right drain electrode (11); 8) The YAlN barrier layer on the left side of the right drain electrode (11) is subjected to step etching by a plasma reactive ion etching process to form an isolation groove (8) with a depth of 150 nm; 9) A Ni / Au metal stack with thicknesses of 15 nm / 20 nm in sequence is deposited at both ends of the p-GaN layer on the left side of the isolation groove by an electron beam evaporation process and annealed in an O2 environment at 550 °C to form a left source electrode (13) and a left drain electrode (14). At the same time, the same electron beam evaporation metal stack deposition is performed on the p-GaN layer on the right side of the isolation groove to fabricate a right gate electrode (9) to form an n-type field effect transistor n-FET on the right side of the isolation groove; 10) The p-GaN layer on the left side of the isolation groove is etched by a low-damage GaN etching technique with an etching depth of 55 nm - 68 nm and annealed in an N2 atmosphere at 450 °C - 500 °C to form a gate recess; 11) An insulating gate dielectric layer (7) with a thickness of 10 nm - 20 nm is deposited on the gate recess by an atomic layer deposition process; 12) A Ti / Au metal stack with thicknesses of 20 nm / 100 nm in sequence is deposited on the insulating gate dielectric layer by an electron beam evaporation process to fabricate a left gate electrode (12) to form a p-type n-type field effect transistor p-FET on the left side of the isolation groove; 13) A Ti / Au metal stack is evaporated on the electrodes of the n-type field effect transistor n-FET and the p-type field effect transistor p-FET respectively by an electron beam evaporation process to interconnect these two field effect transistors n-FET and p-FET, completing the device fabrication.

8. The method according to claim 7, wherein For the MOCVD process used in step 1), step 2) and step 4), the following condition parameters are set for the reaction chamber: The reaction chamber temperature is 950 - 1300 °C, The reaction chamber pressure is maintained at 20 - 60 Torr, A nitrogen source with a flow rate of 2500 - 4000 sccm and a gallium source with a flow rate of 20 - 50 sccm are simultaneously introduced into the reaction chamber.

9. The method according to claim 7, wherein For the MOCVD process used in step 3), the following condition parameters are set for the reaction chamber: The reaction chamber temperature is 950 - 1300 °C, The reaction chamber pressure is maintained at 20 - 60 Torr, A nitrogen source with a flow rate of 2500 - 4000 sccm, a yttrium source with a flow rate of 30 - 60 sccm and an aluminum source with a flow rate of 280 - 350 sccm are simultaneously introduced into the reaction chamber.

10. The method according to claim 7, characterized in that For the MOCVD process used in step 5), the following condition parameters are set for the reaction chamber: The reaction chamber temperature is 950 - 1300 °C, The reaction chamber pressure is maintained at 20 - 60 Torr, Ammonia with a flow rate of 2500 - 4000 sccm, a gallium source with a flow rate of 150 - 180 sccm and a magnesium source with a flow rate of 100 - 300 sccm are simultaneously introduced into the reaction chamber.

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