Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, including a substrate, a storage node pad, a support structure, a capacitor structure and an insulating filling layer. The storage node pad is arranged on the substrate. The support structure is arranged on the substrate and includes a first support layer and a second support layer arranged in sequence from bottom to top. The capacitor structure is arranged on the substrate and includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer stacked in sequence, wherein the bottom electrode layer includes a first bottom electrode layer with a symmetrical columnar structure and a second bottom electrode layer with an asymmetrical columnar structure, and the first bottom electrode layer and the second bottom electrode layer respectively have at least one horizontal extension portion extending in a horizontal direction, thereby, the bottom electrode layer can be more stably arranged on the support structure to achieve more optimized functions and effects.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor storage device and a manufacturing method thereof. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor storage devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend.

[0003] Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of related storage devices. Summary of the invention

[0004] One of the purposes of the present invention is to provide a method for manufacturing a semiconductor device, which is to pre-form a sacrificial layer on the side wall of each bottom electrode layer. In this way, after the sacrificial layer is subsequently removed, each bottom electrode layer can have a vertical columnar structure that is narrow at the top and wide at the bottom, so as to increase the distance between each bottom electrode layer, which is beneficial to the subsequent deposition manufacturing process of the capacitor dielectric layer and the top electrode layer.

[0005] One object of the present invention is to provide a semiconductor device, wherein the bottom electrode layer includes a first bottom electrode layer having a symmetrical columnar structure and a second bottom electrode layer having an asymmetrical columnar structure, wherein the first bottom electrode layer and the second bottom electrode layer each have at least one horizontal extension extending in a horizontal direction, and can further straddle a capacitor dielectric layer to form a more stable capacitor structure. At the same time, the support structure can also more stably support the capacitor structure, so that the semiconductor device can achieve more optimized functions and effects.

[0006] To achieve the above-mentioned purpose, one embodiment of the present invention provides a semiconductor device including a substrate, a storage node pad, a support structure, a capacitor structure and an insulating filling layer. The storage node pad is arranged on the substrate. The support structure is arranged on the substrate and includes a first support layer and a second support layer arranged in sequence from bottom to top. The capacitor structure is arranged on the substrate and includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer stacked in sequence, wherein the bottom electrode layer includes a first bottom electrode layer having a symmetrical columnar structure, and a second bottom electrode layer having an asymmetrical columnar structure, and the first bottom electrode layer and the second bottom electrode layer respectively have at least one horizontal extension portion extending in a horizontal direction.

[0007] To achieve the above-mentioned purpose, one embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps. First, a substrate is provided, a plurality of storage node pads are formed on the substrate, and a support structure is formed on the substrate, the support structure includes a first support layer and a second support layer arranged in sequence from bottom to top. Then, a capacitor structure is formed on the substrate, the capacitor structure includes a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer stacked in sequence, wherein the bottom electrode layer includes a first bottom electrode layer having a symmetrical columnar structure, and a second bottom electrode layer having an asymmetrical columnar structure, and the first bottom electrode layer and the second bottom electrode layer respectively have at least one horizontal extension portion extending in a horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings provide a deeper understanding of the embodiments of the present invention and are incorporated into this specification and become a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figures 1 to 9 A schematic diagram of the steps of a method for manufacturing a semiconductor device in a first embodiment of the present invention is shown, wherein:

[0010] Figure 1 is a schematic cross-sectional view of the semiconductor device of the present invention after forming a supporting layer structure;

[0011] Figure 2 is a schematic cross-sectional view of the semiconductor device of the present invention after forming a sacrificial material layer;

[0012] Figure 3 is a schematic cross-sectional view of the semiconductor device of the present invention after forming a sacrificial layer;

[0013] Figure 4 is a schematic cross-sectional view of the semiconductor device of the present invention after forming a bottom electrode layer;

[0014] Figure 5 is a schematic cross-sectional view of the semiconductor device of the present invention after forming a mask layer;

[0015] Figure 6 is a schematic cross-sectional view of the semiconductor device of the present invention after the third supporting material layer is removed;

[0016] Figure 7 is a schematic cross-sectional view of the semiconductor device of the present invention after a portion of the sacrificial layer is removed;

[0017] Figure 8 is a schematic cross-sectional view of the semiconductor device of the present invention after the first sacrificial layer is removed; and

[0018] Fig. 9 It is a cross-sectional schematic diagram of the semiconductor device of the present invention after forming a capacitor structure and a support structure. Figures 10 to 12 A schematic diagram of the steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention is shown, wherein:

[0019] Fig.10 is a schematic cross-sectional view of the semiconductor device of the present invention after the sacrificial layer is removed;

[0020] Fig.11 is a cross-sectional schematic diagram of the semiconductor device of the present invention after forming a capacitor structure and a support structure; and

[0021] Fig.12 FIG. 4 is a cross-sectional view of a semiconductor device according to another embodiment after forming a capacitor structure and a support structure.

[0022] Figure 13 to Figure 14 A schematic diagram of the steps of a method for manufacturing a semiconductor device in a third embodiment of the present invention is shown, wherein:

[0023] Fig.13 is a schematic cross-sectional view of the semiconductor device of the present invention after the sacrificial layer is removed;

[0024] Fig.14 is a cross-sectional schematic diagram of the semiconductor device of the present invention after forming a capacitor structure and a support structure; and

[0025] Fig.15 FIG. 4 is a cross-sectional view of a semiconductor device according to another embodiment after forming a capacitor structure and a support structure.

[0026] The reference numerals are described as follows:

[0027] 100, 300, 500 Semiconductor devices

[0028] 101 Shallow Trench Isolation

[0029] 110 Substrate

[0030] 130 Dielectric layer

[0031] 131 Oxide layer

[0032] 133 Nitride layer

[0033] 135 Oxide layer

[0034] 140 Spacer structure

[0035] 141 First spacer

[0036] 143 Second spacer

[0037] 145 The third gap wall

[0038] 150 Contacts

[0039] 160 bit lines

[0040] 160a Bit line contact

[0041] 161 Semiconductor layer

[0042] 163 Barrier Layer

[0043] 165 Conductive layer

[0044] 167 Covering layer

[0045] 170 Dielectric layer

[0046] 180 Storage node pad

[0047] 190 Support layer structure

[0048] 191 first support material layer

[0049] 192 Opening

[0050] 193 Second support material layer

[0051] 195 Third support material layer

[0052] 197 Fourth support material layer

[0053] 200 Sacrificial material layer

[0054] 200a Overhang

[0055] 201 Sacrificial Layer

[0056] 210, 310, 410 capacitor structure

[0057] 211 bottom electrode layer

[0058] 211a, 313a first bottom electrode layer

[0059] 211b, 313b second bottom electrode layer

[0060] 212 Concave Corner

[0061] 212a, 312 horizontal extension

[0062] 213, 313, 313a, 413 capacitor dielectric layer

[0063] 215, 315 top electrode layer

[0064] 220 Mask pattern

[0065] 290 Support structure

[0066] 291 First Support Layer

[0067] 293 Second support layer

[0068] 304 Air gap

[0069] 501, 501a, 501b, 501c, 501d sacrificial layer

[0070] 501f, 501g, 501h Sacrificial layer

[0071] 504, 506 air gap

[0072] 510 Capacitor Structure

[0073] 511 Bottom electrode layer

[0074] 511a, 511b side wall

[0075] 513, 513a, 513b capacitor dielectric layer

[0076] 515 Top electrode layer

[0077] 520 Mask Pattern

[0078] 590 Support structure

[0079] 591 First Support Layer

[0080] 593 Second Support Layer

[0081] D1 Aperture

[0082] T1 Thickness

[0083] P1 First Etching Process

[0084] P2 Second Etching Process

[0085] P3 The third etching process

[0086] P4, P41 Fourth Etching Process

[0087] P5 Fifth Etching Process DETAILED DESCRIPTION

[0088] In order to enable those skilled in the art to further understand the present invention, the following lists the preferred embodiments of the present invention, and with the accompanying drawings, describes in detail the components and intended effects of the present invention. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0089] Please refer to Figures 1 to 9 , which is a schematic diagram of the steps of the method for manufacturing the semiconductor device 100 in the first embodiment of the present invention. First, Figure 1 As shown, a substrate 110 is provided, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.) or a silicon-on-insulator (SOI) substrate, etc., and at least one insulating region is formed in the substrate 110, such as a shallow trench isolation (STI) 101, and a plurality of active areas (AA, not shown) are defined on the substrate 110, and the shallow trench isolation 101 surrounds all of the active areas. In one embodiment, the formation of the insulating region 101 is, for example, firstly forming a plurality of trenches (not shown) in the substrate 110 by etching, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride, etc.), but the present invention is not limited thereto.

[0090] In addition, a plurality of buried gates (not shown) may be formed in the substrate 110. The buried gates extend in parallel along a direction (e.g., the x direction, not shown) and intersect with the active region and the shallow trench isolation 101 to serve as buried word lines (BWL, not shown) of the semiconductor device 100. A plurality of bit lines 160 and a plurality of contacts 150 may be formed on the substrate 110. The bit lines 160 extend in another direction (e.g., the y direction, not shown) perpendicular to the direction and are arranged alternately. Although the overall extending direction of the active region, the buried gates and the bit lines 160 is not specifically shown in the drawings of the present embodiment, a person skilled in the art should be able to easily understand that the bit lines 160 should be perpendicular to the buried gates and intersect with the active region and the buried gates when viewed from a top view.

[0091] Specifically, each bit line 160 is formed on the substrate 110 in a mutually separated manner and includes a semiconductor layer (e.g., including polysilicon) 161, a barrier layer 163 (e.g., including titanium and / or titanium nitride), a conductive layer 165 (e.g., including a low-resistance metal such as tungsten, aluminum or copper), and a cap layer 167 (e.g., including silicon oxide, silicon nitride or silicon oxynitride, etc.) stacked in sequence, but not limited thereto. It should be noted that, in principle, all bit lines 160 are formed in parallel to each other on the dielectric layer 130 above the substrate 110, wherein the dielectric layer 130 preferably has a composite layer structure, such as an oxide layer 131-nitride layer 133-oxide layer 135 (oxide-nitride-oxide, ONO) structure, but not limited thereto. In addition, each bit line 160 extends and intersects with the plurality of active regions at the same time, wherein the bit line 160 falling on each active region further extends into each active region through a bit line contact (BLC) 160a formed correspondingly thereunder. Each bit line contact 160a is, for example, formed integrally with the semiconductor layer 161 of the bit line 160 and directly contacts the substrate 110 (each active region) thereunder.

[0092] On the other hand, each contact 150 is also formed on the substrate 110 in a spaced manner and further extends into each active region. Thus, each contact 150 can be used as a storage node contact (SNC) of the semiconductor device 300 and directly contact the substrate 110 (including the active region and the shallow trench isolation 101) below. In one embodiment, the contact 150 includes a metal material with a low resistance value, such as aluminum (Al), titanium (Ti), copper (Cu) or tungsten (W), and each contact 150 is insulated from each bit line 160 through a spacer structure 140. In one embodiment, the spacer structure 140 can selectively have a single-layer structure or a plurality of layers. Figure 1 The composite layer structure shown includes, for example, a first spacer 141 (eg, comprising silicon nitride), a second spacer 143 (eg, comprising silicon oxide), and a third spacer 145 (eg, comprising silicon nitride) sequentially stacked on the sidewalls of each bit line 160 , but is not limited thereto.

[0093] Please refer to Figure 1As shown, a plurality of storage node pads (SN pads) 180 are formed in the dielectric layer 170 on the substrate 110, which are located above the contacts 150 and the bit lines 160 and are respectively located opposite to each contact 150. In one embodiment, the storage node pads 180 also include a low-resistance metal material such as aluminum, titanium, copper or tungsten, for example, a metal material different from the contact 150, but not limited thereto. In another embodiment, the storage node pads can also be integrally formed with the contact 150 and can include the same material. Subsequently, a capacitor structure 210 can be further formed above the storage node pads 180 to directly contact and electrically connect the storage node pads 180 below. In one embodiment, the manufacturing process of the capacitor structure 210 includes but is not limited to the following steps. First, a support layer structure 190 is formed on the dielectric layer 170 above the substrate 110, which, for example, includes at least one oxide layer and at least one nitride layer alternately stacked. In the present embodiment, the support layer structure 190 includes, for example, a first support material layer 191 (for example, including silicon oxide), a second support material layer 193 (for example, including silicon nitride or silicon carbonitride), a third support material layer 195 (for example, including silicon oxide) and a fourth support material layer 197 (for example, including silicon nitride or silicon carbonitride, etc.), which are stacked in sequence from bottom to top, but are not limited thereto. Preferably, the oxide layer (for example, including the first support material layer 191 and the third support material layer 195) may have a relatively large thickness, for example, about 5 to 10 times or more of the thickness of the nitride layer (for example, including the second support material layer 193 or the fourth support material layer 197), and the thickness of the nitride layer (for example, the fourth support material layer 197) disposed away from the substrate 110 is preferably greater than the thickness of the nitride layer (for example, the second support material layer 193) disposed adjacent to the substrate, such as Figure 1 As shown, but not limited to this. Thus, the overall thickness of the support layer structure 190 can be about 1600 angstroms to 2000 angstroms, but not limited to this. Those skilled in the art should understand that the specific stacking number of the aforementioned oxide layer (such as the first support material layer 191 or the third support material layer 195) and the aforementioned nitride layer (such as the second support material layer 193 or the fourth support material layer 197) is not limited to the aforementioned number, but can be adjusted according to actual needs, such as 3 layers, 4 layers or other numbers. Then, a plurality of openings 192 are formed in the support layer structure 190, which sequentially penetrate the fourth support material layer 197, the third support material layer 195, the second support material layer 193 and the first support material layer 191, and correspond to each storage node pad 180 located below. In this way, the top surface of each storage node pad 180 can be exposed from each opening 192, as shown in FIG. Figure 1 shown.

[0094] Then, if Figure 2 As shown, a deposition process with poor step coverage is performed on the substrate 110 to form a sacrificial material layer 200. Specifically, the sacrificial material layer 200 includes, for example, a general dielectric material such as silicon oxide, silicon nitride or silicon oxynitride, and conformally covers the surface of the opening 192. However, since the opening 192 has a high aspect ratio, the sacrificial material layer 200 can only partially cover the sidewall of the upper half of the opening 192. At the same time, an overhang 200a is formed on the top of the opening 192 to produce a sealing phenomenon. It should be noted that the coverage area of ​​the sacrificial material layer 200 on the surface of each opening 192 can be further adjusted with various parameters of the deposition process (such as deposition temperature, flow field or material selection). In this embodiment, the sacrificial material layer 200, for example, covers the junction between the third support material layer 195 and the second support material layer 193, but is not limited thereto. In addition, although in the present embodiment, the coverage area of ​​the sacrificial material layer 200 on the surface of each opening 192 is substantially the same as an implementation mode for description, those skilled in the art should understand that in the actual process, the aforementioned parameters can also be selectively controlled so that the sacrificial material layer can have different coverage areas on the surface of each opening 192 (not shown).

[0095] Then, if Figure 3 As shown, a first etching process P1 is performed, such as a dry etching process, to partially remove the sacrificial material layer 200 and the overhanging portion 200a, to form a sacrificial layer 201 that only covers the two opposite sidewalls of the opening 192. The top surface of the sacrificial layer 201 is preferably lower than the top surface of the fourth supporting material layer 197, for example, it can be flush with the bottom surface of the fourth supporting material layer 197 to ensure that each opening 192 can be completely opened, such as Figure 3 As shown. Due to the poor step coverage of the deposition process, the sacrificial layer 201 covering the surface of each opening 192 has a gradually decreasing thickness in its lower half, while its upper half has a uniform thickness T1. The thickness T1 can also be further adjusted with the various parameters of the aforementioned deposition process (such as deposition temperature, flow field or material selection, etc.). In the present embodiment, the thickness T1 of the sacrificial layer 201 is, for example, approximately one-fifth to one-tenth of the aperture D1 of the opening 192, but is not limited thereto. In addition, in another embodiment, the aforementioned parameters can also be selectively controlled so that the upper half of the sacrificial layer disposed on the surface of each opening 192 has a different uniform thickness (not shown).

[0096] like Figure 4As shown, deposition and back etching processes are sequentially performed on the substrate 110 to form a plurality of bottom electrode layers 211, which respectively fill the remaining space of each opening 192 and directly contact each storage node pad 180 below. In this way, the sacrificial layer 201 formed in the aforementioned steps can be located on the two opposite side walls of the upper half of each bottom electrode layer 211, and between each bottom electrode layer 211 and the third supporting material layer 195 of the supporting layer structure 190. For this reason, each bottom electrode layer 211 can generally have a vertical columnar structure that is narrow at the top and wide at the bottom, and symmetrical on the left and right, but is not limited thereto. In one embodiment, the bottom electrode layer 211 includes, for example, a metal material with a low resistance value such as aluminum, titanium, copper or tungsten, preferably including titanium, but not limited thereto.

[0097] Then, if Figure 5 As shown, a plurality of mask patterns 220 are formed on the substrate 110, covering a portion of the fourth support material layer 197 and a portion of the bottom electrode layer 211, and a second etching process P2 is performed through the mask patterns 220, such as another dry etching process. Specifically, each mask pattern 220 is sequentially formed on the support layer structure 190 in a manner of simultaneously covering any bottom electrode layer 211 and the support layer structure 190 on both sides thereof, and partially exposing two bottom electrode layers 211 adjacent to the left and right sides of any bottom electrode layer 211, covering a portion of the fourth support material layer 197 and a portion of the bottom electrode layer 211, and exposing the remaining portion of the fourth support material layer 197 and the remaining portion of the bottom electrode layer 211. Thus, the second etching process P2 is performed through the mask pattern 220 to completely remove the remaining fourth support material layer 197, exposing the third support material layer 195 below, and partially remove the remaining bottom electrode layer 211 until its top surface is lower than the top surface of the fourth support material layer 197. In this operation, a concave corner 212 can be etched out of the top of the remaining bottom electrode layer 211, such as Figure 5 shown.

[0098] Then, if Figure 6 As shown, a third etching process P3 is performed through the mask pattern 220, such as an isotropic wet etching process, so as to completely remove the third support material layer 195 of the support layer structure 190 under the cover of each mask pattern 220. In detail, the isotropic wet etching process is to introduce an etchant such as tetramethylammonium hydroxide (TMAH) to first remove the third support material layer 195 exposed from the mask pattern 220 until the second support material layer 193 below and the sacrificial layer 201 on both sides are exposed, and then continue to remove the remaining third support material layer 195 on both sides, but it is not limited to the aforementioned etchant. In this operation, at least the sidewall of one side of each sacrificial layer 201 can be completely exposed, such as Figure 6 Then, as Figure 7 As shown, a fourth etching process P4 is performed through the mask pattern 220 , such as another isotropic wet etching process, in which an etchant such as tetramethylammonium hydroxide is introduced to further remove the sacrificial layer 201 from the exposed sidewalls of each sacrificial layer 201 .

[0099] like Figure 8 As shown, the fifth etching process P5 is performed through the mask pattern 220, for example, another isotropic wet etching process, and an etchant such as tetramethylammonium hydroxide is also introduced to first remove the exposed second support material layer 193 and the first support material layer 191 thereunder, until the top surface of the dielectric layer 170 is exposed, and then the remaining first support material layer 191 is removed from both sides, but the etchant is not limited to the aforementioned etchant. Under this operation, the two opposite side walls of each bottom electrode layer 211 can be substantially exposed, and the remaining second support material layer 193 and the remaining fourth support material layer 197 respectively form the first support layer 291 and the second support layer 293 arranged in sequence from bottom to top, and the first support layer 291 and the second support layer 293 are at least arranged on one side of each bottom electrode layer 211 to jointly form a support structure 290 supporting the bottom electrode layer 211. Preferably, the thickness of the second support layer 293 located away from the substrate 110 may be greater than the thickness of the first support layer 291 located near the substrate, for example, about 2 to 5 times the thickness of the first support layer 291. Figure 8 As shown, but not limited to.

[0100] Affected by the sacrificial layer 201, the upper half of each bottom electrode layer 211 may partially have a relatively small diameter, for example, smaller than the aperture D1 of the opening 192, and the lower half may have a relatively large diameter, for example, equal to the aperture D1 of the opening 192, so that each bottom electrode layer 211 may generally present a vertical columnar structure that is narrow at the top and wide at the bottom, such as Figure 8As shown, but not limited thereto. In this embodiment, the portion of each bottom electrode layer 211 between the first support layer 291 and the second support layer 293 in the vertical direction (for example, in the direction perpendicular to the substrate 110) is defined as the upper half; and the portion of each bottom electrode layer 211 between the first support layer 291 and the storage node pad 180 in the vertical direction is defined as the lower half, but not limited thereto. It should be noted that, in this embodiment, the bottom electrode layer 211 includes a first bottom electrode layer 211a having a symmetrical columnar structure, and a second bottom electrode layer 211b having an asymmetrical columnar structure, and the top of the second bottom electrode layer 211b also has a concave corner 212, which can further present a left-right asymmetrical structure. In addition, it should be particularly noted that the upper half of each bottom electrode layer 211 (including the first bottom electrode layer 211a and the second bottom electrode layer 211b) further includes at least one horizontal extension portion 212a extending in a horizontal direction (for example, in a direction parallel to the substrate 110), the bottom of which is flush with the bottom of the second support layer 293. Figure 8 As shown, the first bottom electrode layer 211a has two horizontal extensions 212a extending in two opposite directions, thus presenting a symmetrical columnar structure; and each second bottom electrode layer 211b has a horizontal extension 212a extending toward the left or right side, thus presenting an asymmetrical columnar structure, so that the distance between each bottom electrode layer 211 and the adjacent bottom electrode layer 211 can be further increased to facilitate the subsequent deposition process.

[0101] Then, if Fig. 9As shown, the mask pattern 220 is completely removed, and a deposition process is performed on the substrate 110 to sequentially form a capacitor dielectric layer 213 and a top electrode layer 215. In this way, the bottom electrode layer 211 (including the first bottom electrode layer 211a and the second bottom electrode layer 211b), the capacitor dielectric layer 213 and the top electrode layer 215 can together form a capacitor structure 210. In detail, the capacitor dielectric layer 213 conformally covers the exposed surfaces of the bottom electrode layer 211 and the dielectric layer 170, and the top electrode layer 215 fills the remaining space between the bottom electrode layers 211, and a portion of the capacitor dielectric layer 213 and the top electrode layer 215 can further fill between the second support layer 293 and the first support layer 291, and further fill between the first support layer 291 and the dielectric layer 170, so that the capacitor dielectric layer 213 can directly contact the bottom of the horizontal extension portion 212a. In other words, each horizontal extension 212a of the bottom electrode layer 211 can be arranged across a portion of the capacitor dielectric layer 213, thereby forming a capacitor structure 210 with a more stable structure. In one embodiment, the capacitor dielectric layer 213, for example, includes a high dielectric constant dielectric material, which is selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), titanium oxide (TiO2) and zirconium oxide-aluminum oxide-zirconium oxide (ZAZ), preferably including zirconium oxide-aluminum oxide-zirconium oxide; the top electrode layer 215, for example, includes a low resistance metal material such as aluminum, titanium, copper or tungsten, preferably including titanium, but not limited thereto.

[0102] In this way, the manufacturing process of the capacitor structure 210 is completed. The capacitor structure 210 includes a plurality of capacitors extending vertically to serve as storage nodes (SN) of the semiconductor device 100. The storage nodes can be electrically connected to the transistor components (not shown) of the semiconductor device 100 through the storage node pads 180 and the storage node plugs (i.e., the contacts 150), so that the capacitor structure 210 and the storage node plugs disposed on the substrate 110 can have a good contact relationship. In this way, the semiconductor device 100 of this embodiment can form a dynamic random access memory (DRAM) device, which is composed of at least one transistor component and at least one capacitor to form the smallest component unit (memory cell) in the dynamic random access memory array to receive voltage information from the bit line 160 and the buried word line.

[0103] According to the manufacturing method of the first embodiment of the present invention, the semiconductor device 100 is firstly fabricated by using a deposition process with poor step coverage (such as Figure 2 As shown) and the first etching process P1 (as shown Figure 3 ), forming a sacrificial layer 201 covering only the two opposite sidewalls of the opening 192, so that each bottom electrode layer 211 formed subsequently can have a vertical columnar structure with a narrow top and a wide bottom, so as to initially increase the distance between each bottom electrode layer 211. Then, when removing the third support material layer 195 of the support layer structure 190 (as shown in FIG. Figures 5 and 6 As shown in FIG. 2 ), a concave corner 212 is further formed on the top of a portion of the bottom electrode layer 211 through the mask pattern 220, thereby making the second bottom electrode layer 211b present a left-right asymmetric structure, so as to additionally increase the distance between the second bottom electrode layer 211b and the adjacent bottom electrode layer 211 (including the first bottom electrode layer 211a and the second bottom electrode layer 211b), so as to facilitate the subsequent deposition process of the capacitor dielectric layer 213 and the top electrode layer 215. Therefore, under this operation, the manufacturing method of the semiconductor device 100 in the first embodiment of the present invention can effectively improve the manufacturing defects derived from the increase in the density of the memory cell, so that the capacitor dielectric layer 213 and the top electrode layer 215 formed subsequently can be more evenly and flatly covered on each bottom electrode layer 211, thereby improving its structural reliability, so as to achieve more optimized functions and effects. It should be noted that the first bottom electrode layer 211a has two horizontal extensions 212a extending in two opposite directions respectively; and each second bottom electrode layer 211b has a horizontal extension 212a extending toward the left or right side, and each horizontal extension 212a can be arranged across a portion of the capacitor dielectric layer 213, thereby forming a more stable capacitor structure 210. Here, the support structure 290 can more stably support both sides of the capacitor structure 210, thereby improving the structural reliability of the semiconductor device 100.

[0104] In addition, those skilled in the art should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device and its manufacturing method of the present invention may also have other aspects, not limited to the above. For example, in another embodiment, the various parameters of the deposition process may be adjusted to directly form Figure 3 The sacrificial layer 201 shown in FIG. Figure 2 The overhanging portion 200a shown in the figure can thus omit the first etching process P1. The following will further describe other embodiments or variations of the method for the semiconductor device of the present invention. In order to simplify the description, the following description mainly describes the differences between the embodiments, and does not repeat the same parts. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0105] Please refer to Figures 10 to 12, which is a schematic diagram of the steps of the method for manufacturing the semiconductor device 300 in the second embodiment of the present invention. The steps of forming the front end of the semiconductor device 300 in this embodiment are substantially the same as the steps of forming the front end of the semiconductor device 100 in the first embodiment. Figures 1 to 6 The main difference between this embodiment and the first embodiment is that in this embodiment, the top surface of the sacrificial layer (not shown) is between the top surface and the bottom surface of the fourth supporting material layer 197, so when the sacrificial layer (not shown) is completely removed later, Figure 7 After the fourth etching process P4 shown in FIG. 1 , an air gap 304 can be formed between each bottom electrode layer 211 and the fourth supporting material layer 197. Fig.10 As shown. Subsequently, the fifth etching process P5 is continued on the substrate 110 to completely remove the mask pattern 220, so that the remaining second support material layer 193 and the remaining fourth support material layer 197 can together form the support structure 290. In this way, the upper half of each bottom electrode layer (including the first bottom electrode layer 311a and the second bottom electrode layer 311b) of this embodiment also includes at least one horizontal extension portion 312 extending in a horizontal direction (for example, in a direction parallel to the substrate 110), the bottom of which is higher than the bottom of the second support layer 293 and between the bottom and the top of the second support layer 293, as shown in FIG. 10. Similarly, the first bottom electrode layer 311a has two horizontal extension portions 312 extending in two opposite directions, thereby presenting a symmetrical columnar structure; and each second bottom electrode layer 311b has a horizontal extension portion 312 extending toward the left side or the right side, thereby presenting an asymmetrical columnar structure. In this way, the distance between each bottom electrode layer 311 and the adjacent bottom electrode layer 311 can be further increased to facilitate the subsequent deposition manufacturing process.

[0106] Then, Fig.11As shown, a capacitor dielectric layer 313 and a top electrode layer 315 are sequentially formed on each bottom electrode layer 311. In this way, the bottom electrode layer 311, the capacitor dielectric layer 313 and the top electrode layer 315 can form a capacitor structure 310 together, wherein the material selection and specific manufacturing process of the capacitor dielectric layer 313 and / or the top electrode layer 315 of this embodiment are the same as those of the capacitor dielectric layer 213 and / or the top electrode layer 215 of the first embodiment, and are not repeated here. It should be noted that in this embodiment, various parameters of the deposition manufacturing process (such as deposition temperature, flow field or material selection, etc.) are selectively adjusted so that part of the capacitor dielectric layer 313a can completely fill the air gap 304 between each bottom electrode layer 311 and the second support layer 293. The capacitor dielectric layers 313 and 313a may also include high dielectric constant dielectric materials such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zinc oxide, titanium oxide, or zirconium oxide-aluminum oxide-zirconium oxide, which may be filled between each bottom electrode layer 311 and the second support layer 293 to more stably support the capacitor structure 310. However, in another embodiment, the subsequently deposited capacitor dielectric layer 413 may not be filled into the air gap 304 between each bottom electrode layer 211 and the second support layer 293. In this way, after the capacitor structure 410 is formed, the air gap 304a may still be maintained between each bottom electrode layer 211 and the second support layer 293, such as Fig.12 shown.

[0107] Thus, the manufacturing process of the capacitor structure 310 / 410 is completed. The capacitor structure 310 / 410 includes a plurality of capacitors extending vertically to serve as storage nodes of the semiconductor device 300, which can be electrically connected to the transistor components (not shown) of the semiconductor device 300 through the storage node pad 180 and the storage node plug (i.e., the contact 150), so that the capacitor structure 310 / 410 and the storage node plug disposed on the substrate 110 can have a good contact relationship. Thus, the semiconductor device 300 of this embodiment can also form a dynamic random access memory device.

[0108] According to the manufacturing method of this embodiment, the top surface height of the sacrificial layer is adjusted in the etching process P41 (such as Fig.10As shown in the figure, an air gap 304 is formed between each bottom electrode layer 311 and the fourth supporting material layer 197. To this end, the capacitor dielectric layer 313 or the capacitor dielectric layer 413 deposited subsequently can selectively completely fill or not fill each air gap 304. Therefore, in the capacitor structure 310 / 410 formed subsequently, a portion of the capacitor dielectric layer 313 or the air gap 304 can be further sandwiched between each bottom electrode layer 312 (including the first bottom electrode layer 311a and the second bottom electrode layer 311b) and the second supporting layer 293, which is located below the horizontal extension portion 312, and can also stably support the capacitor structure 310 / 410 while improving the structural reliability and device performance of the semiconductor device 300.

[0109] Please refer to Figure 13 to Figure 14 , which is a schematic diagram of the steps of manufacturing a semiconductor device 500 in the third embodiment of the present invention. The steps of forming the front end of the semiconductor device 500 in this embodiment are substantially the same as the steps of forming the semiconductor devices 100 and 300 in the aforementioned embodiments, and the same or similar parts are not repeated here. The main difference between the present embodiment and the aforementioned embodiment is that, in the present embodiment, the thickness and coverage area of ​​each sacrificial layer 501 on the surface of each opening 192 are different by adjusting various parameters of the deposition process. For example, part of the sacrificial layers 501a, 501b, 501c may only cover part of the third supporting material layer 195, another part of the sacrificial layers 501d, 501e may further cover the boundary between the second supporting material layer 193 and the first supporting material layer 191, and another part of the sacrificial layers 501f, 501g may further cover part of the first supporting material layer 191, but not limited thereto; and another part of the sacrificial layers 501e, 501h may have a thickness T2 that is uniform as a whole but less than the thickness T1, and another part of the sacrificial layers 501c, 501d may have a thickness T3 that is uniform as a whole but greater than the thickness T1, such as Fig.14 Furthermore, in another embodiment, the sacrificial layers 501b and 501g may have an overall non-uniform film thickness, such as Fig.14 shown.

[0110] Next, a bottom electrode layer 511 (as described in the first embodiment) is formed. Figure 4 As shown), the mask pattern 520 (as shown in the first embodiment) Figure 5 ), and sequentially remove a portion of the fourth support material layer 197 and a portion of the bottom electrode layer 511 (as shown in the first embodiment above) under the cover of the mask pattern 520. Figure 5 ), removing the third support material layer 195 (as shown in the first embodiment above) Figure 6 ), removing the sacrificial layer 501 (as shown in the first embodiment above) Figure 7As shown), and removing part of the second support material layer 193 and the first support material layer 191, forming Fig.14 The bottom electrode layer 511, the first support layer 591 (i.e., the remaining second support material layer 193) and the second support layer 593 (i.e., the remaining fourth support material layer 197) are shown, wherein the first support layer 591 and the second support layer 593 may together form a support structure 590, and an air gap 504 may be further formed between each bottom electrode layer 511 and the second support layer 593. It should be noted that, in response to the structural state of each sacrificial layer 501, each bottom electrode layer 511 of the present embodiment may have two mutually asymmetric opposite side walls 511a, 511b, particularly referring to the side wall of the upper half of each bottom electrode layer 511 (e.g., the portion between the first support layer 591 and the second support layer 593 in the direction perpendicular to the substrate 110), which may have, for example, an overall flat or irregular surface, an overall uniform or non-uniform depression, different depression degrees, different extension lengths, etc. Wherein, one side wall 511a of a portion of the bottom electrode layer 511 may extend between the first support layer 591 and the second support layer 593 in the direction perpendicular to the substrate 110, and the other side wall 511b may extend below the first support layer 591, and may selectively have an overall flat or irregular surface, such as Fig.14 As shown, each bottom electrode layer 511 of this embodiment can present a more diversified asymmetric structure as a whole.

[0111] Then, if Fig.15As shown, the mask pattern 520 is completely removed, and a capacitor dielectric layer 513 and a top electrode layer 515 are sequentially formed on each bottom electrode layer 511. In this way, the bottom electrode layer 511, the capacitor dielectric layer 513 and the top electrode layer 515 can form a capacitor structure 510 together, wherein the material selection and specific manufacturing process of the capacitor dielectric layer 513 and / or the top electrode layer 515 of this embodiment are the same as those of the capacitor dielectric layer 213 and / or the top electrode layer 215 of the first embodiment, and are not repeated here. It should be noted that in this embodiment, various parameters of the deposition manufacturing process (such as deposition temperature, flow field or material selection, etc.) are selectively adjusted, so that part of the capacitor dielectric layer 513a can completely fill the air gap 504 between each bottom electrode layer 511 and the second support layer 593, and part of the capacitor dielectric layer 513b can completely fill the air gap 506 between each bottom electrode layer 511 and the first support layer 591. The capacitor dielectric layers 513, 513a, 513b may also include high dielectric constant dielectric materials such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zinc oxide, titanium oxide, or zirconium oxide-aluminum oxide-zirconium oxide, which may be filled between each bottom electrode layer 511 and the second support layer 593 to more stably support the capacitor structure 510. However, in another embodiment, the subsequently deposited capacitor dielectric layer 513 may not be filled into the air gap 504 between each bottom electrode layer 511 and the second support layer 593.

[0112] In this way, the manufacturing process of the capacitor structure 510 is completed. The capacitor structure 510 includes a plurality of capacitors extending vertically to serve as storage nodes of the semiconductor device 500, which can be electrically connected to the transistor components (not shown) of the semiconductor device 500 through the storage node pads 180 and the storage node plugs (i.e., contacts 150), so that there can be a good contact relationship between the capacitor structure 510 and the storage node plugs disposed on the substrate 110. In this way, the semiconductor device 500 of this embodiment can also form a dynamic random access memory device.

[0113] According to the manufacturing method of this embodiment, by adjusting various parameters when forming the sacrificial layer 501, each sacrificial layer 501 can have different lengths, thicknesses, or overall non-uniform film thicknesses (such as Fig.14 As shown in FIG. 5 , each bottom electrode layer 511 formed subsequently can present a more diversified asymmetric structure as a whole, so as to further increase the distance between adjacent bottom electrode layers 511, which is beneficial to the subsequent deposition process of the capacitor dielectric layer 513 and the top electrode layer 515. In addition, the bottom electrode layer 511 of this embodiment can be more stably disposed on the support structure 590, thereby improving the structural reliability and device performance of the semiconductor device 500.

[0114] In general, the present invention first utilizes a deposition process with poor step coverage and an etching process to preliminarily form a sacrificial layer in the opening of the support layer structure, so that each bottom electrode layer formed subsequently can have a vertical columnar structure that is narrow at the top and wide at the bottom, so as to initially widen the distance between each bottom electrode layer. Then, in the process of removing the support layer structure, a concave angle is further formed on the top of a portion of the bottom electrode layer through a mask pattern to further widen the distance between each bottom electrode layer, so as to facilitate the subsequent deposition process of the capacitor dielectric layer and the top electrode layer. Therefore, the manufacturing method of the present invention can effectively improve the manufacturing defects derived from the increase in the density of the storage unit, so that the capacitor dielectric layer and the top electrode layer can be more evenly and flatly covered on the bottom electrode layer, thereby improving its structural reliability, so that the semiconductor device of the present invention can achieve more optimized functions and effects.

[0115] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that include: substrate; A plurality of storage node pads are arranged on the substrate; A support structure is arranged on the substrate, wherein the support structure comprises a first support layer and a second support layer arranged in sequence from bottom to top; as well as A capacitor structure is arranged on the substrate, and the capacitor structure includes a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer stacked in sequence, wherein the bottom electrode layer includes a first bottom electrode layer with a symmetrical columnar structure, and a second bottom electrode layer with an asymmetrical columnar structure, the first bottom electrode layer and the second bottom electrode layer respectively have at least one horizontal extension portion extending in a horizontal direction, wherein the side wall of at least one of the horizontal extension portions is flush with the side wall of the bottom electrode layer located between the substrate and the first supporting layer, and the top of the second bottom electrode layer has a concave angle.

2. The semiconductor device according to claim 1, wherein: The bottom surface of the at least one horizontal extension portion is flush with the bottom surface of the second supporting layer.

3. The semiconductor device according to claim 2, wherein: The bottom surface of the at least one horizontal extension portion directly contacts the capacitor dielectric layer.

4. The semiconductor device according to claim 1, wherein: Part of the capacitor dielectric layer is sandwiched between the second supporting layer and the bottom electrode layer.

5. The semiconductor device according to claim 4, wherein: The portion of the capacitor dielectric layer is located below the at least one horizontal extension portion.

6. The semiconductor device according to claim 4, wherein: The capacitor dielectric layer includes a high dielectric constant dielectric material.

7. The semiconductor device according to claim 1, wherein: The air gap is sandwiched between the second supporting layer and each of the bottom electrode layers, and the air gap is located below the at least one horizontal extension portion.

8. A method for manufacturing a semiconductor device, characterized in that Include: providing a substrate; forming a plurality of storage node pads on the substrate; forming a support structure on the substrate, the support structure comprising a first support layer and a second support layer arranged in sequence from bottom to top; as well as A capacitor structure is formed on the substrate, wherein the capacitor structure includes a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer stacked in sequence, wherein the bottom electrode layer includes a first bottom electrode layer with a symmetrical columnar structure, and a second bottom electrode layer with an asymmetrical columnar structure, the first bottom electrode layer and the second bottom electrode layer respectively have at least one horizontal extension portion extending in a horizontal direction, wherein the side wall of at least one of the horizontal extension portions is flush with the side wall of the bottom electrode layer located between the substrate and the first supporting layer, and the top of the second bottom electrode layer has a concave angle.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The forming of the support structure further comprises: forming a support layer structure on the substrate, wherein the support layer structure comprises a first support material layer, a second support material layer, a third support material layer and a fourth support material layer sequentially stacked on the substrate; forming a plurality of openings in the support layer structure; forming a mask pattern on the support layer structure; removing a portion of the fourth supporting material layer in the supporting layer structure and removing the third supporting material layer through the mask pattern; removing a portion of the second supporting material layer through the mask pattern, and removing the first supporting material layer in the supporting layer structure; and The mask pattern is completely removed to form the support structure.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: Also includes: forming a sacrificial material layer to cover a portion of the surface of each of the openings and to seal each of the openings; as well as An etching process is performed to partially remove the sacrificial material layer to form a sacrificial layer on two opposite side walls of each opening.

11. The semiconductor device according to claim 10, wherein: The thickness of the sacrificial layer is one fifth to one tenth of the aperture of the opening.

12. The semiconductor device according to claim 10, wherein: The sacrificial layer is formed between each of the bottom electrode layers and the supporting layer structure.

13. The method for manufacturing a semiconductor device according to claim 10, wherein: Also includes: After the fourth supporting material layer and the third supporting material layer are removed, removing the sacrificial layer; as well as After the sacrificial layer is removed, the capacitor dielectric layer is formed.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: After the capacitor dielectric layer is formed, an air gap is formed between each of the bottom electrode layers and the second supporting layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: After the capacitor dielectric layer is formed, a portion of the capacitor dielectric layer is sandwiched between the second support layer and the bottom electrode layer, and is located below the at least one horizontal extension portion.

Images