Three-dimensional memory, methods of making three-dimensional memory, and memory systems

Abstract

The application provides a three-dimensional memory, a preparation method of the three-dimensional memory and a memory system. The preparation method comprises the following steps: forming a stack layer on a substrate and forming a plurality of channel structures penetrating through the stack layer and extending into the substrate, the stack layer comprising a core region and a transition region adjacent to the core region, the plurality of channel structures comprising a first channel structure located in the core region and a second channel structure located in the transition region, and the substrate comprising a base and a stop layer located between the base and the stack layer; removing the base; forming a protective layer on a side of the stop layer away from the stack layer, the protective layer covering at least the second channel structure in a direction parallel to the stop layer; and removing the protective layer after removing a portion of the stop layer corresponding to the core region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology. Specifically, the present application relates to a three-dimensional memory, a method for manufacturing a three-dimensional memory, and a memory system. BACKGROUND

[0002] NAND devices with planar structures have reached the limit of practical expansion. In order to further increase storage capacity and reduce the cost of storage per bit, 3D NAND memory devices have been proposed. A 3D NAND generally includes a core region for storing data. A staircase region with a staircase shape is usually provided on both sides of the core region or before two core regions for leading out word lines. The core region and the staircase region can be divided into a plurality of block regions by a gate line gap structure.

[0003] Taking a 3D NAND with 128 layers as an example, in a region (hereinafter referred to as a transition region) that transitions from the core region to the staircase region, since 9 rows of channel structures located in the core region transition to 3 rows of dummy channel structures located in the staircase region, there is a large stress difference in the transition region, which can easily cause the gate line gap etched in the transition region to be inclined. Therefore, a transition channel structure is usually provided in the transition region to improve the above-mentioned stress difference by providing structural support.

[0004] It should be appreciated that the background section is intended to provide useful background information for understanding the technology and does not necessarily constitute an acknowledgement or any form of suggestion that any of the preceding material constitutes prior art. SUMMARY

[0005] One aspect of the present application provides a method for manufacturing a three-dimensional memory, comprising: forming a stack layer on a substrate and forming a plurality of channel structures through the stack layer and extending into the substrate, the stack layer comprising a core region and a transition region adjacent to the core region, the plurality of channel structures comprising first channel structures located in the core region and second channel structures located in the transition region, the substrate comprising a base and a stop layer located between the base and the stack layer; removing the base; forming a protection layer on a side of the stop layer facing away from the stack layer, the protection layer covering at least the second channel structures in a direction parallel to the stop layer; and after removing a portion of the stop layer corresponding to the core region, removing the protection layer.

[0006] In one embodiment of the present application, the first channel structures extend into the stop layer and comprise a first functional layer and a first channel layer arranged from outside to inside, the method further comprising: removing a portion of the first functional layer extending into the stop layer; and forming a semiconductor layer in contact with the first channel layer on a portion of the stop layer corresponding to the transition region.

[0007] In one embodiment of the present application, removing the portion of the first functional layer extending into the stop layer comprises: removing a portion of the first functional layer extending into the stop layer in the process of removing the protective layer; and removing a remaining portion of the first functional layer extending into the stop layer after removing the protective layer.

[0008] In one embodiment of the present application, removing the portion of the first functional layer extending into the stop layer comprises: removing a portion of the first functional layer extending into the stop layer in the process of removing the protective layer; and removing a remaining portion of the first functional layer extending into the stop layer after removing the protective layer.

[0009] In one embodiment of the present application, the second channel structure extends through the stop layer and into the substrate, and comprises a second functional layer and a second channel layer arranged from outside to inside; wherein the method further comprises: removing a portion of the second functional layer extending into the substrate to expose the second channel layer; and wherein forming the protective layer on a side of the stop layer facing away from the stack layer to cover at least the second channel structure in a direction parallel to the stop layer comprises: forming the protective layer on the portion of the stop layer corresponding to the transition region and on the exposed second channel layer.

[0010] In one embodiment of the present application, forming the semiconductor layer in contact with the first channel layer on the portion of the stop layer corresponding to the transition region comprises: forming the semiconductor layer in contact with the first channel layer and the second channel layer on the portion of the stop layer corresponding to the transition region.

[0011] In one embodiment of the present application, the substrate comprises a substrate and a first insulating layer between the substrate and the stop layer, wherein removing the substrate comprises: removing the substrate; and removing the first insulating layer.

[0012] In one embodiment of the present application, the second channel structure extends through the first insulating layer and into the substrate, and the method further comprises: removing a portion of the second functional layer extending into the substrate at the same time as removing the substrate; and removing a portion of the second functional layer extending into the first insulating layer at the same time as removing the first insulating layer.

[0013] In one embodiment of the present application, the method further comprises: forming a second insulating layer on the stop layer before forming the stack layer; and removing a portion of the second insulating layer corresponding to the core region after removing the portion of the stop layer corresponding to the core region.

[0014] Another aspect of the present application provides a three-dimensional memory, comprising: a semiconductor layer; a stack structure on the semiconductor layer and comprising a core region and a transition region adjoining the core region; a stop layer between the stack structure and the semiconductor layer at least in the transition region; and a plurality of channel structures, comprising: a plurality of first channel structures passing through the stack structure in the core region and comprising a first channel layer extending into the semiconductor layer. In one embodiment of the present application, the plurality of channel structures further comprises: at least one second channel structure passing through the stack structure in the transition region and the stop layer and comprising a second channel layer extending into the semiconductor layer.

[0015] In one embodiment of the present application, the plurality of channel structures further comprises: at least one third channel structure passing through the stack structure in the transition region and extending into the stop layer.

[0016] In one embodiment of the present application, in an extension direction of the channel structures, a size of the first channel layer is greater than a size of the second channel layer.

[0017] In one embodiment of the present application, in a direction parallel to the semiconductor layer, a size of the first channel structure is greater than a size of the second channel structure.

[0018] In one embodiment of the present application, wherein the semiconductor layer has a convex surface in a radial direction toward the channel structures, the stop layer has a concave surface in contact with and matching the convex surface.

[0019] In one embodiment of the present application, the stop layer comprises polysilicon, and the semiconductor layer comprises one of N-type doped polysilicon, metal, or metal nitride.

[0020] In one embodiment of the present application, the stop layer comprises polysilicon, and the semiconductor layer comprises one of N-type doped polysilicon, metal, or metal nitride.

[0021] Still another aspect of the present application provides a memory system, comprising: the three-dimensional memory of any one of the above, the three-dimensional memory being configured to store data; and a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0022] In one embodiment of the present application, the memory system comprises: a solid state drive or a memory card. BRIEF DESCRIPTION OF DRAWINGS

[0023] Other features, objects, and advantages of the application will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. In the drawings,

[0024] Figure 1 Flowchart of a method of fabricating a three-dimensional memory in accordance with some embodiments of the application;

[0025] Figures 2 to 13 Schematic diagram of a semiconductor structure formed after certain steps of a method of fabricating a three-dimensional memory in accordance with some embodiments of the application;

[0026] Figure 14 Schematic diagram of a structure of a three-dimensional memory in accordance with some embodiments of the application;

[0027] Figure 15 Schematic diagram of a structure of a three-dimensional memory in accordance with some embodiments of the application;

[0028] Figure 16 Block diagram of an exemplary system including a memory in accordance with some embodiments of the application;

[0029] Figure 17 Schematic diagram of an exemplary memory card having a memory in accordance with some embodiments of the application;

[0030] Figure 18 Schematic diagram of an exemplary solid state drive (SSD) having a memory in accordance with some embodiments of the application;

[0031] Figure 19 Schematic diagram of a memory including a peripheral circuit and a memory array in accordance with some embodiments of the application. DETAILED DESCRIPTION

[0032] For a better understanding of the present application, various aspects of the application will now be described in greater detail. It is noted that these detailed descriptions are merely descriptive of some exemplary embodiments of the application and are not intended in any way to limit the scope of the application. Throughout the specification, like drawing reference numerals will be understood to refer to like parts throughout the specification and the drawings.

[0033] It is noted that the recitations of “one embodiment,” “an embodiment,” “some embodiments,” “one implementation,” “an implementation,” “some implementations,” etc., indicate that the embodiment(s) so described can include a particular feature, structure, or characteristic, but not every embodiment need necessarily include the particular feature, structure, or characteristic. Further, repeated use of the phrases “some embodiments” or “one embodiment” does not necessarily refer to the same embodiments, although it may. Moreover, the description of a particular feature, structure, or characteristic as an “implementation” does not imply that the implementation cannot be implemented in other embodiments.

[0034] Generally, terminology can be understood at least in part from the context of usage. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in the singular or can be used to describe combinations of features, structures or characteristics. Similarly, terms such as "a," "an," or "the" again can be understood to convey a singular usage or to convey a plural usage, at least in part depending upon context. In addition, the term "based on" can be understood as not necessarily requiring exclusively factual derivations and instead can allow for approximation, based at least in part on assumptions, potential changes, etc., as can be appreciated at least by those having ordinary skill in the art.

[0035] It will be readily appreciated that the terms "on," "over," and "above," in the present disclosure, are to be interpreted in the broadest context possible so that "on" means not only "directly on" but also includes the meaning of "on" with intervening features or layers therebetween, and "over" or "above" means not only "over" or "above" but also can include the meaning of "over" or "above" with no intervening features or layers therebetween (i.e., directly on).

[0036] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can likewise be interpreted accordingly.

[0037] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire upper or lower stracture or can have a smaller extent than the underlying or overlying stracture. In addition, a layer can be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any pair of horizontal planes between or at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers.

[0038] In the drawings, the thicknesses of components, sizes, and the like, are exaggerated for clarity. The drawings are not drawn strictly to scale. For example, the terms "approximately," "about," and the like, as used herein, are used as terms of approximation and not as terms of degree, unless expressly stated otherwise, and are meant to allow for a reasonable amount of deviation based on experimental error, measurement of values, or variations in calculations.

[0039] It should also be understood that the terms "comprises", "comprising", "includes", "including", "has", "having" and the like, when used in this specification, specify the presence of stated features, elements and / or components but do not preclude the presence or addition of one or more other features, elements, components and / or groups thereof. Furthermore, as used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, expressions such as "at least one of... ", when preceding a list of two or more items, denote that at least one of each item in the list is present and that no more than one of each item is present.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0041] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other, as long as there is no conflict. In addition, unless specifically limited, the steps of the methods described in the present application can be performed in any order or in parallel, unless otherwise specified or contradicted by context. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0042] It should be understood that, in describing the embodiments of the present application, the cross-sectional view of the device structure is partially enlarged for the convenience of illustration, and the cross-sectional view is only a schematic structural view for describing some steps and components of the present application and the relationship between the components, which should not limit the scope of protection of the present application.

[0043] The framework of the three-dimensional memory is generally formed by bonding a storage array and a peripheral circuit. The preparation method of the three-dimensional memory provided by some embodiments of the present application includes forming a first semiconductor structure for the storage array and forming a second semiconductor structure for the peripheral circuit, and some operations after bonding the first semiconductor structure and the second semiconductor structure. Figure 1A flow chart of a method of fabricating a three-dimensional memory according to some embodiments of the present application, Figures 2 to 13 A partial view of a semiconductor structure formed after performing some steps of a method of fabricating a three-dimensional memory according to some embodiments of the present application. The following will be described in conjunction with Figures 2 to 13 The fabrication method 300 will be described in detail.

[0044] Referring to Figure 1 , the method 300 includes an operation S310 of forming a stack layer on a substrate and forming a plurality of channel structures through the stack layer and extending into the substrate. As shown in Figure 2 , a first semiconductor structure 400( Figure 4 ) is formed as an example, a first insulating layer 402 and a stop layer 403 are sequentially formed on a substrate 401, and a stack layer 440 is formed on the stop layer 403. For the convenience of subsequent description, the substrate 401 and the first insulating layer 402 can be collectively referred to as a base. Alternatively, the substrate 401, the first insulating layer 402, and the stop layer 403 can be collectively referred to as a substrate (for example, a first substrate 410). Alternatively, the stop layer 403 can be located between the first insulating layer 402 and the stack layer 440. Alternatively, the substrate 401 can have a relatively thick thickness compared with the stop layer 403 and the first insulating layer 402, so that the substrate 401 can serve as a stress support for a device structure (for example, the stack layer 440) formed thereon and be removed in subsequent processes.

[0045] In some examples, the first insulating layer 402 and the stop layer 403 can be sequentially formed on the substrate 401 by a thin film formation process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, thermal oxidation, or any combination thereof.

[0046] Alternatively, the material for the substrate 401 can include silicon (for example, single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. Alternatively, the stop layer 403 includes, for example, polycrystalline silicon.

[0047] Continuing to refer to Figure 2 , in some examples, before forming the stack layer 440, a second insulating layer (for example, silicon oxide) 404 and a polycrystalline silicon layer 405 can also be sequentially formed on the first substrate 410 by a suitable thin film deposition process. Alternatively, the second insulating layer 104 and the polycrystalline silicon layer 105 can be partially removed in subsequent processes, and a structure as shown in Figure 14The semiconductor layer 410' is shown. Optionally, the stop layer 403 can have a relatively thicker thickness compared to the first insulating layer 402, the second insulating layer 404 and the polysilicon layer 405, such that a deep hole etching process performed in the stack layer 440 can stop at the stop layer 403.

[0048] In some examples, the stack layer 440 can be formed by alternately stacking a plurality of dielectric layers 415 and sacrificial layers 416' on the polysilicon layer 405 through a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The number of stacked layers of the dielectric layers 415 and the sacrificial layers 416' in the stack layer 440 can be, for example, 8 layers, 32 layers, 64 layers, 128 layers or more. The number of stacked layers of the dielectric layers 415 and the sacrificial layers 416' is not limited in the present disclosure. Optionally, the material for the dielectric layers 415 can include, for example, silicon oxide, and the material for the sacrificial layers 416' can include, for example, silicon nitride.

[0049] Referring to Figure 3 In some examples, the stack layer 440 can include a step region B1 and a core region B3, and a transition region B2 between the step region B1 and the core region B3. Optionally, the transition region B2 can be adjacent to the core region B3. Optionally, the stack layer 440 can further include a peripheral region B4 located at a side of the step region B1 facing away from the transition region B2. Illustratively, the steps of forming the first semiconductor structure 400 further include forming a plurality of channel structures through the stack layer 440 and extending to the first substrate 410 in the transition region B2 and the core region B3. For ease of description, the plurality of channel structures through the stack layer 440 in the core region B3 can be referred to as first channel structures 430, and the channel structures through the stack layer 440 in the transition region B2 can be referred to as second channel structures 420 (also referred to as "transition channel structures"). In some examples, a plurality of channel holes (not shown) can be formed in the stack layer 440 through a lithography and etching process such as a dry or wet etching process. For ease of description, the channel holes formed in the core region B3 can be referred to as first channel holes, and the channel holes formed in the transition region B2 can be referred to as second channel holes. Illustratively, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be employed to form, in order from outside to inside, a first blocking layer 431, a first storage layer 432 and a first tunneling layer 433 and a first channel layer 434 in the inner wall of the first channel hole. Optionally, the first blocking layer 431, the first storage layer 432 and the first tunneling layer 433 can constitute a first functional layer. Illustratively, a dielectric material such as silicon oxide can be filled in the first channel hole formed with the first functional layer and the first channel layer 434 to form a first dielectric core 435.

[0050] By way of example, the same deposition process as that for forming the first functional layer and the first channel layer 434 can be employed to form the second functional layer consisting of the second blocking layer 421, the second storage layer 422 and the second tunneling layer 423, and the second channel layer 424 in sequence from outside to inside on the inner wall of the second channel hole. By way of example, a dielectric material such as silicon oxide can be filled in the second channel hole formed with the second functional layer and the second channel layer 424 to form the second dielectric core 425.

[0051] Optionally, the material for the first blocking layer 431 and the second blocking layer 421 can include silicon oxide, silicon oxynitride, high dielectric or any combination thereof, for example. The material for the first storage layer 432 and the second storage layer 422 can include silicon nitride, silicon oxynitride, silicon or any combination thereof, for example. The material for the first tunneling layer 433 and the second tunneling layer 423 can include silicon oxide, silicon oxynitride or any combination thereof, for example. In one example, the first functional layer and the second functional layer can be a composite layer including silicon oxide / silicon oxynitride / silicon oxide (ONO), for example.

[0052] The stop layer 403 described above can be used as a stop layer for the first channel structure 430 and the second channel structure 420 to extend, for example, i.e. the first channel structure 430 and the second channel structure 420 can extend into the stop layer 403. In order to provide a good stress support, the size D2 of the second channel structure 420 is generally greater than the size D1 of the first channel structure 430 in the same horizontal direction parallel to the first substrate 410. In the same horizontal direction parallel to the first substrate 410, in order to make the size of the second channel hole etched in the transition region B2 greater than the size of the first channel hole etched in the core region B3, the etching rate for the transition region B2 can be made higher than the etching rate for the core region B3; or the etching time for the transition region B2 can be made longer than the etching time for the core region B3. Either of the above operations can easily lead to over-etching of the first channel hole in the transition region B2.

[0053] Continuing to refer to Figure 3 By way of example, the first substrate 401 and the stop layer 403 both including polysilicon, the first channel hole formed in the transition region B2 is easy to pass through the stop layer 403 and the first insulating layer 402 and extend into the first substrate 401 due to the relatively thin thickness of the first insulating layer 402.

[0054] It should be understood that Figure 3 By way of example, the core region B3 includes two first channel structures 430, in actual processes and structures, the core region B3 can include more than two first channel structures 430.

[0055] In some examples, as Figure 3One of the two second trench structures 420 shown can extend into the substrate 401, i.e., over-etching occurs; the other second trench structure 420 can stop at the stop layer 403. The second trench structures 420 that stop at the stop layer 403 can serve as an example of the third trench structures in the three-dimensional memory 600 described below. In other examples, all of the second trench structures 420 can extend into the substrate 401, which can serve as another example of the third trench structures in the three-dimensional memory 600 described below. In some cases, some of the second trench structures 420 also extend into the stop layer 403, which can serve as yet another example of the third trench structures in the three-dimensional memory 600 described below.

[0056] With continued reference to Figure 3 In some examples, a step structure can also be formed in the step region B1. Illustratively, the step structure can be formed by performing multiple "etch-trim" processes on the alternating stack of the plurality of dielectric layers 415 and the plurality of sacrificial layers 416'. Optionally, each level of the step structure includes at least one dielectric layer / sacrificial layer pair.

[0057] With reference to Figure 4 The steps of forming the first semiconductor structure 400 further include forming a fill layer 411 on the step structure by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The surface of the fill layer 411 away from the surface of the first substrate 410 can be planar, thereby providing a substantially planar surface for the stack layer 440. Optionally, the material for the fill layer 411 includes an insulating material such as silicon oxide.

[0058] In some examples, the steps of forming the first semiconductor structure 400 further include forming a gate line gap structure (not shown) in the stack layer 440. Illustratively, the gate line gap structure can be formed by forming a gate line gap (not shown) in the stack layer 440 by a dry etching or wet etching process, and then sequentially forming an insulating layer (not shown) and a conductor layer (not shown) in the gate line gap by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0059] In some examples, after the gate line gap is formed, a sacrificial layer 416' can be removed via the gate line gap using a wet etching process, for example, and a sacrificial space filling conductive material formed after the sacrificial layer 416' is removed to form a conductive layer 416 Figure 4 ). Optionally, the sacrificial layer 416' and the dielectric layer 415 can have a high etching selectivity, such that the dielectric layer 415 is hardly removed in the process of removing the sacrificial layer 416'.

[0060] Optionally, the conductive layer 416 can be used as a control gate to lead out a word line (not shown), for example. In some examples, the material used for the conductive layer 416 can include a metallic conductive material such as W, Co, Cu, Al, Ti, Ta, Ni, etc. In some examples, the material used for the dielectric layer 415 can also include a semiconductor material such as polysilicon, doped silicon, metal silicide (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof.

[0061] With continued reference to Figure 4 In some examples, the conductive layer 416 and the dielectric layer 415 can extend from the core region B3 to the step region B1 and stop at a location where the step region B1 is adjacent to the peripheral region B4 in a direction parallel to the first substrate 410. Exemplarily, a peripheral contact 412 can be formed in the peripheral region B4, which passes through the fill layer 411, the polysilicon layer 405, and the second oxide layer 404 in sequence and extends into the stop layer 403. The peripheral contact 412 can be used to electrically connect the opposite two surfaces of the first semiconductor structure 400 in a subsequent process. Optionally, the material used for the peripheral contact 412 can include a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof, etc.

[0062] In some examples, forming the first semiconductor structure 400 further includes forming a contact structure 413 in the step region B1, which can pass through the fill layer 411 and contact each of the conductive layers 416. Optionally, the contact structure 413 can be used to electrically connect a word line to be led out and the second semiconductor structure 200 described below. Optionally, the material used for the contact structure 413 can include a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof, etc.

[0063] In some examples, forming the first semiconductor structure 400 further includes forming a dummy channel structure (not shown) in the step region B1, which can pass through the fill layer 411 and extend into the stop layer 403. In some cases, the dummy channel structure can provide structural support for the step structure. Optionally, the material used for the dummy channel structure can include an insulating material such as silicon oxide, etc. In some cases, the dummy channel structure can have the same internal structure as the first channel structure 430 and the second channel structure 420. Optionally, during the process of forming a dummy channel hole for the dummy channel structure, over-etching can also occur for the dummy channel hole, i.e., the dummy channel hole can pass through the stop layer 403 and extend into the substrate 401, so that the formed dummy channel structure extends into the substrate 401.

[0064] In some examples, forming the first semiconductor structure 400 further includes forming a first interconnect layer 414 on a side of the stack layer 440 facing away from the first substrate 410. Illustratively, the first interconnect layer 414 can include first interconnect lines 417 disposed parallel or substantially parallel to the first substrate 410. Optionally, the first interconnect layer 414 can further include first interconnect contacts 418 disposed perpendicular or substantially perpendicular to the first substrate 410 and in contact with the first interconnect lines 417. Optionally, the peripheral contacts 412, the contact structures 413, and the channel layers of the channel structures can be electrically connected to the first interconnect lines 417 by disposing metal contacts. Optionally, the above-mentioned structures electrically connected to the first interconnect lines 417 can be electrically connected to other semiconductor structures (e.g., a "second semiconductor structure" hereinafter) by the first interconnect contacts 418. Optionally, the materials for the first interconnect lines 417 and the first interconnect contacts 418 include, for example, electrically conductive materials such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0065] With continued reference to Figure 4 In some embodiments, the second semiconductor structure 200 can be used to form a peripheral circuit. Illustratively, forming the second semiconductor structure 200 includes forming a peripheral circuit structure 240 on a second substrate 210 different from the first substrate 410 and forming a second interconnect layer 214 on a side of the peripheral circuit structure 240 facing away from the second substrate 210.

[0066] During operation of the three-dimensional memory, the peripheral circuit structure 240 can be configured to control and sense the three-dimensional memory. In some examples, the peripheral circuit structure 240 can include, for example, high-voltage devices for controlling high-voltage signals and / or low-voltage devices for improving read / write speed. Optionally, the above-mentioned high-voltage devices and / or low-voltage devices are composed of, for example, MOS transistors (not shown).

[0067] In some examples, illustratively, the second interconnect layer 214 can include second interconnect lines 217 disposed parallel or substantially parallel to the first substrate 410. Optionally, the second interconnect layer 214 can further include second interconnect contacts 218 disposed perpendicular or substantially perpendicular to the first substrate 410 and in contact with the second interconnect lines 217. Illustratively, the first semiconductor structure 400 can be face-to-face hybrid bonded with the second semiconductor structure 200, and the second interconnect contacts 218 can be in corresponding contact with the first interconnect contacts 418 at a bonding interface, thereby electrically connecting the first semiconductor structure 400 with the second semiconductor structure 200. During operation of the three-dimensional memory, the control of the storage array by the peripheral circuit can be achieved by the electrical connection of the storage array (the first semiconductor structure 400) with the peripheral circuit (the second semiconductor structure 200).

[0068] Figures 5 to 7FIG. 1 shows a partial schematic view of a semiconductor device formed by some operations of a method of fabricating a three-dimensional memory in some embodiments after bonding a first semiconductor structure with a second semiconductor structure.

[0069] Reference is made to Figure 5 Exemplarily, a backside process can be performed on the first semiconductor structure 400, such as forming a semiconductor layer (e.g., a semiconductor layer 410' as shown) on a side of the first semiconductor structure 400 facing away from the second semiconductor structure 200, which can serve as a common source layer and electrically connect the channel layers (e.g., the first channel layer 434 and the second channel layer 424) of the first and second channel structures. Figure 7

[0070] Continuing to refer to Figure 5 In an example where the at least one second channel structure 420 extends to the substrate 401, the substrate 401, the first insulating layer 402 and the stop layer 403 can be sequentially removed. In the process of removing the stop layer 403, a portion of the second channel layer 424 along the extension direction of the second channel structure 420 can be removed at the same time, so that a void 429 appears in the second channel structure 420. Optionally, the void 429 can extend to a position close to the conductive layer 416 (e.g., serving as a bottom select gate layer). Referring to Figure 6 In the process of etching the first functional layer of the first channel structure 430 by, for example, a dry etching process, the etching material (e.g., etching liquid or etching gas) can enter the void 429 and remove at least the portion of the second functional layer corresponding to the void, so that a defect space exposing the conductive layer 416 is formed in the second channel structure 420. Referring to Figure 7 In an example where the semiconductor layer 410' for electrical connection described above is formed, the semiconductor layer 410' can fill the defect space and thus contact the adjacent conductive layer 416 (e.g., serving as a bottom select gate layer), which brings the risk of word line leakage.

[0071] In some examples where the step region B1 includes a dummy channel structure, in the process of removing the stop layer 403 and removing the portion of the second functional layer extending into the substrate 401, the corresponding etching material can remove a portion of the dummy channel structure extending to the substrate 401 along the extension direction of the dummy channel structure, thus forming a gap or a hole in the portion close to the conductive layer 416. In the subsequent process of forming the semiconductor layer 410', the semiconductor material can fill in these gaps or holes, which can cause short-circuit leakage between the adjacent conductive layers 416 or between the semiconductor layer 410' and the conductive layer, affecting the performance and yield of the three-dimensional memory.

[0072] Figures 8 to 13 ​FIG. 3 shows a partial schematic view of a semiconductor device formed by another operation of the method of fabricating a three-dimensional memory according to some embodiments of the present application after bonding the first semiconductor structure and the second semiconductor structure.

[0073] Returning to Figure 1 Method 300 continues to operation S320, removing the substrate. In some examples, substrate 401 and first insulating layer 402 can be sequentially removed as the substrate. Referring to Figure 8 In some examples, an etching process (e.g., a dry or wet etching process), a chemical mechanical polishing (CMP) process, or any combination thereof can be employed to remove substrate 401 from the side of first substrate 410 facing away from stack 440. In some examples, substrate 401 and first insulating layer 402 can be sequentially removed by, for example, a wet etching process.

[0074] In examples where substrate 401 is removed by an etching process, first insulating layer 402 can act as an etching stop layer for etching 401. After the above process, first insulating layer 402 and the portion of second channel structure 420 extending into substrate 401 can be exposed.

[0075] In other examples, at least one of the kind, proportion, or temperature of the material used for etching can be adjusted such that the etching selectivity difference between substrate 401 and the second functional layer is relatively small, so that the portion of the second functional layer extending into substrate 401 is removed at the same time as substrate 401 is removed.

[0076] In examples where second channel layer 424 extends into substrate 401, at least one of the kind, proportion, or temperature of the material used for etching can be adjusted such that the second functional layer has a higher etching selectivity than second channel layer 424, so that the portion of second channel layer 424 extending into substrate 401 will not be removed during the removal of the portion of the second functional layer extending into substrate 401.

[0077] For example, a dry or wet etching process can be employed to remove first insulating layer 402. For example, a dry etching process can be employed, in which at least one of the kind, proportion, or temperature of the etching gas is adjusted such that the portion of the second functional layer extending into first insulating layer 402 is removed at the same time as first insulating layer 402 is removed. For example, the etching process to remove first insulating layer 402 can stop at the surface of stop layer 403 facing away from stack 440.

[0078] Referring to Figure 9In the process of removing the first insulating layer 402 and the portion of the second functional layer extending into the first insulating layer 402 using, for example, a dry etching process, at least one of the kind, proportion, and temperature of the etching gas can be adjusted so that the first functional layer has a higher etching selectivity with the second channel layer, so that the portion of the second channel layer 424 extending into the first insulating layer 402 and the substrate 401 will not be removed. After the above process, the stop layer 403 can be exposed and the second channel layer 424 can be exposed on the side of the stop layer 403 facing away from the stack layer 440( Figure 4 ) of the substrate 401.

[0079] In the example in which the step region B1 includes a dummy channel structure, the process of removing the portion of the second functional layer extending into the substrate 401 and the first insulating layer 402 can cause a portion of the dummy channel structure along its extension direction to be removed at the same time.

[0080] Referring to Figure 1 , the method continues to operation S330, a protective layer covering at least the second channel structure in a direction parallel to the stop layer can be formed on the side of the stop layer facing away from the stack layer. In some embodiments, as shown in Figure 10 , the protective layer 450 can be formed on the side of the stop layer 403 facing away from the stack layer 440( Figure 4 ) by a photolithography process and an etching process (e.g., a dry etching process or a wet etching process). The protective layer 450 can be located on the stop layer 403 and the second channel structure 420 of the transition region B2, for example. Optionally, the protective layer 450 can cover the exposed portion of the second channel layer 424 and the exposed bottom of the second functional layer in a direction parallel or substantially parallel to the first substrate 410 and the stop layer 403. Optionally, the protective layer 450 can also surround the sidewall of the exposed portion of the second channel layer 424 in a direction perpendicular or substantially perpendicular to the stop layer 403, for example.

[0081] In some examples, the protective layer 450 can also cover the dummy channel structure located in the step region B1 in a direction parallel or substantially parallel to the first substrate 410.

[0082] Referring to Figure 11 , in some examples, the protective layer 450 can also cover a portion of the stop layer 403 located in the core region B3 and expose the first channel structure 430 in a direction parallel or substantially parallel to the stop layer 403.

[0083] In some embodiments, the material for the protection layer 450 can include photoresist, and can be formed using, for example, a spin-on process. Alternatively, in the example where an etching process is used to remove a portion of the stop layer 403, the protection layer 450 can also be made of a material that has a high etching selectivity with the stop layer 403 to be partially removed, so that the etching rate of the protection layer 450 is low (e.g., much lower than the etching rate of the stop layer 403). As an option, the protection layer 450 can be silicon oxide or silicon nitride, and the stop layer 403 can be polysilicon.

[0084] Returning to Figure 1 , the method proceeds to operation S350, where the protection layer 450 can be removed after removing the portion of the stop layer 403 corresponding to the core region B3. In some embodiments, as shown in FIG. 4B, the protection layer 450 can be used as a mask to remove the portion of the stop layer 403 that is not covered by the protection layer 450. For example, a portion of the stop layer 403 located in the core region B3 can be removed by, for example, a dry, wet, or plasma etching process, and a portion of the first channel structure 430 extending to the stop layer 403 can be exposed. For example, the etching process to remove the portion of the stop layer 403 located in the core region B3 can stop at the surface of the second insulating layer 404 facing away from the stack 440. Figure 11

[0085] According to embodiments of the present disclosure, the protection layer 450 covering the second channel structure 420 is formed before the step of removing the portion of the stop layer 403 located in the core region B3, which can protect the second functional layer 424 from being damaged during the process of removing the portion of the stop layer 403 located in the core region B3, and reduce the generation of pores 429, thereby reducing the risk of etching the second functional layer by etching gas via the pores 429, and reducing the generation of defect spaces, which can facilitate reducing the risk of electrical leakage caused by the contact between the semiconductor layer 410' formed subsequently and the conductive layer 416.

[0086] Alternatively, in the example where the protection layer 450 covers the dummy channel structure located in the step region B1, the protection layer 450 can reduce the damage to the dummy channel structure caused by, for example, the subsequent process of removing the portion of the stop layer 403 located in the core region B3, and reduce the generation of cracks and holes.

[0087] In the example where the protection layer 450 extends to the core region B3, the portion of the stop layer 403 located in the core region B3 and under the protection layer 450 can be partially retained during the process of removing the portion of the stop layer 403 located in the core region B3 using, for example, a plasma etching process. Referring to Figure 11 Due to the blocking effect of the protection layer 450, the retained stop layer 403 in the core region B3 can form a concave surface that is recessed towards the radial direction of the first channel structure 420.​

[0088] In an example where a portion of the stop layer 403 located in the core region B3 is removed by, for example, gas etching or wet etching, the stop layer 403 located in the core region B3 and below the protective layer 450 can be almost completely removed because the etching liquid or etching gas has good fluidity and can make sufficient contact with the surface to be etched.

[0089] Under the same etching process, the etching selectivity ratio of the protective layer 450 to the stop layer 403 is, for example, 50 to 200:1. Taking dry etching as an example, the etching selectivity ratio of the protective layer 450 to the stop layer 403 can be improved by adjusting at least one of the type, proportion, and temperature of the gas used for etching.

[0090] Optionally, during the process of removing a portion of the stop layer 403 located in the core region B3, at least one of the type, proportion, and temperature of the etching gas can be adjusted to achieve a high etching selectivity between the stop layer 403 and the first functional layer of the first channel structure 430, so that the portion of the first functional layer extending into the stop layer 403 may not be removed. After the above processing, a portion of the second insulating layer 404 located in the core region B3 can be exposed, and the portion of the first functional layer extending into the stop layer 403 can also be exposed.

[0091] For example, the stop layer 403 located in the step area B1 can also be removed. Figure 4 ) and outer area B4 ( Figure 4 The portion of the second insulating layer 404 located in the step region B1 and the peripheral region B4 can be exposed.

[0092] It should be understood that, in cases such as Figure 11 Of the two second channel structures 420 shown, the other second channel structure 420 extending into the stop layer 403 will not have the stop layer 403 removed during the removal of a portion of the stop layer 403 due to the covering effect of the protective layer 450.

[0093] In some embodiments, such as Figure 12 As shown, the protective layer 450 can be removed after removing a portion of the stop layer 403 located in the core region B3. Exemplarily, the protective layer 450 can be removed by an etching process (e.g., dry etching or wet etching). Exemplarily, when the material of the protective layer 450 is photoresist, the protective layer 450 can be removed under heated conditions using, for example, a wet chemical process or a plasma process.

[0094] In the example where the protective layer 450 is silicon nitride or silicon oxide and the first functional layer is an ONO composite layer, the process of removing the protective layer 450 can remove at least a portion of the exposed first functional layer. In the example of a dry etching process, the etching selectivity ratio of the protective layer 450 and the ONO composite layer can be reduced by adjusting at least one of the type, proportion and temperature of the etching gas, so that the exposed portion of the second functional layer can be completely removed while the protective layer 450 is removed.

[0095] For example, the exposed portion of the first functional layer can be removed at the same time as the protective layer 450 is removed, and the remaining exposed portion of the first functional layer can be removed after the protective layer 450 is removed. After the above process, the first channel layer 434 of the first channel structure 430 can be exposed. Optionally, a portion of the second insulating layer 404 in the core region B3 and a portion of the polysilicon layer 405 in the core region B3 can also be removed during the removal of the protective layer 450 and the exposed portion of the first functional layer. For example, portions of the second insulating layer 404 in the step region B1 and the peripheral region B4 and portions of the polysilicon layer 405 in the step region B1 and the peripheral region B4 can also be removed during the removal of the protective layer 450 and the exposed portion of the first functional layer.

[0096] It should be understood that, in the two second channel structures 420 shown as Figure 12 In the other second channel structure 420 extending to the stop layer 403, the portion of the second channel structure 420 extending to the stop layer 403 will not be removed during the removal of the portion of the first functional layer due to the protection of the stop layer 403, and the first channel layer will not be exposed and will not be in contact with the semiconductor layer 410' formed below.

[0097] Referring to Figure 13In some examples, a semiconductor layer 410' can be formed in contact with the second channel layer 424 and the first channel layer 434 on the side of the stop layer 403 facing away from the stack structure 440. Illustratively, the semiconductor layer 410' can cover the exposed portions of the second channel layer 424 and the first channel layer 434. Optionally, the process of forming the semiconductor layer 410' can employ a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Illustratively, the material of the semiconductor layer 410' can include, for example, polysilicon. Illustratively, the method of forming the semiconductor layer 410' can further include forming an amorphous silicon layer on the side of the stop layer 403 facing away from the stack structure 440 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Further, the amorphous silicon can be crystallized into polysilicon using, for example, a laser annealing or a thermal annealing process to form the semiconductor layer 410'. Optionally, the surface of the deposited semiconductor layer 410' can be planarized using, for example, a CMP process. It should be appreciated that the semiconductor layer 410' is electrically connected to each other by being in contact with the second channel layer 424 and the first channel layer 434. The semiconductor layer 410' formed according to the embodiments of the present application can be in contact with the second channel layer 424 through the stop layer 403 at the transition region B2, and since the portion of the semiconductor layer 410' at the transition region B2 is spaced apart from the conductive layer 416 by at least the stop layer 403, the risk of word line leakage caused by the contact between the semiconductor layer 410' and the conductive layer 416 can be reduced.

[0098] Some embodiments of the present application further provide a three-dimensional memory 600 which can be formed using some or all of the operations of the method 300 described above. Figure 14 A cross-sectional view of the three-dimensional memory 600 is shown. As Figure 14 shown, the three-dimensional memory 600 can include a memory array 400' and a peripheral circuit 200'. In some embodiments, the memory array 400' can include a semiconductor layer 410' and a stack structure 440' on the semiconductor layer 410'. Optionally, the material for the semiconductor layer 410' can include silicon (e.g., single crystal silicon, polysilicon), metal, or metal nitride. In some cases, the semiconductor layer 410' can also be doped, for example, with N-type conductive particles to improve the conductivity of the semiconductor layer 410'.

[0099] In some examples, the stack structure 440' can include a plurality of alternating stacks of the dielectric layers 415 and the conductive layers 416. Optionally, the conductive layers 416 can be used as control gates to pull out word lines (not shown), for example. In some examples, the material used for the conductive layers 416 can include metal conductive materials such as W, Co, Cu, Al, Ti, Ta, Ni, etc. In some examples, the material used for the dielectric layers 415 can also include semiconductor materials such as polysilicon, doped silicon, metal silicides (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof, for example.

[0100] With continued reference to Figure 14 In some examples, the stack structure 440' can include a step region B1 and a core region B3, and a transition region B2 between the step region B1 and the core region B3, the transition region B2 can be contiguous to the core region B3. The step region B1 can include a step structure, each step of the step structure includes at least one pair of a dielectric layer 415 and a conductive layer 416.

[0101] Optionally, the memory array 400' further includes a peripheral region B4 located at a side of the step region B1 facing away from the transition region B2, in a direction parallel to the semiconductor layer 410', the conductive layers 416 and the dielectric layers 415 can extend from the core region B3 to the step region B1 and stop at a location where the step region B1 is contiguous to the peripheral region B4.

[0102] As an option, the step region B1 can be located at both sides of the core region B3. As another option, the step region B1 can be located at both sides of the core region B3 (the structure is not shown), the present disclosure does not limit the relative positions of the step region B1 and the core region B3. With reference to Figure 14 In some examples, the memory array 400' further includes a stop layer 403, the stop layer 403 can be located between the stack structure 440' and the semiconductor layer 410' of the transition region B2. With reference to Figure 15 In other examples, the stop layer 403 included in the three-dimensional memory 800 can be located between the stack structure 440' and the semiconductor layer 410' of the transition region B2, the step region B1, and the peripheral region B4.

[0103] In examples such as Figure 14 and Figure 15 In some examples, a portion of the semiconductor layer 410' on the same side as the stack structure 440' can be lower than the rest of the surface on the same side, for example, a portion of the semiconductor layer 410' on the same side as the stack structure 440' can be inwardly recessed, the stop layer 403 can be located on the surface of the inwardly recessed portion of the semiconductor layer 410'. Optionally, the stack structure 440' can be located on the surface of both the semiconductor layer 410' and the stop layer 403 on the same side as the stack structure 440'.

[0104] In some examples, the memory array 400' further includes a polysilicon layer 405 between the semiconductor layer 410' and the stack structure 440'.

[0105] In some examples, the memory array 400' further includes an insulating layer 404'. The insulating layer 404' can be between the semiconductor layer 410' and the stack structure 440'. Optionally, the insulating layer 404' can be on a surface of the stop layer 403 opposite to the stack structure 440'. Optionally, a surface of the insulating layer 404' opposite to the stack structure 440' can be flush with the semiconductor layer 410'. As an option, the material for the stop layer 403, for example, includes polysilicon, and the material for the insulating layer 404', for example, includes silicon oxide. In some examples, the side surface of the inwardly recessed portion of the semiconductor layer 410' can be a convex surface convex toward a direction parallel to the semiconductor layer 410', and the stop layer 403 can have a concave surface in contact with and mating the convex surface of the semiconductor layer 410'.

[0106] Optionally, the stop layer 403 can have a relatively thicker thickness as compared to the second insulating layer 404 and the polysilicon layer 405, such that a channel structure passing through the stack structure 440' can be stopped at the stop layer 403.

[0107] In some examples, the memory array 400' further includes a fill layer 411, which can cover the step structure of the step region B1. Optionally, a surface of the fill layer 411 away from the semiconductor layer 410' can be planar, such that the memory array 400' can be provided with a substantially planar surface. Illustratively, the material for the fill layer 411, for example, includes an insulating material such as silicon oxide.

[0108] Continuing to refer to Figure 14In some examples, the memory array 400' further includes a plurality of trench structures passing through the stack structure 440', such as a first trench structure 430 located in the core region B3, a second trench structure 420 and a third trench structure 460 located in the transition region B2 (the second and third trench structures can also be referred to as "transition trench structures"). Optionally, the first trench structure 430 can pass through the stack structure 440' located in the core region B3. Illustratively, the second trench structure 420 can pass through the stack structure 440' and the stop layer 403 located in the transition region B1. As an option, the third trench structure 460 can pass through the stack structure 440' and stop in the stop layer 403. Optionally, the transition region B1 can further include only the third trench structure 460, i.e., in the above method 300, the second trench structure 420 does not undergo the etching process. In examples where the three-dimensional memory 600 includes the polysilicon layer 405, the first trench structure 430, the second trench structure 420 and the third trench structure 460 can further pass through the polysilicon layer 405. In examples where the three-dimensional memory 600 includes the insulating layer 404' and the polysilicon layer 405, the second trench structure 420 can pass through the stack structure 440', the polysilicon layer 405, the insulating layer 404' and the stop layer 403 in sequence. Optionally, the third trench structure 460 can pass through the stack structure 440', the polysilicon layer 405, the insulating layer 404' and extend into the stop layer 403 in sequence.

[0109] To provide a good stress support, in the same horizontal direction parallel to the semiconductor layer 410', the size of the second trench structure 420 is generally larger than the size of the first trench structure 430.

[0110] It should be understood that, Figure 14 For example only, the core region B3 can include more than two first trench structures 430 in the structure of the three-dimensional memory.

[0111] In some examples, the first trench structure 430 includes, for example, a first functional layer, a first channel layer 434 and a first dielectric core 435 arranged in sequence from outside to inside. Optionally, the first channel layer 434 can pass through the stack structure 440' and extend into the semiconductor layer 410' located in the core region B3. In some examples, the first functional layer can include, for example, a first barrier layer 431, a first storage layer 432 and a first tunneling layer 433 arranged in sequence from outside to inside.

[0112] In some examples, the second channel structure 420 includes, for example, a second functional layer, a second channel layer 424, and a second dielectric core 425 disposed in sequence from outside to inside. Optionally, the second channel layer 424 can pass through the stack structure 440' and the stop layer 403 located at the transition region B2 and extend to the semiconductor layer 410'. In examples in which the three-dimensional memory 600 includes the insulating layer 404' and the polysilicon layer 405, the second channel layer 424 can pass through the stack structure 440', the polysilicon layer 405, the insulating layer 404', and the stop layer 403 in sequence and extend to the semiconductor layer 410'. In some examples, the second functional layer can include, for example, a second blocking layer 421, a second storage layer 422, and a second tunneling layer 423 disposed in sequence from outside to inside.

[0113] In some examples, the third channel structure 460 includes, for example, a third functional layer, a third channel layer 464, and a third dielectric core 465 disposed in sequence from outside to inside. In some examples, the third functional layer can include, for example, a third blocking layer 461, a third storage layer 462, and a third tunneling layer 463 disposed in sequence from outside to inside.

[0114] Exemplarily, in the extension direction of the plurality of channel structures, the size of the second channel layer 424 is greater than the size of the first channel layer 434.

[0115] Optionally, the material for the first blocking layer 431, the second blocking layer 421, and the third blocking layer 461 can include, for example, silicon oxide, silicon oxynitride, high dielectric, or any combination thereof. The material for the first storage layer 432, the second storage layer 422, and the third storage layer 462 can include, for example, silicon nitride, silicon oxynitride, silicon, or any combination thereof. The material for the first tunneling layer 433, the second tunneling layer 423, and the third tunneling layer 463 can include, for example, silicon oxide, silicon oxynitride, or any combination thereof. In one example, the first functional layer and the second functional layer can be, for example, a composite layer including silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0116] In some examples, the memory array 400' can further include a dummy channel structure (not shown) located at the step region B1. The dummy channel structure can pass through the fill layer 411 and extend into the stop layer 403. In some cases, the dummy channel structure can provide structural support for the step structure. Optionally, the material for the dummy channel structure can include, for example, an insulating material such as silicon oxide. Optionally, the internal structure of the dummy channel structure can also be the same as the internal structure of the first channel structure 430 and the second channel structure 420.

[0117] In some examples, the memory array 400' further includes a contact structure 413 formed in the step region Bl, the contact structure 413 can pass through the fill layer 411 and contact each of the conductive layers 416. The contact structure 413 can be used to electrically connect the word lines to the peripheral circuit 200' described below. Optionally, the material used for the contact structure 413 includes a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0118] In some examples, the memory array 400' further includes a gate line gap structure (not shown) passing through the stack structure 440' and extending into the semiconductor layer 410'. Optionally, the gate line gap structure can include a spacer layer (not shown) and a conductor layer (not shown) disposed from outside to inside. Optionally, the spacer layer can be used to electrically isolate two adjacent conductive layers 416.

[0119] In some examples, the memory array 400' further includes a peripheral contact 412 passing through the fill layer 411 in the peripheral region B4, the peripheral contact 412 can be used to electrically connect the two opposite surfaces of the memory array 400' in subsequent processes. Optionally, the material used for the peripheral contact 412 includes a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0120] In some examples, the memory array 400' further includes a first interconnect layer 414 on the stack structure 440'. In some examples, the first interconnect layer 414 can include a first interconnect line 417 disposed parallel or substantially parallel to the first substrate 410. Optionally, the first interconnect layer 414 can further include a first interconnect contact 418 disposed perpendicular or substantially perpendicular to the first substrate 410 and in contact with the first interconnect line 417. Optionally, the peripheral contact 412, the contact structure 413, and the channel layer of each channel structure can be electrically connected to the first interconnect line 417 by disposing a metal contact. Optionally, the above-mentioned structures electrically connected to the first interconnect line 417 can be electrically connected to other semiconductor structures (e.g., the peripheral circuit described below) through the first interconnect contact 418. Optionally, the material used for the first interconnect line 417 and the first interconnect contact 418 includes a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0121] Continuing to refer to Figure 14 In some embodiments, the peripheral circuit 200' includes a substrate (e.g., the second substrate 210 in Figure 4 the peripheral circuit structure 240 on the substrate 220, and a second interconnect layer 214 on a side of the peripheral circuit structure 240 facing away from the substrate 220.

[0122] During operation of the three-dimensional memory, the peripheral circuit 200' can be configured to control and sense the three-dimensional memory. In some examples, the peripheral circuit 200' can include, for example, high-voltage devices for controlling high-voltage signals and / or low-voltage devices for improving read-write speed. Optionally, the high-voltage devices and / or low-voltage devices are composed of, for example, MOS transistors (not shown).

[0123] In some examples, the second interconnection layer 214 can include second interconnection lines 217 disposed parallel or substantially parallel to the substrate 220. Optionally, the second interconnection layer 214 can also include second interconnection contacts 218 disposed perpendicular or substantially perpendicular to the substrate 220 and in contact with the second interconnection lines 217. Exemplarily, the memory array 400' can be face-to-face hybrid bonded with the peripheral circuit 200', the first interconnection contacts 418 can be in corresponding contact with the second interconnection contacts 218 at the bonding interface, thereby electrically connecting the memory array 400' with the peripheral circuit 200'. During operation of the three-dimensional memory, the control of the memory array by the peripheral circuit can be achieved through the electrical connection of the memory array 400' with the peripheral circuit 200'.

[0124] Some embodiments of the present application also provide a system including a memory, which can be any of the examples of the three-dimensional memory 600 or the three-dimensional memory 800 described above. As shown in Figure 16 The system 500 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein, as shown. With continued reference to Figure 17 The system 500 can include a host 408 and a memory system 409 having one or more memories 407 and a memory controller 406, as shown. The host 408 can be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC), such as an application processor (AP). The host 408 can be configured to send or receive data stored in the memory 407.

[0125] According to some embodiments, the memory controller 406 is coupled to the memory 407 and the host 408 and is configured to control the memory 407. The memory controller 406 can manage data stored in the memory 407 and communicate with the host 408. In some embodiments, the memory controller 406 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 406 is designed for operation in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC) used as data storage for mobile devices such as smartphones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 406 can be configured to control operations of the memory 407, such as read, erase, and program operations. The memory controller 406 can also be configured to manage various functions with respect to data stored or to be stored in the memory 407, including bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to process error correction codes (ECC) for data read from or written to the memory 407. Any other suitable functions can also be performed by the memory controller 406, e.g., formatting the memory 407. The memory controller 406 can communicate with external devices (e.g., the host 408) according to a particular communication protocol. For example, the memory controller 406 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0126] The memory controller 406 and the one or more memories 407 can be integrated into various types of memory devices, e.g., included in the same package, such as a universal flash (UFS) package or an eMMC package. That is, the memory system 409 can be implemented as and packaged into different types of end electronic products. In the case of a UFS package, the memory system 409 can be implemented as and packaged into a smartphone, a tablet, a laptop, a digital camera, a camcorder, a personal computer, etc. In the case of an eMMC package, the memory system 409 can be implemented as and packaged into a smartphone, a tablet, a laptop, a digital camera, a camcorder, a personal computer, etc. Figure 16In one example shown, the memory controller 406 and the single memory 407 can be integrated into a memory card 502. The memory card 502 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 502 can further include a memory card connector 504 that electrically couples the memory card 502 with the host 408 (e.g., in a host 408). Figure 18 In another example shown, the memory controller 406 and the multiple memories 407 can be integrated into an SSD 506. The SSD 506 can further include an SSD connector 508 that electrically couples the SSD 506 with the host 408 (e.g., in a host 408). In some embodiments, the storage capacity and / or operating speed of the SSD 506 is greater than the storage capacity and / or operating speed of the memory card 502. Figure 16 Figure 19

[0127] Figure 19 A schematic diagram of a memory 601 including a peripheral circuit and a storage array according to some embodiments of the present application is shown. The memory 601 can be any of the examples of the three-dimensional memory 600 or the three-dimensional memory 800 described above. As shown. The three-dimensional memory 601 includes a coupled storage array 301 (e.g., any of the examples of the storage array 400' described above) and a peripheral circuit (e.g., any of the examples of the peripheral circuit 200' described above). In some embodiments, the storage array 301 can be a flash memory array, for example, and can be implemented using 3D NAND flash technology. The peripheral circuit includes, for example, a page buffer / sense amplifier 505, a column decoder / bit line driver 507, a row decoder / word line driver 509, a voltage generator 510, a control logic unit 512, a register 514, an I / F interface 516, and a data bus 518. It should be understood that in some examples, the peripheral circuit can also include additional peripheral circuits not shown in FIG. 6. Figure 19 Figure 16

[0128] ​​​​In some examples, the page buffer / sense amplifier 505 can be configured to read and program (write) data from and to the memory array according to control signals from the control logic unit 512. Optionally, the page buffer / sense amplifier 505 can store a page of program data (write data) to be programmed into a memory page of the memory array. In another example, the page buffer / sense amplifier 505 can also sense a low power signal representing a data bit stored in a memory cell from a bit line during a read operation, and amplify the small voltage swing to an identifiable logic level. The column decoder / bit line driver 507 can be configured to be controlled by the control logic unit 512 and select one or more strings of memory cells 308 by applying a bit line voltage generated by the voltage generator 510.

[0129] In some embodiments, the row decoder / word line (WL) driver 509 can be configured to be controlled by the control logic unit 512 and select / deselect a memory block of the memory array and select / deselect a word line of the block. The row decoder / word line driver 509 can also be configured to drive a word line using a word line voltage generated by the voltage generator 510. In some implementations, the row decoder / word line (WL) driver 509 can also select / deselect and drive a source select line (SSL) and a drain select line (DSL).

[0130] In some embodiments, the voltage generator 510 can be configured to be controlled by the control logic unit 512 and generate various operating voltages (erase, program, or read voltages) to be provided to the memory array. For example, in a read operation, a read voltage is provided to the row decoder 509 to drive a word line (WL) to read a memory cell 306 coupled thereto.

[0131] In some embodiments, the control logic unit 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The control logic unit 512 can perform the operation methods of the flash memory described below. The register 514 can be coupled to the control logic unit 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address to control the operation of each of the peripheral circuits.

[0132] In some embodiments, the I / F interface 516 can be coupled to the control logic unit 512 and act as a control buffer to buffer commands and data from a host (e.g., a microprocessor, a microcontroller, or a memory controller) to the control logic unit 512. The I / F interface 516 can also buffer data from the control logic unit 512 to the host. ​The I / F interface 516 also couples to the column decoder / bit line drivers 507 via the data bus 518 and acts as a data input / output (I / O) interface and data buffer, buffering and forwarding data to and from the memory array. The control logic unit 512 is coupled to the I / F interface 516 and receives control commands from the host 408 (e.g., via the host 408 shown in FIG. 5) and forwards them to the I / F interface 516, and buffers status information received from the I / F interface 516 and forwards it to the host 408. The I / F interface 516 can also be coupled to the column decoder / bit line drivers 507 via the data bus 518 and acts as a data input / output (I / O) interface and data buffer, buffering and forwarding data to and from the memory array.

[0133] The specific embodiments described above are further to the purpose, technical solutions, and beneficial effects of the present application. It should be understood that the above are merely specific embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of fabricating a three-dimensional memory, characterized by, comprising: forming a stack layer on a substrate, the stack layer comprising a core region and a transition region contiguous to the core region, the substrate comprising a base and a stop layer between the base and the stack layer; forming a plurality of trench structures through the stack layer and extending into the substrate, the plurality of trench structures comprising first trench structures in the core region and second trench structures in the transition region, the first trench structures extending into the stop layer and comprising first channel layers, at least one of the second trench structures penetrating through the stop layer and extending into the base and comprising a second channel layer; removing at least the base to expose a portion of the stop layer and the second channel layer; forming a protection layer on a side of the stop layer facing away from the stack layer, the protection layer covering at least the second channel layer in a direction parallel to the stop layer; removing a portion of the stop layer corresponding to the core region to expose a portion of the first trench structures; removing the protection layer to expose a portion of the first channel layers; and forming a semiconductor layer in contact with the first channel layers and the second channel layer. the first trench structures further comprise a first functional layer, the first channel layers being inside the first functional layer, and exposing a portion of the first channel layers comprises:

2. The method of claim 1, wherein, removing a portion of the first functional layer extending into the stop layer. removing a portion of the first functional layer extending into the stop layer simultaneously with removing the protection layer.

3. The method of claim 2, wherein, removing a portion of the first functional layer extending into the stop layer comprises:

4. The method of claim 2, wherein, removing a portion of the first functional layer extending into the stop layer during removal of the protection layer; and removing a remaining portion of the first functional layer extending into the stop layer after removal of the protection layer. the second trench structures further comprise a second functional layer, the second channel layer being inside the second functional layer; 5. The method of claim 2, wherein, wherein removing at least the base further comprises removing a portion of the second functional layer extending into the base to expose the second channel layer. the base comprises a substrate and a first insulating layer between the substrate and the stop layer, and wherein removing at least the base further comprises:

6. The method of claim 5, wherein, removing the first insulating layer. the second trench structures penetrate through the first insulating layer and extend into the substrate, and wherein removing at least the base further comprises:

7. The method of claim 6, wherein, removing a portion of the second functional layer extending into the substrate simultaneously with removing the base; and removing a portion of the second functional layer extending into the first insulating layer simultaneously with removing the first insulating layer.

8. The method of claim 1, further comprising: forming a second insulating layer on the stop layer before forming the stack layer; and removing a portion of the second insulating layer corresponding to the core region after removing the portion of the stop layer corresponding to the core region.

9. A three-dimensional memory, comprising: a semiconductor layer; a stack structure on the semiconductor layer and comprising a core region and a transition region contiguous to the core region; ​ ​ a stop layer located at least between the stack structure in the transition region and the semiconductor layer; and a plurality of trench structures including: a plurality of first trench structures passing through the stack structure in the core region and including a first trench layer extending into the semiconductor layer; and at least one second trench structure passing through the stack structure in the transition region and the stop layer and including a second trench layer extending into the semiconductor layer. the plurality of trench structures further including:

10. The three-dimensional memory of Claim 9 wherein, at least one third trench structure passing through the stack structure in the transition region and extending into the stop layer. in an extension direction of the trench structures, a size of the first trench layer is larger than a size of the second trench layer.

11. The three-dimensional memory of Claim 9 wherein, in a direction parallel to the semiconductor layer, a size of the first trench structure is larger than a size of the second trench structure.

12. The three-dimensional memory of Claim 9 wherein, the semiconductor layer has a convex surface recessed toward a radial direction of the first trench structure, and the stop layer has a concave surface in contact with and cooperating with the convex surface.

13. The three-dimensional memory of Claim 9 wherein, the stop layer includes polysilicon, and the semiconductor layer includes one of N-type doped polysilicon, metal, or metal nitride.

14. The three-dimensional memory of Claim 9 wherein, 15. A memory system comprising: a three-dimensional memory as claimed in any one of claims 9 to 14, the three-dimensional memory configured to store data; and a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory. a solid state drive or a memory card.

16. The memory system of claim 15, comprising: ​

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