Display substrate, method for manufacturing display substrate, and display device

Abstract

The present invention relates to the field of display, and discloses a display substrate, a method for manufacturing the display substrate, and a display device. The display substrate includes a display area and a non-display area surrounding the display area, and the non-display area includes a fan-out area; the display substrate includes a base substrate, a transparent conductive layer and a metal conductive layer sequentially stacked on the base substrate; the transparent conductive layer has no pattern in the fan-out area; the fan-out area includes a fan-out trace formed by the pattern of the metal conductive layer. A set of mask plates is used in a narrow-frame display device to increase the line width of the fan-out trace in the fan-out area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate, a method for manufacturing the display substrate, and a display device. Background Art

[0002] As people's lives change with each passing day, consumers have higher and higher demands on the quality of display devices. While pursuing large-size display devices, various large-size ultra-narrow frame display devices have also emerged. Since the frame position is often set with peripheral wiring, the size of the peripheral wiring has a decisive influence on the size of the bottom frame, so the narrow frame has stricter requirements on the size of the peripheral wiring.

[0003] In order to cope with market changes, narrow-framed display devices have a smaller area for wiring on the bottom frame. Here, the wiring width is narrowed to meet the size of the narrow frame. However, narrowing the wiring width will increase the risk of wiring disconnection or short circuit. At the same time, the narrowing of the wiring width will highlight the resistance difference between the wiring, resulting in insufficient charging rate of the display area in the display device, thereby affecting the picture quality and display effect. Summary of the invention

[0004] The invention discloses a display substrate, a method for manufacturing the display substrate and a display device, which are used to use a set of mask plates in a narrow-frame display device to increase the line width of a fan-out line in a fan-out area.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention provides a display substrate, the display substrate comprising a display area and a non-display area surrounding the display area, the non-display area comprising a fan-out area;

[0007] The display substrate comprises a base substrate, a transparent conductive layer and a metal conductive layer sequentially stacked on the base substrate; the transparent conductive layer has no pattern in the fan-out area;

[0008] The fan-out region includes a fan-out trace formed by a pattern of the metal conductive layer.

[0009] A transparent conductive layer is arranged on the base substrate. The transparent conductive layer is in other areas except the fan-out area. A metal conductive layer covering the transparent conductive layer is arranged on the base substrate. A fan-out wiring composed of a pattern of the metal conductive layer is formed in the fan-out area. The fan-out wiring can be formed by only one etching, thereby simplifying the process and reducing the production cost and time cost. In addition, since the fan-out wiring is formed by only one etching, the width of the fan-out wiring can be guaranteed, and the risk of disconnection or short circuit of the fan-out wiring is effectively reduced. At the same time, since the fan-out wiring width becomes wider, the resistance difference between the wirings will be weakened, so that the charging rate of the display area in the display device is sufficient, thereby improving the picture quality and display effect.

[0010] Optionally, the display substrate further includes a first conductive medium layer located in the fan-out region;

[0011] The first conductive medium layer is located between the film layer where the fan-out wiring is located and the substrate.

[0012] Optionally, the display area includes a gate line formed by a pattern of the stacked metal conductive layer and a pattern of the transparent conductive layer, a common electrode formed by a pattern of the transparent conductive layer, and a common electrode line formed by a pattern of the metal conductive layer stacked on the common electrode.

[0013] Optionally, the pattern of the transparent conductive layer constituting the gate line has a portion extending out of the pattern of the metal conductive layer.

[0014] Optionally, the non-display area includes a static electricity lead-out area, an anti-static portion consisting of a pattern of the metal conductive layer and a pattern of the transparent conductive layer stacked in layers, and the static electricity lead-out portion is located in the static electricity lead-out area.

[0015] Optionally, the display substrate further comprises a second conductive medium layer located in the static electricity derivation area;

[0016] The second conductive medium layer is located between the metal conductive layer and the transparent conductive layer constituting the antistatic portion.

[0017] Optionally, the pattern of the transparent conductive layer constituting the antistatic portion has a portion extending out of the pattern of the metal conductive layer.

[0018] In a second aspect, the present invention provides a method for manufacturing a display substrate, wherein the display substrate comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a fan-out area; the manufacturing method comprises:

[0019] Providing a substrate;

[0020] Using a mask process, forming a transparent conductive layer without a pattern in the fan-out area on the base substrate;

[0021] forming a metal conductive layer covering the transparent conductive layer on the base substrate;

[0022] A photoresist layer is formed on the metal conductive layer, and the photoresist layer is patterned by a mask process to obtain a patterned mask layer, wherein the patterned mask layer includes a pattern shielding area and a pattern thinning area, wherein the pattern shielding area at least covers the fan-out wiring to be formed, and the pattern thinning area at least covers the area between the fan-out wirings;

[0023] The metal conductive layer and the transparent conductive layer are etched by shielding with the patterned mask layer, so as to form a fan-out wiring in the fan-out area.

[0024] A transparent conductive layer is formed on the substrate by using a mask process. The transparent conductive layer is formed in other areas except the fan-out area. A metal conductive layer covering the transparent conductive layer is formed on the substrate, and a photoresist layer is formed on the metal conductive layer. A set of mask plates are used to pattern the photoresist layer to obtain a patterned mask layer. The patterned mask layer includes a pattern shielding area and a pattern thinning area. The pattern shielding area at least covers the fan-out wiring to be formed, and the pattern thinning area at least covers the area between adjacent fan-out wirings. The metal conductive layer and the transparent conductive layer are etched by using the shielding of the patterned mask layer, that is, in the pattern The metal conductive layer is etched in the pattern thinned area of ​​the mask layer to form a fan-out wiring in the fan-out area. The fan-out wiring can be formed by only one etching, thereby simplifying the process, reducing the production cost and time cost, and only requiring one set of mask plates to achieve it, which further reduces the cost of the mask plates. Moreover, since the fan-out wiring is formed by only one etching, the width of the fan-out wiring can be guaranteed, effectively reducing the risk of disconnection or short circuit of the fan-out wiring. At the same time, because the fan-out wiring width becomes wider, the resistance difference between the wirings will be weakened, resulting in a sufficient charging rate of the display area in the display device, thereby improving the picture quality and display effect.

[0025] Optionally, the pattern shielding area also covers the gate lines and common electrode lines to be formed, and the pattern thinning area also covers the common electrode to be formed;

[0026] The metal conductive layer and the transparent conductive layer are etched by shielding with the patterned mask layer to form a fan-out wiring in the fan-out area, specifically including:

[0027] By shielding the patterned mask layer, the metal conductive layer and the transparent conductive layer are etched one by one in sequence to form gate lines and common electrodes in the display area;

[0028] Thinning the patterned mask layer to remove the pattern thinning area;

[0029] The metal conductive layer is subjected to secondary etching by shielding with the thinned patterned mask layer, so as to form a common electrode line located on the common electrode in the display area and to form the fan-out wiring in the fan-out area.

[0030] Optionally, the pattern shielding area also covers the anti-static part to be formed;

[0031] By shielding the patterned mask layer, the metal conductive layer and the transparent conductive layer are etched one by one in sequence, and a gate line and a common electrode are formed in the display area, while an antistatic part is formed in the non-display area.

[0032] Optionally, the metal conductive layer is etched a second time by shielding the thinned graphic mask layer, forming a common electrode line above the common electrode in the display area, and the anti-static part and the gate line are over-etched while forming the fan-out wiring in the fan-out area.

[0033] In a third aspect, the present invention provides a display device, comprising the display substrate described in any one of the second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of a fan-out wiring structure of a fan-out area in a display substrate provided by an embodiment of the present invention;

[0035] Figure 2 A top view of a display substrate provided by an embodiment of the present invention;

[0036] Figure 3a-3e A diagram showing a change in the film structure of a fan-out region in a display substrate provided by an embodiment of the present invention;

[0037] Figure 4 for Figure 2 A cross-sectional view of the A-A' section;

[0038] Figure 5a-5h A diagram showing a change in the film structure of an electrostatic lead-out area in a display substrate provided by an embodiment of the present invention;

[0039] Figure 6 for Figure 2 A cross-sectional view of the C-C' section;

[0040] Figure 7a-7h A diagram showing a change in the film layer structure of a display area in a display substrate provided by an embodiment of the present invention;

[0041] Figure 8 for Figure 2 Cross-sectional view of the BB' section.

[0042] In the figure: A-display area; B-non-display area; B1-fan-out area; B2-electrostatic lead-out area;

[0043] 1-substrate substrate; 2-transparent conductive layer; 21-common electrode; 22-gate line extension area; 23-antistatic part extension area; 3-metal conductive layer; 31-fan-out wiring; 32-gate line; 33-common electrode line; 4-antistatic part; 5-conductive medium layer; 51-first sub-conductive medium layer; 52-second sub-conductive medium layer; 6-patterned mask layer; 61-pattern shielding area; 62-pattern thinning area; 7-insulating layer; 8-passivation layer; 9-pixel electrode layer. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] The bottom frame width of a normal display device is above 7.5 mm, while the bottom frame width of a narrow frame display device is mostly 6.0 mm to 6.5 mm. Therefore, the sum of the fan-out trace 31 and the gap of the fan-out trace 31 in the fan-out area B1 is set at least 9.9 um to 10.4 um to meet the requirements of a large-size display device. Figure 1 As shown, D1 is the line width of the fan-out wiring 31, D2 is the gap between the fan-out wiring 31, and D1+D2 should meet 9.9um to 10.4um. For example, the large-size display device here refers to a display device larger than 65 inches.

[0046] When preparing the fan-out area B1 routing, because the fan-out area B1 of the large-size display device requires multiple fan-out routings 31, in order to meet the requirement of narrow frame of the large-size display device, the fan-out routing 31 will be narrowed; and when preparing the fan-out routing 31, there is a certain size deviation so that the line width of the final fan-out area B1 routing will be narrower. Due to the existence of size deviation, the actual fan-out routing 31 line width is narrowed, so that the fan-out routing 31 is prone to disconnection in the fan-out area B1.

[0047] High refresh rates in display devices are also a popular trend now. Refresh rate refers to the number of times the electron beam repeatedly scans the image on the screen. The higher the refresh rate, the better the stability of the displayed image (picture). However, at a high refresh rate, the charging rate of display area A will be insufficient. The narrowing of the fan-out line 31 of the fan-out area B1 will highlight the resistance difference between the lines, resulting in insufficient charging rate of display area A in the display device, which affects the image quality and display effect, making it impossible to increase the refresh rate of the display device.

[0048] In order to simultaneously satisfy the advantages of a display device having a high refresh rate and a narrow frame, it is specifically achieved in the following manner:

[0049] like Figure 2 As shown, the area of ​​the display substrate provided by the embodiment of the present invention is divided as follows: the display substrate includes a display area A and a non-display area B surrounding the display area A, and the non-display area B includes a fan-out area B1 and an electrostatic derivation area B2.

[0050] like Figure 3a-3e As shown, an embodiment of the present invention provides a method for manufacturing a display substrate, comprising:

[0051] Providing a substrate 1;

[0052] A transparent conductive layer 2 without a pattern in the fan-out area B1 is formed on the base substrate 1 by using a mask process;

[0053] A metal conductive layer 3 covering the transparent conductive layer 2 is formed on the base substrate 1;

[0054] A photoresist layer is formed on the metal conductive layer 3, and a mask process is used to pattern the photoresist layer to obtain a patterned mask layer 6, wherein the patterned mask layer 6 includes a pattern shielding area 61 and a pattern thinning area 62, wherein the pattern shielding area 61 at least covers the fan-out wiring 31 to be formed, and the pattern thinning area 62 at least covers the area between the fan-out wirings 31;

[0055] By shielding the patterned mask layer 6 , the metal conductive layer 3 and the transparent conductive layer 2 are etched to form a fan-out wiring 31 in the fan-out area B1 .

[0056] It should be noted that a transparent conductive layer 2 is formed on the base substrate 1 by using a mask process. The transparent conductive layer 2 is formed in other areas except the fan-out area B1. A metal conductive layer 3 covering the transparent conductive layer 2 is formed on the base substrate 1, and a photoresist layer is formed on the metal conductive layer 3. A set of mask plates are used to pattern the photoresist layer to obtain a patterned mask layer 6. The patterned mask layer 6 includes a pattern shielding area 61 and a pattern thinning area 62. The pattern shielding area 61 at least covers the fan-out wiring 31 to be formed, and the pattern thinning area 62 at least covers the area between adjacent fan-out wirings 31. The metal conductive layer 3 and the transparent conductive layer 2 are etched by shielding the patterned mask layer 6. That is, the metal conductive layer 3 is etched in the pattern thinning area 62 of the patterned mask layer 6, and a fan-out wiring 31 is formed in the fan-out area B1. The fan-out wiring 31 can be formed by only one etching, thereby simplifying the process, reducing the production cost and time cost, and only requiring one set of mask plates to achieve it, which further reduces the cost of the mask plates; and because the fan-out wiring 31 is formed by only one etching, the width of the fan-out wiring 31 can be guaranteed, and the risk of the fan-out wiring 31 being disconnected or short-circuited is effectively reduced. At the same time, because the line width of the fan-out wiring 31 becomes wider, the resistance difference between the wirings will be weakened, and the charging rate of the display area A in the display device is sufficient, thereby improving the picture quality and display effect.

[0057] In some specific embodiments, a sputtering mask process is used on the base substrate 1 to shield the fan-out area B1 to avoid deposition of the transparent conductive layer 2 on the fan-out area B1. For example, the material of the transparent conductive layer 2 is ITO (Indium Tin Oxides), which is a transparent conductor. The performance of this material can be adjusted by adjusting the ratio of indium and tin, the deposition method, the degree of oxidation, and the size of the grains. The transparent conductive layer 2 is normally formed on the base substrate 1 except for the fan-out area B1 to form a transparent conductive layer 2. For example, the film thickness of the transparent conductive layer 2 is 200A to 700A.

[0058] Before forming the metal conductive layer 3 covering the transparent conductive layer 2 on the base substrate 1, the conductive medium layer 5 is formed first. Specifically, the display area A is shielded by a sputtering mask process to ensure that the conductive medium layer 5 is formed in the fan-out area B1. Since both the transparent conductive layer 2 and the conductive medium layer 5 are formed by a sputtering mask process, there is a film forming fuzzy area, that is, the film thickness is relatively unstable. Therefore, the electrostatic derivation area B2 located between the display area A and the fan-out area B1 is used as two film forming fuzzy areas, that is, the electrostatic derivation area B2 is the overlapping area of ​​the transparent conductive layer 2 and the conductive medium layer 5, and the conductive medium layer 5 located in the electrostatic derivation area B2 is the second sub-conductive medium layer 52. The range of this area of ​​the electrostatic derivation area B2 is 300μm-1000 microns. For example, the material of the metal conductive layer 3 can be copper; the thickness of the conductive medium layer 5 is 100A-300A, and the material is molybdenum lithium (MoNb).

[0059] The conductive medium layer 5 is formed before the metal conductive layer 3 is deposited in order to increase the adhesiveness between the substrate 1 and the metal conductive layer 3 .

[0060] In the present invention, only one set of mask plates is used, and the pattern thinning area 62 in the display area A provided in the embodiment of the present invention also covers the common electrode 21 to be formed;

[0061] By using the patterned mask layer 6 to block, the metal conductive layer 3 and the transparent conductive layer 2 are etched to form a fan-out wiring 31 in the fan-out area B1, which specifically includes:

[0062] refer to Figure 3a-3e and Figure 4 ,as well as Figure 7a-7h and Figure 8 , using the patterned mask layer 6 to shield, the metal conductive layer 3 and the transparent conductive layer 2 are etched once respectively, to form a gate line 32 and a common electrode 21 in the display area A;

[0063] Performing a thinning process on the patterned mask layer 6 to remove the pattern thinning area 62;

[0064] By shielding the thinned patterned mask layer 6, the metal conductive layer 3 is subjected to a secondary etching process to form a common electrode line 33 located above the common electrode 21 in the display area A, and to form a fan-out wiring 31 in the fan-out area B1.

[0065] It can be understood that the common electrode line 33 located above the common electrode 21 in the display area A is formed through two etching processes, while the fan-out wiring 31 formed in the fan-out area B1 is formed through one etching process. The use of a set of mask processes can ensure the width of the fan-out wiring 31, effectively reducing the risk of disconnection or short circuit of the fan-out wiring 31. At the same time, because the line width of the fan-out wiring 31 becomes wider, the resistance difference between the fan-out wiring 31 will be weakened, resulting in a sufficient charging rate in the display area A in the display device, thereby improving the picture quality and display effect.

[0066] Below Figure 3a-3e and Figure 4 The mask process of the fan-out area B1 is described as follows: the transparent conductive layer 2 is not deposited on the base substrate 1 by shielding the fan-out area B1, a conductive medium layer 5 and a metal conductive layer 3 are sequentially deposited on the base substrate 1, a photoresist layer is formed on the metal conductive layer 3, and a mask process is used to pattern the photoresist layer to obtain a patterned mask layer 6 including a pattern shielding area 61 and a pattern thinning area 62, and the patterned mask layer 6 in the pattern thinning area 62 is thinned, i.e., ashed, so that the patterned mask layer 6 in the pattern thinning area The metal conductive layer 3 of 62 is exposed, the metal conductive layer 3 and the conductive dielectric layer 5 are etched once, and the photoresist layer of the pattern shielding area 61 is peeled off, so that the metal conductive layer 3 is exposed to form a fan-out wiring 31. The conductive dielectric layer 5 located between the film layer where the fan-out wiring 31 is located and the base substrate 1 is the first sub-conductive dielectric layer 51. The first sub-conductive dielectric layer 51 formed between the film layer where the fan-out wiring 31 is located and the base substrate 1 is to increase the adhesiveness between the base substrate 1 and the fan-out wiring 31. Figure 4 In the embodiment, the fan-out wiring 31 is also covered with an insulating layer 7 and a passivation layer 8 in sequence.

[0067] Due to process problems, the difference between the size after one etching and the size after development is 1μm-1.5μm, and the difference between the size after two etchings and the final size after development will be 3.7μm-4.5μm. Therefore, it can be seen that the more times the etching is performed, the greater the deviation value of the line width will be, making the error of the final line width formed greater. Since the line width will cause problems such as disconnection or short circuit, it is extremely important to ensure the production accuracy of the line width. Since the fan-out line 31 is formed only after one etching, the size deviation of the final fan-out line 31 will be effectively guaranteed, so that the risk of short circuit and disconnection can be well avoided, and the yield of the display device can be improved.

[0068] like Figure 5a-5h as well as Figure 6 As shown, the pattern shielding area 61 also covers the anti-static part 4 to be formed;

[0069] By shielding the patterned mask layer 6, the metal conductive layer 3 and the transparent conductive layer 2 are etched one by one in sequence, and the gate line 32 and the common electrode 21 are formed in the display area A, and the antistatic part 4 is formed in the non-display area B.

[0070] Below Figure 5a-5h and Figure 6 The preparation process of the electrostatic lead-out area B2 is described below:

[0071] A transparent conductive layer 2 is deposited on the base substrate 1, and a conductive medium layer 5 and a metal conductive layer 3 are sequentially deposited on the side of the transparent conductive layer 2 facing away from the base substrate 1. A photoresist layer is formed on the metal conductive layer 3, and the photoresist layer is patterned using a mask process to obtain a patterned mask layer 6 including only a pattern shielding area 61. The metal conductive layer 3 and the conductive medium layer 5 are etched once to expose the transparent conductive layer 2, and then the transparent conductive layer 2 is etched, and the patterned mask layer 6 in the pattern shielding area 61 is ashed. The metal conductive layer 3 and the conductive medium layer 5 are etched twice, and the photoresist layer in the pattern shielding area 61 is peeled off to expose the metal conductive layer 3 to form an antistatic part 4. The conductive medium layer located between the metal conductive layer and the transparent conductive layer in the antistatic part is a second sub-conductive medium layer 52. Figure 6 In the figure, the antistatic part 4 is also covered with an insulating layer 7 and a passivation layer 8 in sequence. The pattern of the transparent conductive layer 2 constituting the antistatic part 4 has a portion extending out of the pattern of the metal conductive layer 3, that is, the antistatic part extending area 23 in the figure. For example, the antistatic part extending area 23 is 1μm-1.5μm.

[0072] like Figure 7a-7h as well as Figure 8 As shown, the metal conductive layer 3 is subjected to secondary etching by shielding the thinned patterned mask layer 6, forming a common electrode line 33 located above the common electrode 21 in the display area A, and forming a fan-out wiring 31 in the fan-out area B1, while the anti-static part 4 and the gate line 32 are over-etched.

[0073] Below Figure 7a-7h and Figure 8 The preparation process of the display area A is described below:

[0074] A transparent conductive layer 2 is deposited on the substrate 1, and a metal conductive layer 3 is deposited on the side of the transparent conductive layer 2 facing away from the substrate 1. A photoresist layer is formed on the metal conductive layer 3, and the photoresist layer is patterned using a mask process to obtain a patterned mask layer 6 including a pattern shielding area 61 and a pattern thinning area 62. The metal conductive layer 3 is etched once to expose the transparent conductive layer 2, and the patterned mask layer 6 in the pattern thinning area 62 is thinned, i.e., ashed, to expose the metal conductive layer 3 in the pattern thinning area 62. The metal layer is etched twice, and the photoresist layer in the pattern shielding area 61 is peeled off to expose the metal conductive layer 3 to form a gate and a common electrode line 33. Figure 8 In the figure, the gate and common electrode lines 33 are sequentially covered with an insulating layer 7 and a passivation layer 8, and a pixel electrode layer 9 is formed on the side of the passivation layer 8 away from the insulating layer 7. The pattern of the transparent conductive layer 2 constituting the gate line 32 has a portion extending out of the pattern of the metal conductive layer 3, that is, the gate line extension area 22 in the figure, for example, the gate line extension area 22 is 1μm-1.5μm.

[0075] An embodiment of the present invention provides a display substrate, the display substrate includes a display area A and a non-display area B surrounding the display area A, the non-display area B includes a fan-out area B1;

[0076] The display substrate comprises a base substrate 1, a transparent conductive layer 2 and a metal conductive layer 3 sequentially stacked on the base substrate 1; the transparent conductive layer 2 has no pattern in the fan-out area B1;

[0077] The fan-out area B1 includes a fan-out trace 31 formed by a pattern of the metal conductive layer 3 .

[0078] It should be noted that a transparent conductive layer 2 is provided on the base substrate 1, and the transparent conductive layer 2 is in other areas except the fan-out area B1. A metal conductive layer 3 covering the transparent conductive layer 2 is provided on the base substrate 1, and a fan-out wiring 31 composed of a pattern of the metal conductive layer 3 is formed in the fan-out area B1. The fan-out wiring 31 can be formed by only one etching, thereby simplifying the process and reducing the production cost and time cost. Moreover, since the fan-out wiring 31 is formed by only one etching, the width of the fan-out wiring 31 can be guaranteed, and the risk of disconnection or short circuit of the fan-out wiring 31 is effectively reduced. At the same time, because the line width of the fan-out wiring 31 becomes wider, the resistance difference between the wirings will be weakened, and the charging rate of the display area A in the display device is sufficient, thereby improving the picture quality and display effect.

[0079] Preferably, the display substrate further comprises a first sub-conductive medium layer 51 located in the fan-out area B1;

[0080] The first sub-conductive dielectric layer 51 is located between the film layer where the fan-out trace 31 is located and the base substrate 1 .

[0081] Preferably, the display area A includes a gate line 32 formed by a pattern of a stacked metal conductive layer 3 and a pattern of a transparent conductive layer 2, a common electrode 21 formed by a pattern of the transparent conductive layer 2, and a common electrode line 33 formed by a pattern of the metal conductive layer 3 stacked on the common electrode 21.

[0082] Preferably, the pattern of the transparent conductive layer 2 constituting the gate line 32 has a portion extending out of the pattern of the metal conductive layer 3 .

[0083] Preferably, the non-display area B includes a static electricity lead-out area B2, an anti-static portion 4 consisting of a pattern of a stacked metal conductive layer 3 and a pattern of a transparent conductive layer 2, and the static electricity lead-out portion is located in the static electricity lead-out area B2.

[0084] Preferably, the display substrate further comprises a second sub-conductive medium layer 52 located in the static electricity lead-out area B2;

[0085] The second sub-conductive medium layer 52 is located between the metal conductive layer 3 and the transparent conductive layer 2 constituting the antistatic portion 4 .

[0086] Specifically, the first sub-conductive dielectric layer 51 and the second sub-conductive dielectric layer 52 are the same film layer, which is formed by patterning the conductive dielectric layer 5 .

[0087] Preferably, the pattern of transparent conductive layer 2 constituting antistatic portion 4 has a portion extending beyond the pattern of metal conductive layer 3 .

[0088] An embodiment of the present invention further provides a display device, comprising any one of the display substrates described above.

[0089] Based on the same inventive concept, the embodiment of the present application also provides a display device, including the above-mentioned display panel provided in the embodiment of the present application. The display device can be: any product or component with a display function, such as a tablet computer, a television, a display, a laptop computer, a digital photo frame, etc. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be repeated here, nor should they be used as limitations on the present application. The implementation of the display device can refer to the embodiment of the above-mentioned packaging structure, and the repeated parts will not be repeated.

[0090] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display substrate, characterized in that: The display substrate comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a fan-out area; The display substrate comprises a base substrate, a transparent conductive layer and a metal conductive layer sequentially stacked on the base substrate; the transparent conductive layer has no pattern in the fan-out area; The fan-out region includes a fan-out trace formed by a pattern of the metal conductive layer; The display substrate further comprises a first sub-conductive medium layer located in the fan-out region; The first sub-conductive medium layer is located between the film layer where the fan-out wiring is located and the substrate.

2. The display substrate according to claim 1, characterized in that: The display area includes a gate line formed by stacked patterns of the metal conductive layer and the transparent conductive layer, a common electrode formed by the pattern of the transparent conductive layer, and a common electrode line formed by a pattern of the metal conductive layer stacked on the common electrode.

3. The display substrate according to claim 2, characterized in that: The pattern of the transparent conductive layer constituting the gate line has a portion extending out of the pattern of the metal conductive layer.

4. The display substrate according to claim 3, characterized in that: The non-display area includes a static electricity lead-out area, an antistatic portion formed by a pattern of the metal conductive layer and a pattern of the transparent conductive layer stacked in layers, and the antistatic portion is located in the static electricity lead-out area.

5. The display substrate according to claim 4, characterized in that: The display substrate further comprises a second sub-conductive medium layer located in the static electricity lead-out area; The second sub-conductive medium layer is located between the metal conductive layer and the transparent conductive layer constituting the anti-static portion.

6. The display substrate according to claim 5, characterized in that: The pattern of the transparent conductive layer constituting the antistatic portion has a portion extending beyond the pattern of the metal conductive layer.

7. A method for manufacturing a display substrate, characterized in that: The display substrate comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a fan-out area; The production method comprises: Providing a substrate; Using a mask process, forming a transparent conductive layer without a pattern in the fan-out area on the base substrate; forming a metal conductive layer covering the transparent conductive layer on the base substrate; A photoresist layer is formed on the metal conductive layer, and the photoresist layer is patterned by a mask process to obtain a patterned mask layer, wherein the patterned mask layer includes a pattern shielding area and a pattern thinning area, wherein the pattern shielding area at least covers the fan-out wiring to be formed, and the pattern thinning area at least covers the area between the fan-out wirings; The metal conductive layer and the transparent conductive layer are etched by shielding with the patterned mask layer, so as to form a fan-out wiring in the fan-out area.

8. The method according to claim 7, characterized in that: The pattern shielding area also covers the gate line and the common electrode line to be formed, and the pattern thinning area also covers the common electrode to be formed; The metal conductive layer and the transparent conductive layer are etched by shielding with the patterned mask layer to form a fan-out wiring in the fan-out area, specifically including: By shielding the patterned mask layer, the metal conductive layer and the transparent conductive layer are etched one by one in sequence to form gate lines and common electrodes in the display area; Thinning the patterned mask layer to remove the pattern thinning area; The metal conductive layer is subjected to secondary etching by shielding with the thinned patterned mask layer, so as to form a common electrode line located on the common electrode in the display area and to form the fan-out wiring in the fan-out area.

9. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 6.

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