A ring gate transistor and a method of manufacturing the same

Abstract

The application discloses a ring gate transistor and a manufacturing method thereof, and relates to the technical field of semiconductors, which is used for improving the working performance of the ring gate transistor while suppressing the parasitic channel leakage of the ring gate transistor. The ring gate transistor and the manufacturing method thereof comprise a substrate, a stack structure, a gate stack, an isolation side wall and a leakage suppression structure. The stack structure is formed on the substrate. The stack structure comprises a source region, a drain region and at least one layer of nanowires or sheets between the source region and the drain region. The gate stack surrounds the periphery of the at least one layer of nanowires or sheets. The isolation side wall is formed at least on both sides of the gate stack along the length direction. The leakage suppression structure is formed on the substrate. The leakage suppression structure is located below the at least one layer of nanowires or sheets and below the part of the isolation side wall corresponding to the at least one layer of nanowires or sheets. The leakage suppression structure is doped with impurities opposite to the conduction type of the ring gate transistor. The bottom of the source region and the bottom of the drain region are at least flush with the bottom of the leakage suppression structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a gate-ring transistor and its manufacturing method. Background Technology

[0002] With the development of semiconductor technology, gate-around transistors (GMT-A) have emerged. Because the gate stack of a GMT-A is formed not only on the top and sidewalls of the channel, but also on the bottom of the channel, it has stronger gate control capability compared with planar transistors and fin field-effect transistors, which is beneficial for suppressing short-channel effects.

[0003] However, while existing manufacturing methods can suppress parasitic channel leakage current in gate-around transistors, they also lead to a decrease in the performance of gate-around transistors. Summary of the Invention

[0004] The purpose of this invention is to provide a gate-around transistor and a method for manufacturing the same, which improves the performance of the gate-around transistor while suppressing parasitic channel leakage current.

[0005] To achieve the above objectives, the present invention provides a ring-gate transistor, the ring-gate transistor comprising: a substrate,

[0006] A stacked structure is formed on a substrate. The stacked structure includes a source region, a drain region, and at least one layer of nanowires or sheets located between the source region and the drain region, wherein the at least one layer of nanowires or sheets is in contact with the source region and the drain region respectively, and there is a gap between the at least one layer of nanowires or sheets and the substrate.

[0007] The gate is stacked around the periphery of at least one layer of nanowires or sheets.

[0008] Isolation sidewalls are formed at least on both sides of the grid stack along its length.

[0009] A leakage suppression structure is formed on the substrate. The leakage suppression structure is located below at least one nanowire or sheet layer and below the portion of the isolation sidewall corresponding to the at least one nanowire or sheet layer. The leakage suppression structure is doped with impurities of the opposite conductivity type to that of the gate-to-ring transistor. The bottoms of both the source and drain regions are at least flush with the bottom of the leakage suppression structure.

[0010] Compared to existing technologies, the gate-around transistor provided by this invention has a leakage suppression structure formed on the substrate. Furthermore, this leakage suppression structure is located below at least one nanowire or sheet layer and below the portion of the isolation sidewall corresponding to the at least one nanowire or sheet layer. In other words, the leakage suppression structure is located between the at least one nanowire or sheet layer and the substrate, and between the portion of the isolation sidewall corresponding to the nanowire or sheet layer and the substrate. In this case, even if there is a gap between the substrate and the nanowire or sheet layer, and the gate stack surrounds the outer periphery of the at least one nanowire or sheet layer through this gap, the leakage suppression structure can still separate the gate stack from the substrate. Additionally, because the leakage suppression structure is doped with impurities of the opposite conductivity type to that of the gate-around transistor, leakage current in the parasitic channel of the gate-around transistor can be suppressed using a reverse-biased PN junction.

[0011] Furthermore, the leakage suppression structure is formed on the substrate, meaning it is an additional structure formed on the substrate. Moreover, the leakage suppression structure is located below the nanowire or sheet. Based on this, in the actual manufacturing process of the gate-around transistor provided by this invention, the leakage suppression structure can be obtained by pre-forming a leakage suppression layer on the substrate and etching it before forming the channel layer for manufacturing the nanowire or sheet on the substrate. In this case, since the channel layer is formed after the leakage suppression layer, impurities will not enter the channel layer when doping the leakage suppression layer, thus preventing the presence of such impurities in the channel layer and ensuring that the nanowire or sheet formed based on the channel layer has a high carrier mobility. Simultaneously, the quality of the channel layer will not be affected by impurities, facilitating the obtaining of high-quality nanowires or sheets, thereby improving the operating performance of the gate-around transistor.

[0012] Furthermore, the bottoms of both the source and drain regions of the gate-around transistor are at least flush with the bottom of the leakage suppression structure. In other words, the bottom heights of the source and drain regions are less than or equal to the bottom height of the leakage suppression structure. In this case, the source and drain regions are only adjacent to the leakage suppression structure in a plane parallel to the substrate surface, and not adjacent to it along the substrate thickness direction. This prevents the source and drain regions from forming highly doped PN junctions distributed along the substrate thickness direction with the leakage suppression structure, avoiding increased leakage current in the source and drain regions and ensuring good conductivity of the gate-around transistor.

[0013] The present invention also provides a method for manufacturing a gate-around transistor, the method comprising:

[0014] Provide a substrate.

[0015] A stacked structure, isolation sidewalls, a leakage suppression structure, and a gate stack are formed on a substrate. The stacked structure includes a source region, a drain region, and at least one nanowire or sheet located between the source and drain regions. The at least one nanowire or sheet contacts the source and drain regions respectively, and a gap exists between the at least one nanowire or sheet and the substrate. The gate stack surrounds the outer periphery of the at least one nanowire or sheet. Isolation sidewalls are formed on at least two sides of the gate stack along its length. The leakage suppression structure is located below the at least one nanowire or sheet and below the corresponding portions of the isolation sidewalls. The leakage suppression structure is doped with impurities of the opposite conductivity type to that of the gate-to-ring transistor. The bottoms of both the source and drain regions are at least flush with the bottom of the leakage suppression structure.

[0016] Compared with the prior art, the manufacturing method of the ring gate transistor provided by the present invention has the same beneficial effects as the ring gate transistor provided by the present invention, and will not be repeated here. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0018] Figure 1 Part (1) is a cross-sectional view of the fin structure after it has been treated with an anti-penetration injection process; Figure 1 Part (2) is a cross-sectional view of the structure after the ring gate transistor is formed based on the fin structure;

[0019] Figure 2 This is a schematic diagram of the structure after forming a leakage suppression layer and at least one stacked layer on the substrate in an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of the first structure after the fin is formed in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of the second structure after the fin is formed in an embodiment of the present invention;

[0022] Figure 5 Part (1) is a cross-sectional view of the structure along the B-B' direction after the fin is formed in an embodiment of the present invention;

[0023] Figure 5 Parts (2) and (3) are cross-sectional views of two structures along the A-A' direction after the fin is formed in the embodiment of the present invention;

[0024] Figure 6 Parts (1), (2), and (3) are schematic diagrams of three structures after the shallow trench isolation structure in the embodiments of the present invention;

[0025] Figure 7 This is a schematic diagram of the structure after the sacrificial fence and isolation sidewalls are formed in an embodiment of the present invention;

[0026] Figure 8 for Figure 7 The cross-sectional view of the structure shown along the B-B' direction;

[0027] Figure 9 Parts (1), (2) and (3) in the present invention are three structural schematic diagrams of the leakage suppression structure obtained by etching the top of the fin located in the source formation region and the drain formation region down to the patterned leakage suppression layer in the embodiment of the present invention.

[0028] Figure 10 This is a schematic diagram of the structure after the notch is formed in an embodiment of the present invention;

[0029] Figure 11 This is a schematic diagram of the structure after the inner wall is formed in an embodiment of the present invention;

[0030] Figure 12 Parts (1) and (2) are cross-sectional views of two structures along the B-B' direction after the source region and drain region are formed in the embodiment of the present invention;

[0031] Figure 13 This is a cross-sectional view of the structure along the B-B' direction after the dielectric layer is formed in an embodiment of the present invention;

[0032] Figure 14 This is a schematic diagram of the structure after removing the sacrificial gate in an embodiment of the present invention;

[0033] Figure 15 This is a cross-sectional view of the structure along the B-B' direction after the removal of the sacrificial layer within the release area in an embodiment of the present invention;

[0034] Figure 16 Parts (1) and (2) are cross-sectional views of two structures of the gate ring transistor along the B-B' direction provided in the embodiments of the present invention;

[0035] Figure 17 A cross-sectional view of the third type of gate ring transistor along the B-B' direction provided in this embodiment of the invention;

[0036] Figure 18 This is a flowchart illustrating a method for manufacturing a gate-ring transistor according to an embodiment of the present invention.

[0037] Reference numerals: 11 is substrate, 12 is leakage suppression layer, 121 is doped layer, 122 is intrinsic layer, 13 is stacked layer, 131 is sacrificial layer, 132 is channel layer, 14 is fin, 15 is shallow trench isolation structure, 16 is source formation region, 17 is drain formation region, 18 is transition region, 19 is sacrificial gate, 20 is isolation sidewall, 21 is leakage suppression structure, 211 is doped region, 212 is intrinsic region, 22 is notch, 23 is inner sidewall, 24 is source region, 25 is drain region, 26 is dielectric layer, 27 is release region, 28 is nanowire or sheet, 29 is gate stack, 291 is gate dielectric layer, 292 is gate, 30 is fin structure, 31 is barrier layer, and 32 is central region. Detailed Implementation

[0038] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0039] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0040] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0042] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0043] With the development of semiconductor technology, gate-around transistors (GMT-A) have emerged. Because the gate stacking structure of a GMT-A is formed not only on the top and sidewalls of the channel, but also on the bottom of the channel, it has stronger gate control capability compared with planar transistors and fin field-effect transistors. This helps to suppress short-channel effects and gives GMT-A higher operating performance.

[0044] In the actual fabrication of gate-around transistors, at least one stacked layer needs to be formed on the substrate. Each stacked layer includes a sacrificial layer and a channel layer located on the sacrificial layer. The stacked layer is then etched downwards from the top to a portion of the substrate to form a fin-like structure. For example... Figure 1 As shown, after forming a shallow trench isolation structure 15 on the portion of the substrate 11 exposed outside the fin structure 30, impurity ions with a conductivity type opposite to that of the gate ring transistor are typically implanted into the fin structure 30 through a punch-through implantation process to form a barrier layer 31 in the lower middle part of the fin structure 30 (i.e., the etched portion of the substrate 11 included in the fin structure 30), thereby using the highly doped barrier layer 31 to suppress leakage current in the parasitic channel.

[0045] However, before forming the aforementioned barrier layer, an etched channel layer has already been formed on the substrate. This channel layer is used to fabricate nanowires or sheets for the gate-around-the-loop transistor. In this case, during the process of implanting impurity ions into the lower part of the fin structure to form the barrier layer using a punch-through implantation process, implanted impurity ions may be present in the etched channel layer, leading to a decrease in carrier mobility within the nanowires or sheets of the gate-around-the-loop transistor. Furthermore, because a barrier layer needs to be formed in the lower part of the fin structure, the implantation energy of impurity ions is relatively high. Therefore, when performing the aforementioned punch-through implantation process, the etched channel layer may be damaged, thereby affecting the quality of the nanowires or sheets and reducing the conductivity of the gate-around-the-loop transistor.

[0046] Furthermore, when the channel width of a gate-around transistor (GMT-A) is relatively wide, it is difficult to solve the problem of parasitic channel leakage in the GMT-A using the aforementioned anti-punch-through injection process. Specifically, for example... Figure 1As shown, during the fabrication of the gate-around transistor (GOT), the fin structure 30 formed on the substrate 11 also has a relatively wide channel due to the wider channel width of the GOT. Therefore, when impurity ions are implanted into the fin structure 30 using a punch-through implantation process, the impurity ions have difficulty entering the central region 32 of the fin structure 30 along its width direction (parallel to the A-A' direction), meaning that the central region 32 of the fin structure 30 along its width direction does not completely form a barrier layer 31. In this situation, after applying an appropriate voltage to the gate stack 29 of the GOT, the source and drain regions can not only conduct through the channel, but the aforementioned central region 32 also suffers from parasitic channel leakage, thereby reducing the operating performance of the GOT.

[0047] To address the aforementioned technical problems, embodiments of the present invention provide a gate-around transistor and a method for manufacturing the same. In the gate-around transistor provided by the present invention, a leakage suppression structure is located between at least one nanowire or sheet layer and the substrate, and between the isolation sidewall and the corresponding portion of the nanowire or sheet and the substrate, to suppress leakage current in the parasitic channel using a reverse-biased PN junction. Furthermore, the leakage suppression structure is an additional structure formed on the substrate, and is located below the nanowire or sheet to prevent impurities from entering the nanowire or sheet when doping the leakage suppression layer used to fabricate the leakage suppression structure, thus ensuring that the nanowire or sheet has a high carrier mobility.

[0048] like Figure 16 and Figure 17 As shown, an embodiment of the present invention provides a gate-around transistor. The gate-around transistor includes a substrate 11, a stacked structure, a gate stack 29, an isolation sidewall 20, and a leakage suppression structure 21.

[0049] like Figure 16 and Figure 17 As shown, the stacked structure is formed on substrate 11. The stacked structure includes a source region 24, a drain region 25, and at least one nanowire or sheet 28 located between the source region 24 and the drain region 25. The at least one nanowire or sheet 28 contacts the source region 24 and the drain region 25, respectively, and has a gap between it and the substrate 11. A gate stack 29 surrounds the outer periphery of the at least one nanowire or sheet 28. Isolation sidewalls 20 are formed on at least two sides of the gate stack 29 along its length. A leakage suppression structure 21 is formed on substrate 11. The leakage suppression structure 21 is located below the at least one nanowire or sheet 28 and below the portions of the isolation sidewalls 20 corresponding to the at least one nanowire or sheet 28. The leakage suppression structure 21 is doped with impurities of the opposite conductivity type to that of the gate-around transistor. The bottoms of both the source region 24 and the drain region 25 are at least flush with the bottom of the leakage suppression structure 21.

[0050] Specifically, the substrate can be any semiconductor substrate such as a silicon substrate, a germanium-silicon substrate, or a germanium substrate. Furthermore, the substrate can have an active region and an isolation region. The active region is doped with an impurity of the opposite conductivity type to that of the gate-around transistor. For example, in the case of an NMOS transistor, the active region is doped with a P-type impurity (such as boron). As another example, in the case of a PMOS transistor, the active region is doped with an N-type impurity (such as phosphorus). The leakage suppression structure and the stacked structure are formed on the active region.

[0051] In some cases, such as Figure 11 As shown, the aforementioned gate-ring transistor may further include a shallow trench isolation structure 15 formed on the isolation region. The top height of the shallow trench isolation structure 15 is less than or equal to the top height of the leakage suppression structure 21. In this case, the shallow trench isolation structure 15 can isolate the source and drain regions of the gate-ring transistor provided in this embodiment of the invention from the source and drain regions of other transistors formed on the substrate 11, preventing them from being electrically connected to each other. Specifically, the thickness of the shallow trench isolation structure can be set according to actual needs. The material of the shallow trench isolation structure can be an insulating material such as SiN, Si3N4, SiO2, or SiCO.

[0052] For stacked structures, the source and drain regions, as well as the nanowires or sheets, can be made of semiconductor materials such as silicon, silicon germanium, or germanium. The number of nanowires or sheets in the stacked structure can be set according to actual needs and is not specifically limited here.

[0053] Among them, such as Figure 16 As shown, the bottoms of the source region 24 and drain region 25 of the gate-around transistor are at least flush with the bottom of the leakage suppression structure 21. That is, the bottom heights of the source region 24 and drain region 25 can be equal to or less than the bottom height of the leakage suppression structure 21. In both cases, the source region 24 and drain region 25 are only adjacent to the leakage suppression structure 21 in a plane parallel to the surface of the substrate 11, and not adjacent along the thickness direction of the substrate 11. This prevents the source region 24 and drain region 25 from forming highly doped PN junctions distributed along the thickness direction of the substrate 11 with the leakage suppression structure 21, avoiding increased leakage current in the source region 24 and drain region 25, and improving the conductivity of the gate-around transistor.

[0054] For gate stacking, such as Figure 16 and Figure 17As shown, the gate stack 29 may include a gate dielectric layer 291 and a gate 292 formed on the gate dielectric layer 291. The gate dielectric layer 291 surrounds the outer periphery of the nanowire or sheet 28. Alternatively, the gate dielectric layer may be additionally formed on the substrate (or shallow trench isolation structure) and the portion of the leakage suppression structure corresponding to the gate formation region. The thickness of the gate dielectric layer and the gate can be set according to actual needs and is not specifically limited here. The material of the gate dielectric layer can be an insulating material with a low dielectric constant, such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant, such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate can be a conductive material such as polysilicon, TiN, TaN, or TiSiN.

[0055] Regarding the aforementioned isolation sidewalls, such as Figure 14 , Figure 16 and Figure 17 As shown, the isolation sidewalls 20 can be formed only on both sides of the gate stack 29 along its length (parallel to the B-B' direction). Alternatively, the isolation sidewalls can surround the circumference of the gate stack. The thickness and material of the isolation sidewalls can be set according to actual needs. For example, the material of the isolation sidewalls can be insulating materials such as silicon nitride. Specifically, such as... Figure 14 , Figure 16 and Figure 17 As shown, the portion of the isolation sidewall 20 corresponding to the nanowire or sheet 28 is the portion of the isolation sidewall 20 formed on the top nanowire or sheet 28. Furthermore, as... Figure 10 and Figure 11 As shown, the isolation sidewall 20 may also have a portion formed on the substrate 11 (or the shallow trench isolation structure 15).

[0056] For the aforementioned leakage current suppression structure, the distribution of impurities within the structure can be configured according to actual requirements. In one example, such as... Figure 16 As shown, along the thickness direction of the substrate 11, all regions of the leakage current suppression structure 21 can be doped with the aforementioned impurities. In another example, along the thickness direction of the substrate 11, some regions of the leakage current suppression structure 21 may be doped with the aforementioned impurities, while other regions may not be doped with the aforementioned impurities. In this case, the number and arrangement of the doped and undoped regions can also be set according to actual needs. For example: Figure 17As shown, along the thickness direction of the substrate 11, the leakage suppression structure 21 may include a doped portion 211 and an intrinsic portion 212 located on the doped portion 211. The doped portion 211 is doped with the aforementioned impurities. Alternatively, along the thickness direction of the substrate, the leakage suppression structure may include a first intrinsic portion, a second intrinsic portion, and a doped portion located between the first intrinsic portion and the second intrinsic portion. This doped portion is doped with the aforementioned impurities. In both cases, the undoped portion of the leakage suppression structure is closer to the nanowire or sheet. Based on this, as... Figures 2 to 17 As shown, during the manufacturing process of the gate-ring transistor provided in this embodiment of the invention, since the leakage suppression structure 21 is located below at least one nanowire or sheet 28, the sacrificial layer 131 and the channel layer 132 for manufacturing the nanowire or sheet 28 are formed on the leakage suppression layer 12 for manufacturing the leakage suppression structure 21. At this time, after the leakage suppression layer 12 and at least one sacrificial layer 131 and at least one channel layer 132 are formed, the presence of the intrinsic layer 122 in the leakage suppression layer 12 can prevent the doped layer 121 containing impurities from diffusing outwards into the sacrificial layer 131 and the channel layer 132 during subsequent high-temperature processes such as annealing. This further ensures that the carrier mobility of the nanowire or sheet 28 formed by the channel layer 132 is not affected by the aforementioned impurities, thereby improving the conductivity of the gate-ring transistor.

[0057] The type of impurities doped within the leakage current suppression structure can be set with reference to the conductivity type of the gate-around transistor. For example, when the gate-around transistor is a PMOS transistor, the leakage current suppression structure is doped with N-type impurities. As another example, when the gate-around transistor is an NMOS transistor, the leakage current suppression structure is doped with P-type impurities. Furthermore, the doping concentration within the leakage current suppression structure can be set according to the actual application scenario. For example, the doping concentration of the impurities in the leakage current suppression structure can be 1E18cm⁻¹. -3 Up to 2E19cm -3 Specifically, the doping concentration mentioned above refers to the doping concentration in the region doped with impurities within the leakage suppression structure. For example, in the case where the leakage suppression structure includes both the doped portion and the intrinsic portion, the doping concentration of the impurities within the doped portion is 1E18cm⁻¹. -3 Up to 2E19cm -3 .

[0058] The thickness and material of the leakage current suppression structure can be set according to actual needs, as long as it can suppress parasitic channel leakage current in the gate-ring transistor and can be applied to the gate-ring transistor provided in the embodiments of the present invention. For example, the thickness of the leakage current suppression structure can be 10nm to 40nm. For example, the material of the leakage current suppression structure can be Si. 1-x Ge x Semiconductor materials; where 0≤x≤1 (e.g., Si, Si0.3 Ge 0.7 Or Ge, etc.).

[0059] As can be seen from the above, such as Figure 16 and Figure 17 As shown, in the gate-around transistor provided in this embodiment of the invention, a leakage suppression structure 21 is formed on the substrate 11. This leakage suppression structure 21 is located below at least one nanowire or sheet 28 and below the portion of the isolation sidewall 20 corresponding to the at least one nanowire or sheet 28. In other words, the leakage suppression structure 21 is located between the at least one nanowire or sheet 28 and the substrate 11, and between the portion of the isolation sidewall 20 corresponding to the nanowire or sheet 28 and the substrate 11. In this case, even if there is a gap between the substrate 11 and the nanowire or sheet 28, and the gate stack 29 surrounds the outer periphery of the at least one nanowire or sheet 28 through this gap, the leakage suppression structure 21 can still separate the gate stack 29 from the substrate 11. Furthermore, since the leakage suppression structure 21 is doped with impurities of the opposite conductivity type to that of the gate-around transistor, leakage current in the parasitic channel can be suppressed using a reverse-biased PN junction.

[0060] In addition, such as Figures 2 to 17 As shown, the leakage suppression structure 21 is formed on the substrate 11, meaning that the leakage suppression structure 21 is an additional structure formed on the substrate 11. Furthermore, the leakage suppression structure 21 is located below the nanowire or sheet 28. Based on this, in the actual manufacturing process of the gate-around transistor provided in this embodiment of the invention, the leakage suppression structure 21 can be obtained by pre-forming a leakage suppression layer 12 for manufacturing the leakage suppression structure 21 on the substrate 11 and etching the leakage suppression layer 12 before forming the channel layer 132 for manufacturing the nanowire or sheet 28 on the substrate 11. In this case, since the channel layer 132 is formed after the leakage suppression layer 12, impurities will not enter the channel layer 132 when doping impurities into the leakage suppression layer 12. This helps to ensure that the aforementioned impurities are not present in the channel layer 132, thus ensuring that the nanowire or sheet 28 formed based on the channel layer 132 has a high carrier mobility. At the same time, the quality of the channel layer 132 will not be affected by doping impurities, which is conducive to obtaining high-quality nanowires or sheets 28, and thus to improving the working performance of the gate-around transistor.

[0061] In one example, such as Figure 16 and Figure 17 As shown, the gate-around transistor may further include an inner sidewall 23. Along the length of the gate stack 29, the inner sidewall 23 is located between the gate stack 29 and the source region 24, and between the gate stack 29 and the drain region 25. In this case, as... Figures 11 to 17As shown, the presence of the inner sidewall 23 helps to prevent the subsequent gate stack 29 surrounding the nanowire or sheet 28 from forming on the portion of the nanowire or sheet 28 covered by the sidewall, thus facilitating control of the length of the gate stack 29.

[0062] The inner wall can be made of insulating materials such as silicon dioxide or silicon nitride. The specific thickness of the inner wall can be set according to actual needs.

[0063] like Figure 18 As shown, this embodiment of the invention provides a method for manufacturing a gate-ring transistor. The following will describe a method based on... Figures 2 to 17 The illustrated perspective and cross-sectional views describe the manufacturing process. Specifically, the manufacturing method of this gate-ring transistor includes:

[0064] First, a substrate is provided. This substrate can be a semiconductor substrate such as a silicon substrate or a germanium-silicon substrate.

[0065] like Figures 2 to 17 As shown, a stacked structure, isolation sidewalls 20, a leakage suppression structure 21, and a gate stack 29 are formed on a substrate 11. The stacked structure includes a source region 24, a drain region 25, and at least one nanowire or sheet 28 located between the source region 24 and the drain region 25. The at least one nanowire or sheet 28 contacts the source region 24 and the drain region 25, respectively, and has a gap between the at least one nanowire or sheet 28 and the substrate 11. The gate stack 29 surrounds the outer periphery of the at least one nanowire or sheet 28. Isolation sidewalls 20 are formed on at least two sides of the gate stack 29 along its length. The leakage suppression structure 21 is located below the at least one nanowire or sheet 28 and below the portion of the isolation sidewall 20 corresponding to the at least one nanowire or sheet 28. The leakage suppression structure 21 is doped with impurities of the opposite conductivity type to that of the gate-to-ring transistor. The bottoms of both the source region 24 and the drain region 25 are at least flush with the bottom of the leakage suppression structure 21.

[0066] Specifically, the materials and specifications of the aforementioned stacked structure, isolation sidewalls, leakage suppression structure, and grid stack can be found in the previous text and will not be repeated here.

[0067] In one example, the substrate described above has an active region and an isolation region. In this case, forming a leakage suppression structure on the substrate may include the following steps:

[0068] like Figure 2 As shown, a leakage suppression layer 12 and at least one stack 13 are formed covering the substrate 11. Each stack 13 includes a sacrificial layer 131 and a channel layer 132 located on the sacrificial layer 131.

[0069] Specifically, the aforementioned leakage suppression layer is a film layer used to manufacture the leakage suppression structure. Therefore, information such as the thickness, material, and doping status of the leakage suppression layer can be determined by referring to the relevant information on the leakage suppression structure described above. For example: Figure 2 As shown, when the leakage suppression structure includes the doped portion and the intrinsic portion described above, the leakage suppression layer 12 may include a doped layer 121 and an intrinsic layer 122 located on the doped layer 121. The thickness of the intrinsic layer 122 can be set according to actual needs, as long as it can prevent impurities in the doped layer 121 from diffusing into the channel layer 132. For example, the thickness of the intrinsic layer 122 can be 0 to 10 nm.

[0070] For at least one stack, the channel layer included in the stack is a film layer used to fabricate the nanowires or sheets included in the gate-around transistor. Therefore, the number of layers formed on the leakage suppression layer is equal to the number of nanowires or sheets included in the gate-around transistor. The material and thickness of the channel layer are the same as the material and thickness of the nanowires or sheets. The thickness of the sacrificial layer can be set with reference to the specifications of the gate stack. The material of the sacrificial layer can be set according to the materials of the channel layer and the leakage suppression structure to prevent the nanowires or sheets and the leakage suppression structure from being affected when releasing the nanowires or sheets by removing part of the sacrificial layer, thereby improving the yield of the gate-around transistor. For example, the material of the aforementioned leakage suppression structure can be Si. 1-x Ge x The channel layer can be made of Si 1-y Ge y The sacrificial layer can be made of Si 1-z Ge z Where 0≤x≤1, 0≤y≤1, 0≤z≤1, |xz|≥0.2, |yz|≥0.2. Specifically, the materials of the above leakage suppression structure and the channel layer can be the same or different. For example, the material of the leakage suppression structure is Si. 0.2 Ge 0.8 The channel layer is made of Si, and the sacrificial layer is made of Si. 0.6 Ge 0.4 For example, the material of the leakage current suppression structure is Si. 0.5 Ge 0.5 The channel layer is made of Si. 0.5 Ge 0.5 The sacrificial layer is made of Si.

[0071] It is worth noting that when the leakage suppression structure is made of germanium-silicon, the leakage suppression layer is also made of germanium-silicon. In this case, the leakage suppression layer formed on the substrate can also serve as a strain buffer layer to provide stress to the film layer subsequently formed thereon for manufacturing at least one stacked layer, thereby generating strain in the nanowires or sheets formed based on the channel layer included in the stacked layer, improving the carrier mobility of the gate-around transistor and enhancing its driving performance.

[0072] In practical applications, the aforementioned leakage suppression layer and stack can be formed on a substrate using processes such as epitaxial growth. Since at least a portion of the leakage suppression layer is doped with impurities, an in-situ doping process can be used during epitaxial growth to dope the leakage suppression layer with an appropriate concentration of impurities, thereby improving the manufacturing efficiency of the gate-around transistor. Of course, other processes can also be used to form the aforementioned leakage suppression layer and stack.

[0073] like Figures 3 to 5 As shown, at least the leakage suppression layer 12 and at least one stacked layer are patterned to form fins 14 on the active region.

[0074] In practical applications, techniques such as self-aligned double exposure (SADP) can be used to etch from the top of the stacked layers downwards at least to the bottom of the leakage suppression layer, thereby obtaining fins located on the active region. For example, Figure 4 and Figure 5 As shown in section (3), only the leakage suppression layer 12 and the stack can be patterned. Figure 3 and Figure 5 As shown in parts (1) and (2) above, the stacked layers, leakage suppression layer 12, and part of the substrate 11 can be patterned. The specific objects of the patterning process during the formation of the fin 14 can be set according to the actual application scenario, and are not specifically limited here.

[0075] like Figure 6 As shown, a shallow trench isolation structure 15 is formed on the portion of the substrate 11 located in the isolation region. The top height of the shallow trench isolation structure 15 is less than or equal to the top height of the leakage suppression layer 12. The portion of the fin 14 exposed outside the shallow trench isolation structure 15 has a source formation region 16, a drain formation region 17, and a transition region 18 located between the source formation region 16 and the drain formation region 17.

[0076] In practical applications, processes such as chemical vapor deposition can be used to form a barrier material covering the isolation area and fins, followed by planarization. Then, the planarized barrier material undergoes an etch-back process until the top height of the remaining portion of the barrier material is less than or equal to the top height of the patterned leakage suppression layer, resulting in a shallow trench isolation structure. The material for the shallow trench isolation structure can be referenced above. Depending on the thickness of the shallow trench isolation structure, the portion of the fins exposed outside the structure can fall into several categories:

[0077] The first type, such as Figure 6 As shown in part (1), if the top height of the shallow trench isolation structure 15 is equal to the top height of the patterned leakage suppression layer 12, then the exposed portion of the fin 14 includes only at least one patterned stack.

[0078] The second type, such as Figure 6 As shown in part (2), if the top height of the shallow trench isolation structure 15 is less than the top height of the patterned leakage suppression layer 12 and less than the bottom height of the patterned leakage suppression layer 12, then the exposed portion of the fin 14 includes at least one patterned laminate and the portion of the leakage suppression layer 12 that is patterned and exposed outside the shallow trench isolation structure 15.

[0079] The third type, such as Figure 6 As shown in part (3), if the top height of the shallow trench isolation structure 15 is greater than 0 and less than or equal to the bottom height of the patterned leakage suppression layer 12, the exposed portion includes at least one patterned stack and the leakage suppression layer 12.

[0080] like Figure 9 As shown in parts (1), (2) and (3), the top of the portion of the fin located in the source formation region and the drain formation region is etched down to the bottom of the patterned leakage suppression layer to expose the portion of the active region located below the source formation region and the drain formation region, and the remaining portion of the leakage suppression layer forms the leakage suppression structure 21.

[0081] In practical applications, the process of forming the leakage current suppression structure varies depending on the gate stack formation process. For example, when using a back-gate process to form the gate stack, after forming the shallow trench isolation structure and before subsequent operations, the manufacturing method of the ring-gate transistor further includes the following steps: Figure 7 and Figure 8As shown, a sacrificial gate 19 and isolation sidewalls 20 are formed covering the outer periphery of the transition region 18. The isolation sidewalls 20 are located at least on both sides of the sacrificial gate 19 along its length. Specifically, a gate material for forming the sacrificial gate can be deposited on the formed structure using processes such as chemical vapor deposition. Then, a process such as dry etching can be used to etch the gate material, retaining the portion of the gate material covering the outer periphery of the transition region, to obtain the sacrificial gate. The gate material can be an easily removable material such as amorphous silicon or polycrystalline silicon. Figure 7 and Figure 8 As shown, after the sacrificial gate 19 is formed, an isolation sidewall 20 can be formed at least on the sidewall of the sacrificial gate 19 using the method described above. The material and thickness of the isolation sidewall 20 can be referred to the previous text.

[0082] like Figure 9 As shown, after obtaining the sacrificial gate 19 and the isolation sidewall 20, under the masking effect of the sacrificial gate 19 and the isolation sidewall 20, the top of the portion of the fin located in the source formation region and the drain formation region can be etched downwards to at least the bottom of the patterned leakage suppression layer. At this time, the remaining portion of the leakage suppression layer is located within and / or below the transition region.

[0083] It should be noted that, in order to ensure that the portion of the patterned leakage suppression layer located below the source and drain formation regions is completely removed, after etching to the bottom of the patterned leakage suppression layer, the portion of the substrate located below the source and drain formation regions can be etched further downwards.

[0084] As can be seen from the formation process of the leakage suppression structure described above, since the channel layer is formed after the leakage suppression layer, impurities will not enter the channel layer when doping the leakage suppression layer. This helps to prevent the presence of such impurities in the channel layer, ensuring that the nanowires or sheets formed based on the channel layer have high carrier mobility. At the same time, the quality of the channel layer will not be affected by impurities, which is beneficial for obtaining high-quality nanowires or sheets, and thus improving the operating performance of the gate-around transistor.

[0085] In one example, as described above, when the gate stack is formed using a back-gate process, after forming a leakage suppression structure in the remaining portion of the leakage suppression layer, and before forming a source region at least in the source formation region and a drain region at least in the drain formation region, the manufacturing method of the aforementioned gate-around transistor may further include the steps of: Figure 10 As shown, along the length of the gate stack, the portion of the sacrificial layer located within the transition region is selectively etched to cause the sidewalls of the remaining portion of the sacrificial layer to be recessed inward relative to the sidewalls of the remaining portion of the channel layer, thus obtaining a notch 22. Figure 11 As shown, an inner wall 23 is formed within the notch.

[0086] In practical applications, since the sacrificial layer, the leakage suppression structure, and the channel layer all have a certain etching selectivity, a selective etchant can be used to selectively etch only the portion of the sacrificial layer located within the transition region. Because the portions of the leakage suppression structure and the channel layer located within the transition region are not affected by the etchant, the sidewalls of the remaining portion of the sacrificial layer are recessed inward relative to the sidewalls of the remaining portion of the channel layer, thus creating a notch. Then, processes such as chemical vapor deposition can be used to form inner sidewalls within the notch.

[0087] It should be noted that if, during the subsequent release of nanowires or sheets, only the portion of the sacrificial layer located in the release area is removed without affecting the portion of the sacrificial layer covered by the isolation sidewall, or if the length requirement of the gate stack is not strict, the aforementioned inner sidewall may not be necessary.

[0088] In one example, as described above, when the gate stack is formed using a back gate, after forming a leakage suppression structure in the remaining portion of the leakage suppression layer, the manufacturing method of the above-described gate-ring transistor further includes the following steps:

[0089] like Figure 12 As shown, a source region 24 is formed at least within the source formation region, and a drain region 25 is formed at least within the drain formation region. Specifically, epitaxial growth or other processes can be used to form the source region 24 within the source formation region and the drain region 25 within the drain formation region. The source region 24 and the drain region 25 can be formed simultaneously or in stages.

[0090] In some cases, such as Figure 13 As shown, after forming the source region 24 and drain region 25, a dielectric layer 26 covering the substrate 11 can be formed using processes such as physical vapor deposition and chemical mechanical polishing. The top of the dielectric layer 26 is flush with the top of the sacrificial gate 19 to prevent the source region 24 and drain region 25 from being affected by etching and cleaning operations during subsequent removal of the sacrificial gate 19 and the remaining portion of the sacrificial layer, thereby improving the yield of the gate-around transistor.

[0091] like Figure 14 and Figure 15 As shown, the sacrificial gate and the portion of the sacrificial layer covered by the release region 27 are removed, so that the portion of each channel layer located within the transition region forms the corresponding nanowire or sheet 28. The release region 27 is the region released after the sacrificial gate is removed.

[0092] In practical applications, dry or wet etching processes can be used to remove the portion of the sacrificial gate and sacrificial layer covered by the released area.

[0093] like Figure 16 and Figure 17As shown, a gate stack 29 is formed around at least one layer of nanowires or sheets 28.

[0094] For example, gate stacks can be formed using processes such as atomic layer deposition. The specific structure and materials of the gate stack can be found in the preceding text.

[0095] It should be noted that, besides the leakage current suppression structure, the above-mentioned stacked structure, isolation sidewalls, and grid stacks can be formed in various ways. How to form these structures is not the main feature of this invention; therefore, this specification only provides a brief description to enable those skilled in the art to easily implement the invention. Those skilled in the art can certainly conceive of other ways to manufacture the above-mentioned structures.

[0096] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0097] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A gate-ring transistor, characterized in that, include: Substrate, A stacked structure is formed on the substrate; the stacked structure includes a source region, a drain region, and at least one layer of nanowires or sheets located between the source region and the drain region, the at least one layer of nanowires or sheets being in contact with the source region and the drain region respectively, and having a gap between the at least one layer of nanowires or sheets and the substrate; The gate stack surrounds the outer periphery of the at least one layer of nanowires or sheets through the gaps; Isolation sidewalls are formed at least on both sides of the grid stack along its length; A leakage suppression structure is formed on the substrate; the leakage suppression structure is located below the at least one nanowire or sheet and below the portion of the isolation sidewall corresponding to the at least one nanowire or sheet; the leakage suppression structure is doped with impurities of the opposite conductivity type to the gate-ring transistor; the bottoms of the source region and the drain region are at least flush with the bottom of the leakage suppression structure; the thickness of the leakage suppression structure is 10 nm to 40 nm; the material of the leakage suppression structure is Si. 1-x Ge x , 0≤x≤1; Along the thickness direction of the substrate, the leakage suppression structure includes a doped portion and an intrinsic portion located on the doped portion; the doped portion is doped with the impurity, and the doping concentration of the impurity in the doped portion is 1E18cm⁻¹. -3 Up to 2E19cm -3 The thickness of the intrinsic part is 0 to 10 nm.

2. The gate-ring transistor according to claim 1, characterized in that, The ring-gate transistor further includes an inner sidewall; along the length of the gate stack, the inner sidewall is located between the gate stack and the source region, and between the gate stack and the drain region.

3. The gate-ring transistor according to claim 1 or 2, characterized in that, The substrate has an isolation region and an active region; the leakage suppression structure and the stacked structure are formed on the active region; The gate ring transistor further includes a shallow trench isolation structure formed on the isolation region; the top height of the shallow trench isolation structure is less than or equal to the top height of the leakage current suppression structure.

4. A method for manufacturing a gate-ring transistor, characterized in that, include: Provide a substrate; A stacked structure, isolation sidewalls, leakage suppression structure, and gate stack are formed on the substrate; the stacked structure includes a source region, a drain region, and at least one layer of nanowires or sheets located between the source region and the drain region, the at least one layer of nanowires or sheets contacting the source region and the drain region respectively, and a gap is formed between the at least one layer of nanowires or sheets and the substrate; the gate stack surrounds the outer periphery of the at least one layer of nanowires or sheets through the gap; the isolation sidewalls are formed on at least two sides of the gate stack along the length direction; The leakage suppression structure is located below the at least one nanowire or sheet layer and below the portion of the isolation sidewall corresponding to the at least one nanowire or sheet layer; the leakage suppression structure is doped with an impurity of the opposite conductivity type to that of the gate-to-ring transistor; the bottoms of the source region and the drain region are at least flush with the bottom of the leakage suppression structure; along the thickness direction of the substrate, the leakage suppression structure includes a doped portion and an intrinsic portion located on the doped portion; the doped portion is doped with the impurity; The thickness of the leakage current suppression structure is 10 nm to 40 nm; the material of the leakage current suppression structure is Si. 1-x Ge x , 0≤x≤1; the doping concentration of the impurities in the doped portion is 1E18cm. -3 Up to 2E19cm -3 The thickness of the intrinsic part is 0 to 10 nm.

5. The method for manufacturing a gate-ring transistor according to claim 4, characterized in that, The substrate has an active region and an isolation region; Forming the leakage suppression structure on the substrate includes: A leakage suppression layer and at least one stack are formed covering the substrate; each of the stacks includes a sacrificial layer and a channel layer located on the sacrificial layer; At least the leakage suppression layer and the at least one stacked layer are patterned to form fins on the active region; A shallow trench isolation structure is formed on the portion of the substrate located in the isolation region; the top height of the shallow trench isolation structure is less than or equal to the top height of the leakage suppression layer; the portion of the fin exposed outside the shallow trench isolation structure has a source formation region, a drain formation region, and a transition region located between the source formation region and the drain formation region; The top of the portion of the fin located in the source formation region and the drain formation region is etched downwards at least to the bottom of the patterned leakage suppression layer to expose the portion of the active region located below the source formation region and the drain formation region, and the remaining portion of the leakage suppression layer forms the leakage suppression structure.

6. The method for manufacturing a gate-to-ring transistor according to claim 5, characterized in that, After forming a shallow trench isolation structure on the portion of the substrate located in the isolation region, and before etching downwards at least from the top of the portion of the fin located in the source formation region and the drain formation region to the bottom of the patterned leakage suppression layer, the method for manufacturing the gate ring transistor further includes: A sacrificial fence and an isolation sidewall are formed covering the outer perimeter of the transition zone; the isolation sidewall is located at least on both sides of the sacrificial fence along its length. After the remaining portion of the leakage suppression layer forms the leakage suppression structure, the manufacturing method of the gate ring transistor further includes: The source region is formed at least within the source formation region, and the drain region is formed at least within the drain formation region; The sacrificial gate and the portion of the sacrificial layer covered by the release region are removed, such that the portion of each channel layer located within the transition region forms the corresponding layer of nanowires or sheets; the release region is the region released after the sacrificial gate is removed; The gate stack is formed around at least one layer of nanowires or sheets.

7. The method for manufacturing a gate-to-ring transistor according to claim 6, characterized in that, After the remaining portion of the leakage suppression layer forms the leakage suppression structure, before forming the source region at least in the source formation region and the drain region at least in the drain formation region, the manufacturing method of the ring-gate transistor further includes: Along the length of the gate stack, the portion of the sacrificial layer located in the transition region is selectively etched to make the sidewalls of the remaining portion of the sacrificial layer recessed inward relative to the sidewalls of the remaining portion of the channel layer, thus obtaining a notch; An inner wall is formed within the notch.

8. The method for manufacturing a gate-ring transistor according to any one of claims 5 to 7, characterized in that, The channel layer is made of Si. 1-y Ge y The sacrificial layer is made of Si. 1-z Ge z Where 0≤y≤1, 0≤z≤1, |xz|≥0.2, |yz|≥0.

2.

9. The method for manufacturing a gate-to-ring transistor according to any one of claims 5 to 7, characterized in that, The process for forming the leakage suppression layer includes epitaxial growth and in-situ doping.

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