Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, wherein the semiconductor structure comprises: a substrate comprising a first region and a second region; a first fin structure on the first region and a second fin structure on the second region, the first fin structure comprising a plurality of first channel layers with a first spacing between adjacent first channel layers, the second fin structure comprising a plurality of second channel layers with a second spacing between adjacent second channel layers; a first gate structure on the first fin structure of the first region and within the first spacing, and a second gate structure on the second fin structure of the second region and within the first spacing; an opening between the first gate structure and the second gate structure, a top surface of the opening being higher than or flush with top surfaces of the first gate structure and the second gate structure; and an isolation structure within the opening, the isolation structure enclosing the opening into a closed cavity. The semiconductor structure has reduced parasitic capacitance and improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] FinFET (Fin Field-Effect Transistor) architecture is the mainstay of the semiconductor industry today. However, with the continuous miniaturization of devices, when the channel length reaches a certain value, the FinFET structure cannot provide sufficient electrostatic control and sufficient drive current. Therefore, nanosheet structures, namely gate-all-around (GAA) technology, were introduced. Compared with FinFET, the gate-all-around characteristic of nanosheets provides excellent channel control capabilities. At the same time, the excellent three-dimensional distribution of the channel optimizes the effective drive current per unit area.

[0003] With the increasing demand for smaller track heights, further reductions in cell height necessitate even smaller spacing between NMOS and PMOS devices within standard cells. However, for fin field-effect transistors and nanosheets, process limitations restrict the spacing between these NMOS and PMOS devices. To expand the miniaturization of these devices, an innovative architecture called the forksheet device has been proposed. The forksheet can be considered a natural extension of the nanosheet. Compared to nanosheets, the channel of the forksheet is controlled by a fork-shaped gate structure, achieved by introducing a "dielectric wall" between the NMOS and PMOS devices before gate patterning. This wall physically and electrically isolates the NMOS gate trench from the PMOS gate trench, significantly reducing the spacing between the NMOS and PMOS, resulting in better area and performance miniaturization for the forksheet.

[0004] However, the performance of current fork-shaped nanosheets still needs improvement. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which reduces the parasitic capacitance of the semiconductor structure by forming air sidewalls, thereby improving the performance of the semiconductor structure.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate, the substrate including a first region and a second region; a first fin structure located on the first region and a second fin structure located on the second region, the first fin structure including a plurality of first channel layers mutually discrete along the normal direction of the substrate surface, with a first spacing between adjacent first channel layers; the second fin structure including a plurality of second channel layers mutually discrete along the normal direction of the substrate surface, with a second spacing between adjacent second channel layers; a first gate structure located on the first region and a second gate structure located on the second region, the first gate structure being located on the first fin structure and... Within a first interval, the second gate structure is located on the second fin structure and within the second interval; a first source / drain doped layer is located in the first region and a second source / drain doped layer is located in the second region, the first source / drain doped layer is located within the first fin structure on both sides of the first gate structure, and the second source / drain doped layer is located within the second fin structure on both sides of the second gate structure; an opening is located between the first gate structure and the second gate structure, and the top surface of the opening is higher than or flush with the top surfaces of the first gate structure and the second gate structure; an isolation structure is located within the opening, and the isolation structure closes the opening into a sealed cavity.

[0007] Optionally, it may also include: a dielectric structure located on the substrate, the dielectric structure covering the first gate structure and the second gate structure.

[0008] Optionally, it further includes: a first plug and a second plug located on the first region, the first plug and the second plug being located within the dielectric structure, and the first plug being electrically connected to the top of the first gate structure, and the second plug being electrically connected to the first source / drain doped layer; a third plug and a fourth plug located on the second region, the third plug and the fourth plug being located within the dielectric structure, and the third plug being electrically connected to the top of the second gate structure, and the fourth plug being electrically connected to the second source / drain doped layer.

[0009] Optionally, the dielectric structure includes a first dielectric layer and a second dielectric layer, the top surface of the first dielectric layer is flush with the top surfaces of the first gate structure and the second gate structure, the second dielectric layer is located on the first dielectric layer, the top surface of the second dielectric layer is flush with the top surfaces of the first plug and the third plug, the opening is located inside the first dielectric layer, and the top surface of the opening is flush with the top surface of the first dielectric layer.

[0010] Optionally, the material of the first dielectric layer includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxynitride, and silicon oxynitride; the material of the second dielectric layer includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxynitride, and silicon oxynitride; and the material of the isolation structure includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxynitride, and silicon oxynitride.

[0011] Optionally, the medium structure includes a third medium layer, the top surface of which is flush with the top surfaces of the first plug and the third plug, the opening is located within the third medium layer, the opening is also located between the first plug and the third plug, and the top surface of the opening is flush with the top surfaces of the first plug and the third plug.

[0012] Optionally, the material of the third dielectric layer is the same as the material of the isolation structure, including one or more combinations of low-k dielectric materials, ultra-low-k dielectric materials, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxynitride, and silicon oxynitride.

[0013] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; forming a first fin structure on the first region and a second fin structure on the second region, the first fin structure including a plurality of first channel layers mutually separated along the normal direction of the substrate surface, with a first spacing between adjacent first channel layers, the second fin structure including a plurality of second channel layers mutually separated along the normal direction of the substrate surface, with a second spacing between adjacent second channel layers; forming a first gate structure on the first region and a second gate structure on the second region, the first gate structure being located on the first fin structure and within the first spacing, the second gate structure being located on the second fin structure and within the second spacing; forming an opening between the first gate structure and the second gate structure, the top surface of the opening being higher than or flush with the top surfaces of the first gate structure and the second gate structure; forming an isolation structure within the opening, the isolation structure closing the opening to form a sealed cavity.

[0014] Optionally, before forming the first fin structure and the second fin structure, the method further includes: forming a first initial fin structure on the first region and forming a second initial fin structure on the second region. The first initial fin structure includes a first sacrificial layer and a first channel layer alternately stacked along the normal direction of the substrate surface. The second initial fin structure includes a second sacrificial layer and a second channel layer alternately stacked along the normal direction of the substrate surface. An initial opening is provided between the first initial fin structure and the second initial fin structure. An initial isolation structure is formed within the initial opening.

[0015] Optionally, after forming the initial isolation structure and before forming the first gate structure and the second gate structure, the method further includes: forming a dummy gate structure on the first region and the second region, the dummy gate structure spanning the first initial fin structure, the second initial fin structure and the initial isolation structure; forming a first dielectric layer on the substrate, the first dielectric layer being located on the sidewall of the dummy gate structure; removing the dummy gate structure; forming a first gate opening in the first dielectric layer of the first region, the first gate opening exposing a portion of the sidewall surface of the first initial fin structure; and forming a second gate opening in the first dielectric layer of the second region, the second gate opening exposing a portion of the sidewall surface of the second initial fin structure.

[0016] Optionally, the method for forming the first fin structure and the second fin structure includes: removing the first sacrificial layer exposed by the first gate opening, forming a first gap between adjacent first channel layers, and forming the first fin structure; removing the second sacrificial layer exposed by the second gate opening, forming a second gap between adjacent second channel layers, and forming the second fin structure.

[0017] Optionally, the method for forming the first gate structure and the second gate structure includes: forming a first gate structure within the first gate opening and the first gap; and forming a second gate structure within the second gate opening and the second gap.

[0018] Optionally, after forming the pseudo-gate structure, the method further includes: forming a first source / drain doped layer in the first initial fin structure on both sides of the pseudo-gate structure, and forming a second source / drain doped layer in the second initial fin structure on both sides of the pseudo-gate structure.

[0019] Optionally, the method of forming the opening includes: removing the initial isolation structure, forming an opening between the first gate structure and the second gate structure, wherein the top surface of the opening is flush with the top surfaces of the first gate structure and the second gate structure.

[0020] Optionally, after forming the isolation structure, the method further includes: forming a second dielectric layer on the top surfaces of the first gate structure and the second gate structure; removing a portion of the second dielectric layer until the top surfaces of the first gate structure and the second gate structure are exposed, forming a first contact hole in the first region and a third contact hole in the second region; removing a portion of the second dielectric layer and the first dielectric layer until the top surfaces of the first source / drain doped layer and the second source / drain doped layer are exposed, forming a second contact hole in the first region and a fourth contact hole in the second region; forming a first plug in the first contact hole, a second plug in the second contact hole, a third plug in the third contact hole, and a fourth plug in the fourth contact hole.

[0021] Optionally, after forming the first gate structure and the second gate structure but before forming the opening, the method further includes: forming a second dielectric layer on the top surface of the first gate structure and the second gate structure; removing a portion of the second dielectric layer until the top surface of the first gate structure and the second gate structure is exposed, forming a first contact hole in the first region and a third contact hole in the second region; removing a portion of the second dielectric layer and the first dielectric layer until the top surface of the first source / drain doped layer and the second source / drain doped layer is exposed, forming a second contact hole in the first region and a fourth contact hole in the second region; forming a first plug in the first contact hole, a second plug in the second contact hole, a third plug in the third contact hole, and a fourth plug in the fourth contact hole.

[0022] Optionally, the method of forming the opening includes: removing the first dielectric layer and the second dielectric layer to expose the initial isolation structure; removing the initial isolation structure to form an opening between the first gate structure and the second gate structure, and between the first plug and the third plug, wherein the top surface of the opening is flush with the top surfaces of the first plug and the third plug.

[0023] Optionally, after forming the opening, the method further includes: forming a third dielectric layer on the substrate, the top surface of the third dielectric layer being flush with the top surfaces of the first plug and the third plug, and forming an isolation structure within the opening, the isolation structure closing the opening to form a sealed cavity.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0025] The semiconductor structure of the present invention has an isolation structure between the first gate structure and the second gate structure, and the isolation structure closes the opening into a sealed cavity. The isolation structure is used to isolate the devices formed on the first region and the second region. By forming a sealed cavity as an air sidewall while reducing the distance between the devices, the parasitic capacitance between the devices formed on the first region and the devices formed on the second region can be reduced due to the low dielectric constant of air, thereby improving the performance of the formed semiconductor structure.

[0026] The method for forming the technical solution of the present invention involves forming an opening between the first gate structure and the second gate structure after forming a first gate structure and a second gate structure. The top surface of the opening is higher than or flush with the top surfaces of the first gate structure and the second gate structure. Then, an isolation structure is formed within the opening, and the isolation structure closes the opening into a sealed cavity. The isolation structure is used to isolate the devices formed on the first region and the second region. By forming a sealed cavity as an air sidewall while reducing the distance between the devices, the low dielectric constant of air can reduce the parasitic capacitance between the devices formed on the first region and the devices formed on the second region, thereby improving the performance of the formed semiconductor structure. Attached Figure Description

[0027] Figure 1 This is a schematic cross-sectional view of a semiconductor structure in one embodiment;

[0028] Figures 2 to 14 This is a schematic diagram of the semiconductor formation process in one embodiment of the present invention;

[0029] Figures 15 to 20 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention. Detailed Implementation

[0030] As described in the background section, the performance of current forked nanosheets still needs improvement. This will be explained in conjunction with specific embodiments.

[0031] Figure 1 This is a schematic cross-sectional view of a semiconductor structure in one embodiment.

[0032] refer to Figure 1The system includes: a substrate 100, the substrate 100 including a first region I and a second region II; a first fin structure 111 located on the first region I and a second fin structure 112 located on the second region II; a first gate structure 121 located on the first region I, the first gate structure 121 being located on and surrounding the first fin structure 111; a second gate structure 122 located on the second region II, the second gate structure 122 being located on and surrounding the second fin structure 112; and an isolation structure 130 located between the first gate structure 121 and the second gate structure 122, wherein the first gate structure 121 and the second gate structure 122 expose the top surface of the isolation structure 130.

[0033] In the semiconductor structure, the first region I and the second region II can be used to form an NMOS device or a PMOS device. The isolation structure 130 physically and electrically isolates the NMOS gate trench from the PMOS gate trench. However, as the distance between the first region I and the second region II decreases, parasitic capacitance will exist between the first gate structure and the second gate structure. The material of the isolation structure is usually silicon nitride, silicon oxide, etc., and the dielectric constant of materials such as silicon nitride and silicon oxide is relatively large, which makes the parasitic capacitance of the semiconductor device relatively large, thereby affecting the electrical performance of the semiconductor device.

[0034] To address the aforementioned problems, this invention provides a semiconductor structure and a method for forming the same. By forming an isolation structure between a first gate structure and a second gate structure, and the isolation structure sealing the opening into a closed cavity, the closed cavity serves as an air sidewall. Since air has a very low dielectric constant, the distance between the first region I and the second region II can be reduced, thereby significantly decreasing the parasitic capacitance between adjacent first gate structures and second gate structures, which is beneficial for improving the performance of the formed semiconductor structure.

[0035] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 2 to 14 This is a schematic diagram of the semiconductor formation process in one embodiment of the present invention.

[0037] refer to Figure 2 A substrate 200 is provided, the substrate 200 including a first region I and a second region II.

[0038] The substrate 200 provides a process platform for the subsequent formation of semiconductor structures, and the first region I and the second region II are used for the subsequent formation of MOS devices.

[0039] In this embodiment, the first region I is used to form a PMOS device and the second region II is used to form an NMOS device; in other embodiments, the first region I can also be used to form an NMOS device and the second region II can also be used to form a PMOS device.

[0040] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon-germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0041] Next, a first fin structure is formed on the first region I and a second fin structure is formed on the second region II. The first fin structure includes a plurality of first channel layers that are mutually separated along the normal direction of the substrate surface, and there is a first interval between adjacent first channel layers. The second fin structure includes a plurality of second channel layers that are mutually separated along the normal direction of the substrate surface, and there is a second interval between adjacent second channel layers.

[0042] A first gate structure is formed on a first region I and a second gate structure is formed on a second region II. The first gate structure is located on the first fin structure and within a first interval, and the second gate structure is located on the second fin structure and within a second interval.

[0043] Please refer to the formation process of the first fin structure, the second fin structure, the first gate structure, and the second gate structure. Figures 2 to 10 .

[0044] Continue to refer to Figure 2 A first initial fin structure is formed on a first region I and a second initial fin structure is formed on a second region II, with an initial opening 201 between the first initial fin structure and the second initial fin structure.

[0045] The first initial fin structure includes a first sacrificial layer 202 and a first channel layer 203 stacked alternately along the normal direction of the substrate 200 surface, and the second initial fin structure includes a second sacrificial layer 204 and a second channel layer 205 stacked alternately along the normal direction of the substrate 200 surface.

[0046] The method of forming the first initial fin structure and the second initial fin structure includes: forming a stacked material structure (not shown) on a substrate 200, the stacked material structure including sacrificial material layers and channel material layers alternately stacked along the normal direction of the surface of the substrate 200, the sacrificial material layers being used for subsequent formation of a first sacrificial layer 202 and a second sacrificial layer 204, and the channel material layers being used for subsequent formation of a first channel layer 203 and a second channel layer 205; forming a mask layer (not shown) on the stacked material structure, the mask layer exposing a portion of the surface of the sacrificial material layers, the mask layer defining the position and size of the first initial fin structure and the second initial fin structure to be formed; using the mask layer as a mask, etching the sacrificial material layer, the channel material layer, and a portion of the thickness of the substrate 200 to form the first initial fin structure in a first region I, forming the second initial fin structure in a second region II, and forming an initial opening 201 between the first initial fin structure and the second initial fin structure.

[0047] In this embodiment, the first initial fin structure and the second initial fin structure further include a partially patterned substrate 200 at the bottom.

[0048] The sacrificial material layer is made of silicon or silicon-germanium; the channel material layer is made of silicon or silicon-germanium. The sacrificial material layer is made of a different material than the channel material layer, thus minimizing damage to the first channel layer 203 and the second channel layer 205 during the subsequent removal of the first sacrificial layer 202 and the second sacrificial layer 204. In this embodiment, the sacrificial material layer is made of silicon-germanium; the channel material layer is made of silicon.

[0049] Continue to refer to Figure 2 An isolation layer 206 is formed on the substrate 200. The isolation layer 206 is located on the sidewalls of a portion of the first initial fin structure and the second initial fin structure, and the top surface of the isolation layer 206 is lower than the top surface of the first initial fin structure and the second initial fin structure.

[0050] In this embodiment, the isolation layer 206 covers the sidewall surface of the substrate 200 at the bottom of the first initial fin structure and the second initial fin structure, which is patterned.

[0051] The method for forming the isolation layer 206 includes: forming an initial isolation film (not shown) on the substrate 200; planarizing the initial isolation film until the top surfaces of the first initial fin structure and the second initial fin structure are exposed; and continuing to etch back the initial isolation film to form the isolation layer 206.

[0052] The insulating layer 206 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbide. In this embodiment, the insulating layer 206 is made of silicon oxide.

[0053] refer to Figure 3 An initial isolation structure 207 is formed within the initial opening 201.

[0054] The method for forming the initial isolation structure 207 includes: forming an initial isolation material layer (not shown) within the initial opening 201, on the surface of the first initial fin structure and the surface of the second initial fin structure; removing the initial isolation material layer from the surface of the first initial fin structure and the surface of the second initial fin structure, and forming the initial isolation structure 207 within the initial opening 201, wherein the top surface of the initial isolation structure 207 is flush with the top surfaces of the first initial fin structure and the second initial fin structure.

[0055] The initial isolation structure 207 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the initial isolation structure 207 is made of silicon nitride.

[0056] The process for forming the initial isolation material layer includes: chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and heat treatment; the process for removing the initial isolation material layer from the surfaces of the first and second initial fin structures includes: wet etching or isotropic dry etching.

[0057] In this embodiment, the process for forming the initial isolation material layer includes atomic layer deposition (ALD). ALD has strong pore-filling capabilities and can form a dense and thin initial isolation material layer in the initial opening 201. This allows the formed initial isolation structure 207 to provide good support in subsequent processes and prevent the collapse of the first initial fin structure and the second initial fin structure.

[0058] refer to Figures 4 to 6 , Figure 4 This is a top view of a semiconductor structure omitting the first and second source / drain doped layers. Figure 5 yes Figure 4 A schematic diagram of the cross-sectional structure along the AA direction. Figure 6 yes Figure 4A cross-sectional structural diagram along the BB direction shows that after the initial isolation structure 207 is formed, a pseudo-gate structure 208 is formed on the first region I and the second region II. The pseudo-gate structure 208 spans the first initial fin structure, the second initial fin structure and the initial isolation structure 207.

[0059] The dummy gate structure 208 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) located on the dummy gate dielectric layer.

[0060] In this embodiment, the dummy gate dielectric layer is made of silicon oxide; in other embodiments, the dummy gate dielectric layer may also be made of silicon oxynitride.

[0061] In this embodiment, the material of the dummy gate layer is polycrystalline silicon.

[0062] Continue to refer to Figures 4 to 6 A first source / drain doped layer 209 is formed in the first initial fin structure on both sides of the pseudo-gate structure 208, and a second source / drain doped layer 210 is formed in the second initial fin structure on both sides of the pseudo-gate structure 208.

[0063] The method for forming the first source / drain doped layer 209 and the second source / drain doped layer 210 includes: using the pseudo-gate structure 208 as a mask, etching the first initial fin structure and the second initial fin structure, forming a first source / drain opening (not shown) in the first initial fin structure on both sides of the pseudo-gate structure 208, forming a second source / drain opening (not shown) in the second initial fin structure on both sides of the pseudo-gate structure 208; forming the first source / drain doped layer 209 in the first source / drain opening, and forming the second source / drain doped layer 210 in the second source / drain opening.

[0064] In this embodiment, the first source / drain doped layer 209 and the second source / drain doped layer 210 are formed by epitaxial growth process.

[0065] The first source / drain doped layer 209 contains first source / drain doped ions, and the second source / drain doped layer 210 contains second source / drain doped ions. When the first region I is used to form a P-type device, the material of the first source / drain doped layer includes silicon, germanium, or silicon-germanium; the first source / drain doped ions are P-type ions, including boron ions and BF ions. 2- The second source / drain doped layer is made of silicon, gallium arsenide, or indium gallium arsenide. The second source / drain doped ion is an N-type ion, including phosphorus ions or arsenic ions.

[0066] refer to Figure 7 and Figure 8 , Figure 7 and Figure 5 The view orientation is consistent. Figure 8 and Figure 6 With the view direction consistent, a first dielectric layer 211 is formed on the substrate 200, and the first dielectric layer 211 is located on the sidewall surface of the pseudo gate structure 208.

[0067] The method for forming the first dielectric layer 211 includes: forming a first dielectric material layer (not shown) on the substrate 200 and the sidewalls and top surface of the dummy gate structure 208; planarizing the first dielectric material layer until the top surface of the dummy gate structure 208 is exposed, thereby forming the first dielectric layer 211.

[0068] The material of the first dielectric layer 211 includes a dielectric material, which includes one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon oxynitride, and silicon oxycarbide.

[0069] In this embodiment, the material of the first dielectric layer 211 includes silicon oxide; the process for forming the first dielectric material layer includes chemical vapor deposition.

[0070] In this embodiment, the method further includes: planarizing the first dielectric layer 211 and the pseudo-gate structure 208 until the top surface of the initial isolation structure 207 is exposed, so that the top surfaces of the pseudo-gate structure 208, the first dielectric layer 211 and the initial isolation structure 207 are flush; this facilitates the subsequent removal of the initial isolation structure.

[0071] refer to Figure 9 and Figure 10 , Figure 9 and Figure 7 The view orientation is consistent. Figure 10 and Figure 8 With the view direction consistent, the pseudo-gate structure 208 is removed, a first gate structure 215 is formed on the first region I, and a second gate structure 216 is formed on the second region II.

[0072] In this embodiment, before forming the first gate structure 215 and the second gate structure 216, the method further includes: removing the dummy gate structure 208; forming a first gate opening (not shown) in the first dielectric layer 211 of the first region I, the first gate opening exposing a portion of the sidewall surface of the first initial fin structure; forming a second gate opening in the first dielectric layer 211 of the second region II, the second gate opening exposing a portion of the sidewall surface of the second initial fin structure; removing the first sacrificial layer 202 exposed by the first gate opening; forming a first gap 217 between adjacent first channel layers 203 to form a first fin structure; removing the second sacrificial layer 204 exposed by the second gate opening; forming a second gap 218 between adjacent second channel layers 205 to form a second fin structure.

[0073] In this embodiment, the process for removing the first sacrificial layer 202 and the second sacrificial layer 204 includes a wet etching process, which causes less damage to the first channel layer 203 and the second channel layer 205.

[0074] In this embodiment, the method for forming the first gate structure 215 and the second gate structure 216 includes: forming an initial gate structure (not shown) within a first gate opening, a first interval 217, a second gate opening, and a second interval 218, the initial gate structure spanning the first fin structure, the second fin structure, and the initial isolation structure 207; planarizing the initial gate structure until the top surface of the initial isolation structure 207 is exposed; forming a first gate structure 215 on a first region I, the first gate structure 215 being located on the first fin structure and within the first interval 217; and forming a second gate structure 216 on a second region II, the second gate structure 216 being located on the second fin structure and within the second interval 218.

[0075] The first gate structure 215 includes a first gate dielectric layer (not shown), a first work function layer (not shown) located on the first gate dielectric layer, and a first gate layer (not shown) located on the first work function layer; the second gate structure 216 includes a second gate dielectric layer (not shown), a second work function layer (not shown) located on the second gate dielectric layer, and a second gate layer (not shown) located on the second work function layer.

[0076] The materials of the first gate dielectric layer and the second gate dielectric layer include high dielectric constant materials, wherein the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes alumina or hafnium oxide; the material of the first work function layer includes one or more combinations of N-type work function materials and P-type work function materials, and the material of the second work function layer includes one or more combinations of N-type work function materials and P-type work function materials; the materials of the first gate layer and the second gate layer include metals, wherein the metals include tungsten.

[0077] refer to Figure 11 and Figure 12 , Figure 11 and Figure 9 The view orientation is consistent. Figure 12 and Figure 10 With the view direction consistent, the initial isolation structure 207 is removed, and an opening 219 is formed between the first gate structure 215 and the second gate structure 216. The top surface of the opening 219 is flush with the top surfaces of the first gate structure 215 and the second gate structure 216.

[0078] In this embodiment, the opening 219 provides space for the subsequent formation of the isolation structure.

[0079] In this embodiment, the process for removing the initial isolation structure 207 includes a dry etching process.

[0080] refer to Figure 13 and Figure 14 , Figure 13 and Figure 11 The view orientation is consistent. Figure 14 and Figure 12 With the views aligned, an isolation structure 220 is formed within the opening 219, which closes the opening 219 into a sealed cavity.

[0081] In this embodiment, the material of the isolation structure 220 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and silicon oxynitride nitride. The process for forming the isolation structure 220 includes a chemical vapor deposition process.

[0082] As the distance between the first region I and the second region II gradually decreases, the opening 219 has a high aspect ratio. When the isolation structure 220 is deposited using chemical vapor deposition, due to its poor via-filling ability, the isolation structure 220 will first seal the opening 219 from the top before completely filling it, thus sealing the opening 219 into a sealed cavity. The sealed cavity serves as an air sidewall. Since air has a low dielectric constant, the parasitic capacitance between adjacent first gate structures 215 and second gate structures 216 can be reduced, thereby improving the performance of the formed semiconductor structure.

[0083] Continue to refer to Figure 13 and Figure 14 After the isolation structure 220 is formed, a second dielectric layer 212 is formed on the first dielectric layer 211. The second dielectric layer 212 covers the first gate structure 215, the second gate structure 216 and the top surface of the isolation structure 220.

[0084] The material of the second dielectric layer 212 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and silicon oxynitride nitride. The process for forming the second dielectric layer 212 includes chemical vapor deposition, thermal treatment, or atomic layer deposition.

[0085] After forming the second dielectric layer 212, the method further includes: forming a first plug 221 in the second dielectric layer 212 of the first region I, the first plug 221 being electrically connected to the top of the first gate structure 215; forming a third plug 223 in the second dielectric layer 212 of the first region I, the third plug 223 being electrically connected to the top of the second gate structure 216; forming a second plug 222 in the first dielectric layer 211 and the second dielectric layer 212 of the first region I, the second plug 222 being electrically connected to the top of the first source / drain doped layer 209; and forming a fourth plug 224 in the first dielectric layer 211 and the second dielectric layer 212 of the second region II, the fourth plug 224 being electrically connected to the top of the second source / drain doped layer 210.

[0086] In this embodiment, the first plug 221, the second plug 222, the third plug 223, and the fourth plug 224 are formed simultaneously. The forming method includes: removing a portion of the second dielectric layer 212 until the top surfaces of the first gate structure 215 and the second gate structure 216 are exposed; forming a first contact hole (not shown) in a first region I and a third contact hole (not shown) in a second region II; removing a portion of the second dielectric layer 212 and the first dielectric layer 213 until the top surfaces of the first source / drain doped layer 209 and the second source / drain doped layer 210 are exposed; forming a second contact hole (not shown) in the first region I and a fourth contact hole (not shown) in the second region II; forming a first plug 221 in the first contact hole, a second plug 222 in the second contact hole, a third plug 223 in the third contact hole, and a fourth plug 224 in the fourth contact hole.

[0087] Accordingly, embodiments of the present invention also provide a semiconductor structure.

[0088] refer to Figure 13 and Figure 14 The semiconductor structure includes: a substrate 200, the substrate 200 including a first region I and a second region II; a first fin structure located on the first region I and a second fin structure located on the second region II, the first fin structure including a plurality of first channel layers 203 mutually separated along the normal direction of the surface of the substrate 200, with a first spacing 217 between adjacent first channel layers 203, the second fin structure including a plurality of second channel layers 205 mutually separated along the normal direction of the surface of the substrate 200, with a second spacing 218 between adjacent second channel layers 205; a first gate structure 215 located on the first region I and a second gate structure 216 located on the second region II, the first gate structure 215 located on the first fin structure and within the first spacing 217, the second gate structure 216 located on the second fin structure and within the second spacing 218; and an opening 219 (reference). Figure 11 and Figure 12 An opening 219 is located between the first gate structure 215 and the second gate structure 216, with the top of the opening 219 flush with the top surfaces of the first gate structure 215 and the second gate structure 216; an isolation structure 220 is located inside the opening 219, and the isolation structure 220 closes the opening 219 into a sealed cavity.

[0089] The opening 219 is also located between the first fin structure and the second fin structure.

[0090] The isolation structure 220 is used to isolate devices formed on the first region I and the second region II. The sealed cavity serves as an air sidewall. Air has a low dielectric constant, which can reduce the parasitic capacitance between the first gate structure 215 and the second gate structure 216. Even as the semiconductor process shrinks further, the performance of the semiconductor structure can still be guaranteed.

[0091] In this embodiment, it also includes: an isolation layer 206, located on a portion of the sidewall surface of the first fin structure and the second fin structure.

[0092] In this embodiment, it further includes: a first source / drain doped layer 209 located within the first fin structure on both sides of the first gate structure 215; and a second source / drain doped layer 210 located within the second fin structure on both sides of the second gate structure 216.

[0093] In this embodiment, it further includes: a first dielectric layer 211 covering the sidewall surfaces of the first gate structure 215 and the second gate structure 216, the top surface of the first dielectric layer 211 being flush with the top surfaces of the first gate structure 215 and the second gate structure 216; and a second dielectric layer 212 located on the first dielectric layer 211, which also covers the top surfaces of the first gate structure 215, the second gate structure 216 and the isolation structure 220.

[0094] In this embodiment, the first dielectric layer 211 and the second dielectric layer 212 constitute a dielectric structure.

[0095] In this embodiment, the device further includes: a first plug 221 located within the second dielectric layer 212 of the first region I, and the first plug 221 is electrically connected to the top of the first gate structure 215; a third plug 223 located within the second dielectric layer 212 of the second region II, and the third plug 223 is electrically connected to the top of the second gate structure 216; a second plug 222 located within the second dielectric layer 212 and the first dielectric layer 211 of the first region I, and the second plug 222 is electrically connected to the top of the first source / drain doped layer 209; and a fourth plug 224 located within the second dielectric layer 212 and the first dielectric layer 211 of the second region II, and the fourth plug 224 is electrically connected to the top of the second source / drain doped layer 210.

[0096] Figures 15 to 20 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention.

[0097] Please refer to Figure 15 and Figure 16 , Figure 15 yes Figure 9 A structural diagram based on the basic structure. Figure 16 yes Figure 10 A structural diagram based on the basic structure. Figure 15 View direction and Figure 9 Consistent, Figure 16 View direction and Figure 10 In a consistent manner, a second dielectric layer 312 is formed on the first dielectric layer 211, covering the top surfaces of the first gate structure 215, the second gate structure 216, and the initial isolation structure 207; a first plug 321 is formed within the second dielectric layer 312 in the first region I, the first plug 321 being electrically connected to the top of the first gate structure 215; a third plug 323 is formed within the second dielectric layer 312 in the first region I, the third plug 323 being electrically connected to the top of the second gate structure 216; a second plug 322 is formed within the first dielectric layer 211 and the second dielectric layer 312 in the first region I, the second plug 322 being electrically connected to the top of the first source / drain doped layer 209; and a fourth plug 324 is formed within the first dielectric layer 211 and the second dielectric layer 312 in the second region II, the fourth plug 324 being electrically connected to the top of the second source / drain doped layer 210.

[0098] refer to Figure 17 and Figure 18 , Figure 17 View direction and Figure 15 Consistent, Figure 18 View direction and Figure 16 In accordance with the above, the first dielectric layer 211, the second dielectric layer 312, and the initial isolation structure 207 are removed to form an opening 319. The top surface of the opening 319 is higher than the top surfaces of the first gate structure 215 and the second gate structure 216. It is located not only between the first gate structure 215 and the second gate structure 216, but also between the first plug 321 and the third plug 323, and between the second plug 322 and the fourth plug 324.

[0099] In this embodiment, the top surface of the opening 319 is flush with the top surfaces of the first plug 321, the second plug 322, the third plug 323 and the fourth plug 324.

[0100] In this embodiment, the process for removing the first dielectric layer 211, the second dielectric layer 312 and the initial isolation structure 207 includes a dry etching process.

[0101] refer to Figure 19 and Figure 20 , Figure 19 View direction and Figure 17 Consistent, Figure 20 View direction and Figure 18 In accordance with the above, an isolation structure 320 is formed within the opening 319, which closes the opening 319 into a sealed cavity.

[0102] In this embodiment, while forming the isolation structure 320, a third dielectric layer 313 is also formed on the substrate 200. The third dielectric layer 313 covers the sidewalls and top surface of the first gate structure 215 and the second gate structure 216.

[0103] In this embodiment, the isolation structure 320 and the third dielectric layer 313 are made of the same material.

[0104] The materials of the isolation structure 320 and the third dielectric layer 313 include low-k dielectric materials (low-k dielectric materials refer to dielectric materials with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), ultra-low-k dielectric materials (ultra-low-k dielectric materials refer to dielectric materials with a relative permittivity less than 2.6), or one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and silicon oxynitride nitride.

[0105] In this embodiment, the process for forming the isolation structure 320 and the third dielectric layer 313 includes chemical vapor deposition.

[0106] In this embodiment, when the third dielectric layer 313 is formed on the substrate 200, the material of the third dielectric layer 313 simultaneously fills the opening 319. Since the opening 319 has a high aspect ratio, the filling capacity of the material forming the isolation structure 320 is limited. When the opening 319 is not completely filled, the top of the opening 319 will be sealed to close the opening 319 into a sealed cavity, which serves as an air sidewall.

[0107] In this embodiment, the first plug 321, the second plug 322, the third plug 323, and the fourth plug 324 are formed first, and then the initial isolation structure 207 is removed to form an opening. On the one hand, the formed opening can be located between the first plug 321 and the third plug 323, and between the second plug 322 and the fourth plug 324, so that the air sidewall formed subsequently can not only reduce the parasitic capacitance between the first gate structure 215 and the second gate structure 216, but also reduce the parasitic capacitance between the first plug 321 and the third plug 323, and between the second plug 322 and the fourth plug 324, further improving the performance of the semiconductor structure. On the other hand, it can also avoid the overlay alignment problem caused during the formation of the first plug 321, the second plug 322, the third plug 323, and the fourth plug 324, and the process is less likely to cause a short circuit.

[0108] Accordingly, embodiments of the present invention also provide a semiconductor structure.

[0109] refer to Figure 19 and Figure 20The semiconductor structure includes: a substrate 200, the substrate 200 including a first region I and a second region II; a first fin structure located on the first region I and a second fin structure located on the second region II, the first fin structure including a plurality of first channel layers 203 mutually separated along the normal direction of the surface of the substrate 200, with a first spacing 217 between adjacent first channel layers 203, the second fin structure including a plurality of second channel layers 205 mutually separated along the normal direction of the surface of the substrate 200, with a second spacing 218 between adjacent second channel layers 205; a first gate structure 215 located on the first region I and a second gate structure 216 located on the second region II, the first gate structure 215 located on the first fin structure and within the first spacing 217, the second gate structure 216 located on the second fin structure and within the second spacing 218; and an opening 319 (reference). Figure 17 and Figure 18 An opening 219 is located between the first gate structure 215 and the second gate structure 216, with the top of the opening 219 being higher than the top surfaces of the first gate structure 215 and the second gate structure 216; an isolation structure 320 is located within the opening 319, and the isolation structure 320 closes the opening 319 into a sealed cavity.

[0110] In this embodiment, it also includes: an isolation layer 206, located on a portion of the sidewall surface of the first fin structure and the second fin structure.

[0111] In this embodiment, it further includes: a first source / drain doped layer 209 located within the first fin structure on both sides of the first gate structure 215; and a second source / drain doped layer 210 located within the second fin structure on both sides of the second gate structure 216.

[0112] In this embodiment, a third dielectric layer 313 is also included, which covers the sidewall surfaces and top surfaces of the first gate structure 215 and the second gate structure 216. The top surface of the third dielectric layer 313 is flush with the top surfaces of the first plug 321, the second plug 322, the third plug 323 and the fourth plug 324.

[0113] In this embodiment, the third dielectric layer 312 constitutes a dielectric structure.

[0114] In this embodiment, the device further includes: a first plug 321 located within the third dielectric layer 313 of the first region I, and the first plug 321 is electrically connected to the top of the first gate structure 215; a third plug 323 located within the third dielectric layer 313 of the second region II, and the third plug 323 is electrically connected to the top of the second gate structure 216; a second plug 322 located within the third dielectric layer 313 of the first region I, and the second plug 322 is electrically connected to the top of the first source / drain doped layer 209; and a fourth plug 324 located within the third dielectric layer 313 of the second region II, and the fourth plug 324 is electrically connected to the top of the second source / drain doped layer 210.

[0115] The opening 319 is also located between the first plug 321 and the third plug 323, and between the second plug 322 and the fourth plug 324.

[0116] The isolation structure 320 is used to isolate devices formed on the first region I and the second region II. The sealed cavity serves as an air sidewall. Air has a low dielectric constant, which can reduce the parasitic capacitance between the first gate structure 215 and the second gate structure 216. It can also reduce the parasitic capacitance between the first plug 321 and the third plug 323, and between the second plug 322 and the fourth plug 324. As the semiconductor process further shrinks, the performance of the formed semiconductor structure is further improved.

[0117] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate comprising a first region and a second region; The first fin structure is located on the first region and the second fin structure is located on the second region. The first fin structure includes a plurality of first channel layers that are mutually separated along the normal direction of the substrate surface, and there is a first interval between adjacent first channel layers. The second fin structure includes a plurality of second channel layers that are mutually separated along the normal direction of the substrate surface, and there is a second interval between adjacent second channel layers. A first gate structure located on a first region and a second gate structure located on a second region, wherein the first gate structure is located on the first fin structure and within a first interval, and the second gate structure is located on the second fin structure and within a second interval; A first source / drain doped layer located in the first region and a second source / drain doped layer located in the second region, wherein the first source / drain doped layer is located within the first fin structure on both sides of the first gate structure, and the second source / drain doped layer is located within the second fin structure on both sides of the second gate structure. A second plug located on the first region, the second plug being electrically connected to the first source / drain doped layer; A fourth plug located on the second region, the fourth plug being electrically connected to the second source / drain doped layer; An opening is located between the first gate structure and the second gate structure, between the first source / drain doped layer and the second source / drain doped layer, and between the second plug and the fourth plug, and the top surface of the opening is flush with the top surfaces of the second plug and the fourth plug. An isolation structure is located within the opening, and the isolation structure closes the opening into a sealed cavity. The isolation structure is located between the first gate structure and the second gate structure, between the first source / drain doped layer and the second source / drain doped layer, and between the second plug and the fourth plug. The top surface of the isolation structure is flush with the top surfaces of the second plug and the fourth plug.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A dielectric structure located on the substrate, the dielectric structure covering the first gate structure and the second gate structure.

3. The semiconductor structure as described in claim 2, characterized in that, Also includes: A first plug and a second plug are located on the first region, the first plug and the second plug are located within the dielectric structure, and the first plug is electrically connected to the top of the first gate structure, and the second plug is electrically connected to the first source / drain doped layer; a third plug and a fourth plug are located on the second region, the third plug and the fourth plug are located within the dielectric structure, and the third plug is electrically connected to the top of the second gate structure, and the fourth plug is electrically connected to the second source / drain doped layer.

4. The semiconductor structure as described in claim 3, characterized in that, The medium structure includes a third medium layer, the top surface of which is flush with the top surfaces of the first plug and the third plug, the opening is located within the third medium layer, the opening is also located between the first plug and the third plug, and the top surface of the opening is flush with the top surfaces of the first plug and the third plug.

5. The semiconductor structure as described in claim 4, characterized in that, The material of the third dielectric layer is the same as the material of the isolation structure, including one or more combinations of low-k dielectric materials, ultra-low-k dielectric materials, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and silicon oxynitride nitride.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A first fin structure is formed on the first region and a second fin structure is formed on the second region. The first fin structure includes a plurality of first channel layers that are mutually separated along the normal direction of the substrate surface, and there is a first interval between adjacent first channel layers. The second fin structure includes a plurality of second channel layers that are mutually separated along the normal direction of the substrate surface, and there is a second interval between adjacent second channel layers. A first source / drain doped layer and a first gate structure are formed on the first region. The first gate structure is located on the first fin structure and within the first interval. The first source / drain doped layer is located within the first fin structure on both sides of the first gate structure. A second source / drain doped layer and a second gate structure are formed on the second region. The second gate structure is located on the second fin structure and within the second gap. The second source / drain doped layer is located within the second fin structure on both sides of the second gate structure. A second plug is formed on the first region, and the second plug is electrically connected to the first source / drain doped layer; a fourth plug is formed on the second region, and the fourth plug is electrically connected to the second source / drain doped layer. ； An opening is formed between the first gate structure and the second gate structure, the opening is also located between the first source / drain doped layer and the second source / drain doped layer and the second plug and the fourth plug, and the top surface of the opening is flush with the top surfaces of the second plug and the fourth plug; An isolation structure is formed within the opening, which closes the opening to form a sealed cavity. The isolation structure is located between the first gate structure and the second gate structure, between the first source / drain doped layer and the second source / drain doped layer, and between the second plug and the fourth plug. The top surface of the isolation structure is flush with the top surfaces of the second plug and the fourth plug.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, Before forming the first fin structure and the second fin structure, the method further includes: forming a first initial fin structure on the first region, forming a second initial fin structure on the second region, wherein the first initial fin structure includes a first sacrificial layer and a first channel layer alternately stacked along the normal direction of the substrate surface, and the second initial fin structure includes a second sacrificial layer and a second channel layer alternately stacked along the normal direction of the substrate surface, wherein an initial opening is provided between the first initial fin structure and the second initial fin structure; and forming an initial isolation structure within the initial opening.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the initial isolation structure and before forming the first gate structure and the second gate structure, the method further includes: forming a dummy gate structure on the first region and the second region, the dummy gate structure spanning the first initial fin structure, the second initial fin structure and the initial isolation structure; forming a first dielectric layer on the substrate, the first dielectric layer being located on the sidewall of the dummy gate structure; removing the dummy gate structure; forming a first gate opening in the first dielectric layer of the first region, the first gate opening exposing a portion of the sidewall surface of the first initial fin structure; and forming a second gate opening in the first dielectric layer of the second region, the second gate opening exposing a portion of the sidewall surface of the second initial fin structure.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method of forming the first fin structure and the second fin structure includes: removing the first sacrificial layer exposed by the first gate opening, forming a first gap between adjacent first channel layers, and forming the first fin structure; removing the second sacrificial layer exposed by the second gate opening, forming a second gap between adjacent second channel layers, and forming the second fin structure.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the first gate structure and the second gate structure includes: forming a first gate structure within the first gate opening and the first gap; and forming a second gate structure within the second gate opening and the second gap.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming the pseudo-gate structure, the method further includes: forming a first source / drain doped layer in the first initial fin structure on both sides of the pseudo-gate structure, and forming a second source / drain doped layer in the second initial fin structure on both sides of the pseudo-gate structure.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the first gate structure and the second gate structure, and before forming the opening, the method further includes: forming a second dielectric layer on the top surface of the first gate structure and the second gate structure; removing a portion of the second dielectric layer until the top surface of the first gate structure and the second gate structure is exposed, forming a first contact hole in the first region, and forming a third contact hole in the second region; removing a portion of the second dielectric layer and the first dielectric layer until the top surface of the first source / drain doped layer and the second source / drain doped layer is exposed, forming a second contact hole in the first region, and forming a fourth contact hole in the second region; forming a first plug in the first contact hole, forming a second plug in the second contact hole, forming a third plug in the third contact hole, and forming a fourth plug in the fourth contact hole.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method of forming the opening includes: removing the first dielectric layer and the second dielectric layer to expose the initial isolation structure; removing the initial isolation structure to form an opening between the first gate structure and the second gate structure, and between the first plug and the third plug, wherein the top surface of the opening is flush with the top surfaces of the first plug and the third plug.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the opening, the method further includes: forming a third dielectric layer on the substrate, the top surface of the third dielectric layer being flush with the top surfaces of the first plug and the third plug, and forming an isolation structure within the opening, the isolation structure closing the opening to form a sealed cavity.

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