A Capacitor Array Switching Method for SAR ADC

Abstract

The present invention discloses a capacitance array switching method for a SAR ADC, which relates to the field of integrated circuit technologies. The SAR ADC includes a sampling switch, a split capacitance array, a reference level group, a comparator, and a timing control circuit. The reference level group includes a first level GND, a second level VREF, and a third level VCM, and the third level VCM = 1 / 2VREF. The method includes the following steps: In the sampling stage, the input signal is respectively connected to the top plates of the split capacitance array through the sampling switch, and the bottom plates of the split capacitance array are all connected to the third level VCM; in the conversion stage, the sampling switch is disconnected, and the comparator obtains a multi-bit digital code by comparing the voltages of the top plates of the split capacitance array, and controls the connection relationship of the capacitor bottom plates in the split capacitance array according to the digital code. The area used by the capacitance array switching method of the present invention is about 50% of that of the traditional VCM-based capacitance array switching method, and the power consumption is also 50% of that of the traditional VCM-based capacitance array switching method.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a method for switching a capacitor array of a SAR ADC. Background Art

[0002] Under the application conditions of medium precision and medium sampling rate, the successive approximation register type analog-to-digital converter SAR ADC has a small area, and the charge redistribution architecture and clock comparator reduce the power consumption. At the same time, under the application conditions of high precision and relatively high sampling rate, the application requirements can be achieved by cascading a residue amplifier with a SAR ADC. Therefore, the SAR ADC is very suitable for applications in modern communication, process control, and medical equipment. The traditional SAR ADC consists of a binary weighted capacitor array, a comparator, and a timing control circuit. The power consumption of the SAR ADC mainly comes from the capacitive DAC, the comparator, and the digital control logic. At low speeds, the power consumption of the capacitive charge and discharge of the capacitors in the capacitive DAC occupies a large proportion of the overall power consumption. At the same time, the capacitors in the capacitive DAC also occupy a large proportion of the overall layout area.

[0003] In existing research, a variety of switching algorithms have been proposed to reduce the switching power consumption and area of the capacitive DAC. From the change of the common-mode level of the comparator input signal during the conversion process, it can be roughly divided into three categories: the common-mode level does not change, the common-mode level has a callback, and the common-mode level changes monotonically. Among them, the switching conversion method with a monotonically changing common-mode level can achieve lower power consumption. However, compared with the other two methods, this method will increase the design complexity of other circuits such as subsequent comparators. When using the switching conversion method with an unchanged common-mode level, the subsequent circuit design complexity is relatively low. However, compared with the other two methods, this method has higher power consumption and a larger area. Summary of the Invention

[0004] An embodiment of the present invention provides a method for switching a capacitor array of a SAR ADC, which can solve the problems existing in the prior art.

[0005] The present invention provides a method for switching a capacitor array of a SAR ADC. The SAR ADC includes a sampling switch, a split capacitor array, a comparator, and a timing control circuit. The split capacitor array is provided with a reference level group, and the reference level group includes a first level GND, a second level VREF, and a third level VCM, where the third level VCM = 1 / 2VREF. The method includes the following steps: In the sampling stage, connect the input signal to the top plates of the split capacitor array through the sampling switch respectively, and the bottom plates of the split capacitor array are all connected to the third level VCM.

[0006] During the conversion stage, the sampling switch is disconnected, and the comparator obtains a multi-bit digital code by comparing the voltages of the top plates of the split capacitor array, and controls the connection relationship of the capacitor bottom plates in the split capacitor array according to the digital code.

[0007] Preferably, the input signals include Vip and Vin, the split capacitor array includes a P capacitor array and an N capacitor array, and the sizes of the split capacitors in each section of the P capacitor array and the N capacitor array are both: C i = 2 i-1 , where 1 ≤ i ≤ N - 2, C0 = C.

[0008] Preferably, the sampling stage specifically includes the following steps:

[0009] Connect Vip and Vin to the top plates of the P capacitor array and the N capacitor array respectively through the sampling switch, and the bottom plates of the P capacitor array and the N capacitor array are both connected to the third level VCM.

[0010] Preferably, the split capacitor array includes a P capacitor array and an N capacitor array, and the conversion stage specifically includes the following steps:

[0011] Step 1, the comparator obtains the most significant bit digital code D1 by comparing the voltages of the top plates of the P capacitor array and the N capacitor array, and controls the connection relationship of the capacitor bottom plates in the P capacitor array and the N capacitor array according to the most significant bit digital code D1:

[0012] If D1 = 1, connect the C N-2 bottom plate in the P capacitor array to the first level GND, and connect the C N-2 bottom plate in the N capacitor array to VREF to generate a voltage offset of -1 / 2VREF;

[0013] If D1 = 0, connect the C N-2 bottom plate in the P capacitor array to the second level VREF, and connect the C N-2 bottom plate in the N capacitor array to GND to generate a voltage offset of +1 / 2VREF;

[0014] Steps 2 to step N - 2, the comparator obtains the corresponding digital code by comparing the voltages of the top plates of the P capacitor array and the N capacitor array obtained in the previous step, and controls the connection relationship of the bottom plates in the P capacitor array and the N capacitor array. The connection relationship of the bottom plates in the P capacitor array and the N capacitor array in steps 2 to step N - 2 is the same as that in step 1;

[0015] Step N - 1, the comparator obtains the digital code D N-1 by comparing the voltages of the top plates of the P capacitor array and the N capacitor array in step N - 2, and according to the digital code D N-1Control the connection relationship of the capacitor bottom plates in the P-capacitor array and the N-capacitor array:

[0016] If D N-1 = 1, connect the bottom plate of C0 in the P-capacitor array to the first level GND to generate a voltage offset of -1 / (2 N-1 )VREF;

[0017] If D N-1 = 0, connect the bottom plate of C0 in the N-capacitor array to the first level GND to generate a voltage offset of +1 / (2 N-1 )VREF;

[0018] Step N, obtain the least significant digit code D N .

[0019] Preferably, when the method is used as a pipelined ADC, a level conversion process before the amplification stage can be added, which specifically includes:

[0020] If D N = 1, the connection relationship of the bottom plate levels in the P-capacitor array and the N-capacitor array remains unchanged;

[0021] If D N = 0, then increase the connection level of the bottom plate of C0 in the P-capacitor array by VCM.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] The capacitor array switching method of the small-area and high-energy-efficiency SAR ADC proposed by the present invention adopts the VCM switching technology, and combines the split capacitor technology and the unilateral switching technology to effectively reduce the capacitor area and the overall conversion power consumption. Through modeling and analysis, it is obtained that the area used by the capacitor array switching method of the present invention is about 50% of that of the traditional VCM-based capacitor array switching method, and the power consumption is also 50% of that of the traditional VCM-based capacitor array switching method. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0025] Figure 1 It is a schematic structural diagram of implementing an N-bit SAR ADC by the method of the present invention;

[0026] Figure 2 The conversion process diagram of a 3-bit SAR ADC implemented by the traditional VCM-based capacitive array switching method;

[0027] Figure 3 The conversion process diagram of a 3-bit SAR ADC implemented by the method of the present invention;

[0028] Figure 4 The MATLAB simulation result diagram of the switching energy consumption varying with the ADC output codeword when the traditional VCM-based capacitive array switching method and the method of the present invention are applied to a 10-bit SAR ADC. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0030] Referring to Figures 1-4 , the present invention provides a capacitive array switching method for a SAR ADC. The SAR ADC includes a sampling switch, a split capacitive array, a comparator, and a timing control circuit. The split capacitive array adopts a binary weighted split capacitive structure and includes a P capacitive array and an N capacitive array. The split capacitive array is provided with a reference level group, and the reference level group includes a first level GND, a second level VREF, and a third level VCM, where the third level VCM = 1 / 2VREF, and a third level is introduced to assist the switching of the capacitive array. The input signals include Vip and Vin. The input signals Vin and Vip are respectively connected to the top plates of the P capacitive array and the N capacitive array through the sampling switch. The top plate of the P capacitive array is connected to the non-inverting input terminal of the comparator, and the top plate of the N capacitive array is connected to the inverting input terminal of the comparator. The output terminal of the comparator generates a control signal through the timing control circuit to control the reference levels connected to the bottom plates of the P capacitive array and the N capacitive array.

[0031] The sizes of the split capacitors in each segment of the P capacitive array and the N capacitive array are: C i = 2 i-1 , where 1 ≤ i ≤ N - 2, and the capacitor C0 = C, where C is the unit capacitor size.

[0032] For the input signals Vip and Vin, after N comparisons, this capacitive array switching method obtains an N-bit digital output code, including two stages: sampling and conversion, and specifically includes the following steps:

[0033] In the sampling stage, two input signals Vip and Vin are respectively connected to the top plates of the P-capacitor array and the N-capacitor array through sampling switches, and the bottom plates of all capacitors are connected to the third level VCM.

[0034] In the conversion stage, the sampling switches are disconnected to enter the conversion stage. It specifically includes the following steps:

[0035] Step 1, the comparator compares the voltages of the top plates of the P-capacitor array and the N-capacitor array to obtain the most significant digit code D1, and controls the connection relationship of the bottom plates of the capacitors in the P-capacitor array and the N-capacitor array according to the digit code D1;

[0036] If D1 = 1, connect the bottom plate of C in the P-capacitor array N-2 to the first level GND, that is, 0 level, and connect the bottom plate of C in the N-capacitor N-2 to VREF to generate a voltage offset of -1 / 2VREF.

[0037] If D1 = 0, connect the bottom plate of C in the P-capacitor array N-2 to the second level VREF, and connect the bottom plate of C in the N-capacitor N-2 to GND, that is, 0 level, to generate a voltage offset of +1 / 2VREF.

[0038] Steps 2 to N-2 are similar to Step 1. The comparator compares the voltages of the top plates of the P-capacitor array and the N-capacitor array obtained in the previous step to obtain the corresponding digit code, and controls the connection relationship of the bottom plates in the P-capacitor array and the N-capacitor array according to the digit code. The specific situation of the connection relationship is the same as that in Step 1.

[0039] After the comparator in Step 2 compares the voltages of the top plates of the P-capacitor array and the N-capacitor array obtained in Step 1, it obtains the second most significant digit code D2. If D2 = 1, connect the bottom plate of C in the P-capacitor array N-3 to the first level GND, that is, 0 level, and connect the bottom plate of C in the N-capacitor N-3 to the second level VREF to generate a voltage offset of -1 / 2VREF.

[0040] If D2 = 0, connect the bottom plate of C in the P-capacitor array N-1 to the second level VREF, and connect the bottom plate of C in the N-capacitor N-1 to the first level GND, that is, 0 level, to generate a voltage offset of +1 / 2VREF.

[0041] Steps 3 to N-2 follow the same pattern.

[0042] Step N-1, the comparator compares the voltages of the top plates of the P-capacitor array and the N-capacitor array to obtain the digit code D N-1 and according to the digit code DN-1 Control the connection relationship of the capacitor bottom plates in the P-capacitor array and the N-capacitor array.

[0043] If D N-1 = 1, connect the C0 bottom plate in the P-capacitor array to the first level GND, that is, 0 level, to generate a voltage offset of -1 / (2N - 1)VREF.

[0044] If D N-1 = 0, connect the C0 bottom plate in the N-capacitor array to the first level GND, that is, 0 level, to generate a voltage offset of +1 / (2N - 1)VREF.

[0045] Step N, obtain the least significant digit code D by comparing the top plate voltages of the P-capacitor array and the N-capacitor array obtained in step N - 1 N .

[0046] When the capacitor array switching method in the present invention is used as a pipelined ADC, a level conversion process before the amplification stage can be added, and the process is as follows:

[0047] If D N = 1, the level connection relationship of the C0 bottom plates in the P-capacitor array and the N-capacitor array remains unchanged;

[0048] If D N = 0, then increase the connection level of the C0 bottom plate in the P-capacitor array by VCM. For example, if the connection level of the C0 bottom plate in the P-capacitor array is the first level GND when D N-1 = 0, then when D N = 0, the C0 bottom plate in the P-capacitor array is connected to the third level VCM; if the connection level of the C0 bottom plate in the P-capacitor array is the third level VCM when D N-1 = 0, then when D N = 0, the C0 bottom plate in the P-capacitor array is connected to the second level VREF.

[0049] The following specifically describes the present invention in conjunction with an embodiment. Figure 3 The following shows the specific conversion process of the 3-bit SAR ADC according to the embodiment of the present invention:

[0050] Step 1, the comparator obtains the most significant digit code D1 by comparing the voltages of the top plates of the P-capacitor array and the N-capacitor array, and controls the connection relationship of the capacitor bottom plates in the P-capacitor array and the N-capacitor array according to the digit code D1;

[0051] If D1 = 1, connect the C1 bottom plate in the P-capacitor array to the first level GND, that is, 0 level, and connect the C1 bottom plate in the N-capacitor array to the second level VREF to generate a voltage offset of -1 / 2VREF.

[0052] If D1 = 0, connect the C1 bottom plate in the P capacitor array to the second level VREF, and connect the C1 bottom plate in the N capacitor array to the first level GND, i.e., the 0 level, to generate a voltage offset of +1 / 2VREF.

[0053] Step 2: The comparator compares the voltages of the top plates of the P capacitor array and the N capacitor array to obtain the digital code D2, and controls the connection relationship of the capacitor bottom plates in the P capacitor array and the N capacitor array according to the digital code D2;

[0054] If D2 = 1, connect the C0 bottom plate in the P capacitor array to the first level GND, i.e., the 0 level, to generate a voltage offset of -1 / 4VREF.

[0055] If D2 = 0, connect the C0 bottom plate in the N capacitor array to the first level GND, i.e., the 0 level, to generate a voltage offset of +1 / 4VREF.

[0056] Step 3: By comparing the voltages of the top plates of the P capacitor array and the N capacitor array obtained in Step 2, obtain the least significant bit digital code D3.

[0057] In this example, when this switching method needs to be applied to a pipelined ADC, a level conversion process before the amplification stage can be added, and the process is as follows:

[0058] If D3 = 1, the connection relationship of the C0 bottom plate levels in the P capacitor array and the N capacitor array remains unchanged.

[0059] If D3 = 0, then increase the level connected to the C0 bottom plate in the P capacitor array by VCM.

[0060] Figure 4 Introduced is the MATLAB simulation result graph of the switching energy consumption varying with the ADC output code word of the traditional VCM-based capacitor array switching method and the switching method of the present invention applied to a 10-bit SAR ADC. It can be seen from the graph that the power consumption of the present invention is about 50% of that of the traditional VCM-based capacitor array switching method.

[0061] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0062] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A method for switching a capacitor array of a SAR ADC, characterized in that, The SAR ADC includes a sampling switch, a split capacitor array, a comparator, and a timing control circuit. The split capacitor array is provided with a reference level group, and the reference level group includes a first level GND, a second level VREF, and a third level VCM, where the third level VCM = 1 / 2VREF. The method includes the following steps: In the sampling stage, the input signal is respectively connected to the top plates of the split capacitor array through the sampling switch, and the bottom plates of the split capacitor array are all connected to the third level VCM; In the conversion stage, the sampling switch is disconnected, and the comparator obtains a multi-bit digital code by comparing the voltages of the top plates of the split capacitor array, and controls the connection relationship of the capacitor bottom plates in the split capacitor array according to the digital code; The input signal includes Vip and Vin, the split capacitor array includes a P capacitor array and an N capacitor array, and the sizes of the split capacitors in each segment of the P capacitor array and the N capacitor array are all: C i = 2 i-1 , where 1 ≤ i ≤ N - 2, C0 = C; Connect Vip and Vin to the top plates of the P capacitor array and the N capacitor array respectively through the sampling switch, and the bottom plates of the P capacitor array and the N capacitor array are all connected to the third level VCM; The conversion stage specifically includes the following steps: Step 1, the comparator obtains the most significant bit digital code D1 by comparing the voltages of the top plates of the P capacitor array and the N capacitor array, and controls the connection relationship of the capacitor bottom plates in the P capacitor array and the N capacitor array according to the most significant bit digital code D1: If D1 = 1, connect the C of the P capacitor array N-2 bottom plate to the first level GND, and connect the C of the N capacitor array N-2 bottom plate to the second level VREF to generate a voltage offset of -1 / 2VREF; If D1 = 0, connect the C in the P capacitor array N-2 bottom plate to the second level VREF, and connect the C in the N capacitor array N-2 bottom plate to the first level GND to generate a voltage offset of +1 / 2VREF; Steps 2 to step N-2, the comparator obtains the corresponding digital code by comparing the voltages of the top plates of the P capacitor array and the N capacitor array obtained in the previous step, and controls the connection relationship of the bottom plates in the P capacitor array and the N capacitor array according to the digital code. The connection relationship of the bottom plates in the P capacitor array and the N capacitor array in steps 2 to step N-2 is the same as that in step 1; Step N-1: The comparator obtains a digital code D by comparing the voltages of the top plates of the P-capacitor array and the N-capacitor array in Step N-2. N-1 , and based on the digital code D N-1 controls the connection relationship of the capacitor bottom plates in the P-capacitor array and the N-capacitor array: If D N-1 = 1, connect the C0 bottom plate in the P capacitor array to the first level GND to generate a voltage offset of -1 / (2 N-1 )VREF; If D N-1 = 0, connect the C0 bottom plate in the N-capacitor array to the first level GND to generate a voltage offset of +1 / (2 N-1 )VREF; Step N, obtain the least significant digit code D by comparing the top plate voltages of the P capacitor array and the N capacitor array obtained in step N-1 N .

2. The method for switching a capacitor array of a SAR ADC according to claim 1, characterized in that, When the method is used as a pipelined ADC, a level conversion process before the amplification stage can be added, which specifically includes the following situations: If D N = 1, the level connection relationship of the C0 bottom plates in the P-capacitor array and the N-capacitor array remains unchanged; If D N = 0, the reference level connected to the C0 bottom plate in the P capacitor array is increased by VCM.

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