A clock signal synchronization method and device

Abstract

The present application provides a clock signal synchronization method and device. In this method, a frame network device calibrates a local clock signal based on a recovered upstream clock signal of an upstream network device and outputs a multi-channel selector for a primary master control board and a standby master control board; the multi-channel selectors of the primary master control board and the standby master control board respectively output the calibrated signals to their respective multi-channel drivers; the multi-channel drivers of the primary master control board and the standby master control board respectively output a first group and a second group of multiplexed clock signals to phase-locked loop chips of each service board in the frame; a clock signal selector of each service board gates and inputs the first group of multiplexed clock signals to the phase-locked loop chips of each board; the phase-locked loop chip of the service board docking with the upstream device locks the recovered upstream clock signal, and the phase-locked loop chips of other service boards lock the first group of multiplexed clock signals and calibrate the local clock signal.

Description

Technical Field

[0001] This application relates to communication technologies, and particularly to a clock signal synchronization method and device. Background Art

[0002] Synchronization Ethernet (Sync E) is a technology that recovers the clock from the Ethernet link code stream. The clock of the transmitting end is recovered from the serial data code stream by the Ethernet physical layer chip (PHY), so as to achieve network clock synchronization.

[0003] In a frame network device of Ethernet, in addition to recovering the clock of the upstream device from the docking Ethernet port of the service board connecting to the upstream device and synchronizing the clock frequency of the local board, it is also necessary to synchronize the clock frequency to other service boards of the frame network device, so that the service board docking the downstream device sends Ethernet packets with the synchronized clock frequency, and continues to transmit the clock synchronization information to ensure clock synchronization in the entire network.

[0004] To avoid the large number of Ethernet ports of the upstream device occupied by each service board of the frame device to dock with the upstream device to synchronize the clock frequency of the upstream device, the existing frame network device adopts Figure 1 the method shown in the figure. The upstream clock signal clock 1 recovered by the Ethernet physical layer (PHY) chip of the service board card docking the upstream device is input to the active main control board and the standby main control board. The phase-locked loop (PLL) chips 30 and 40 of the active main control board and the standby main control board respectively output the calibrated clocks a1 - an and a1' - an' to the PLL chips 1 - n of all service boards. The PLL chips 1 - n of each service board calibrate the system clock of their respective local boards and output it to the PHY chips 1 - n of their respective local boards and the service modules of their respective local boards (not shown in the figure); the PHY of the service board n docking the downstream device encodes the calibrated clock information in the Ethernet packet and sends it to the downstream device through the Ethernet for clock synchronization. However, the frequency input range of the clock signal supported by the PLL chip of the main control board of the frame network device is limited, so the selection of the PHY chip on the service board is limited. Summary of the Invention

[0005] The purpose of this application is to provide a clock signal synchronization method and device, which provide full-frame synchronization through the service board of the frame network device docking the upstream device, and simplify the selection of the PHY chip for the service board card.

[0006] To achieve the above object, the present application provides a clock signal synchronization method. In this method, the first service board connected to the upstream network device restores the upstream clock signal of the upstream network device, calibrates the local clock signal of the first service board based on the upstream clock signal, and outputs the calibrated local clock signal of the first service board to the first multi-channel selector of the active main control board and the second multi-channel selector of the standby main control board; the first multi-channel selector of the active main control board outputs the calibrated local clock signal of the first service board to the first multi-channel driver of the active main control board; the second multi-channel selector of the standby main control board outputs the calibrated local clock signal of the first service board to the second multi-channel driver of the standby main control board; the first and second multi-channel drivers respectively output a first set of multi-channel clock signals and a second set of multi-channel clock signals to the phase-locked loop chips of each service board; the clock signal selectors of the first service board, the second service board connected to the downstream network device, and other service boards select and input the first set of multi-channel clock signals to the phase-locked loop chips of each service board; the phase-locked loop chip of the first service board locks the restored upstream clock signal, and the phase-locked loop chips of the second service board and other service boards lock the first set of multi-channel clock signals and calibrate the local clock signals.

[0007] To achieve the above object, the present application further provides a clock signal synchronization device, which is applied to an Ethernet in-frame network device. The device includes a primary main control board, a standby main control board, a first service board for docking with an upstream network device, a second service board for docking with a downstream network device, and more than one other service board; the output end of the Ethernet physical layer chip of the first service board is connected to the phase-locked loop chip of this board, and the output end of the phase-locked loop chip of the first service board is connected to the first multi-channel selector of the primary main control board and the second multi-channel selector of the standby main control board; the output ends of the first multi-channel selector and the multi-channel selector are respectively connected to the multi-channel drivers of the primary main control board and the standby main control board of this board; the output end of the multi-channel driver of the primary main control board is respectively connected to the first input end of the clock signal selector of each service board; the output end of the multi-channel driver of the standby main control board is respectively connected to the second input end of the clock signal selector of each service board; the upstream clock signal of the upstream network device recovered by the Ethernet physical layer chip of the first service board is input into the phase-locked loop chip of the first service board, and the phase-locked loop chip of the first service board calibrates the local clock signal of the first service board based on the upstream clock signal, and outputs the calibrated local clock signal of the first service board to the first multi-channel selector and the second multi-channel selector; the first multi-channel selector outputs the calibrated local clock signal of the first service board to the first multi-channel driver; the second multi-channel selector outputs the calibrated local clock signal of the first service board to the second multi-channel driver; the first and second multi-channel drivers respectively output a first group of multi-channel clock signals and a second group of multi-channel clock signals to the phase-locked loop chips of each service board; the clock signal selectors of the first service board, the second service board for docking with the downstream network device, and other service boards select and pass the first group of multi-channel clock signals input to the phase-locked loop chips of each service board; the phase-locked loop chip of the first service board locks the recovered upstream clock signal, and the phase-locked loop chips of the second service board and other service boards lock the first group of multi-channel clock signals and calibrate the local clock signals.

[0008] The beneficial effect of the present application is that it can reduce the frequency limitation of the clock signal output by the PHY chip on the service board caused by the PLL chip on the main control board, and simplify the selection of the PHY chip on the service board of the in-frame network device. Description of the Drawings

[0009] Figure 1 Schematic diagram of synchronizing the clock of the existing in-frame network device in Ethernet;

[0010] Figure 2 Schematic diagram of the method for synchronizing the clock of the in-frame network device in Ethernet provided by the present application;

[0011] Figure 3 Schematic diagram of synchronizing the clock of the in-frame network device in Ethernet provided by the present application. Detailed Embodiments

[0012] Multiple examples shown in multiple attached drawings will be described in detail. In the following detailed description, multiple specific details are provided to give a comprehensive understanding of this application. Known methods, steps, components, and circuits are not described in detail in the examples to avoid making these examples difficult to understand.

[0013] Among the terms used, the term "including" means including but not limited to; the term "containing" means including but not limited to; the terms "above", "within", and "below" include the specified number; the terms "greater than" and "less than" do not include the specified number. The term "based on" means at least based on a part of it.

[0014] Figure 2 Schematic diagram of the method for synchronizing the clock of the frame network device in the synchronous Ethernet provided for this application; the method includes:

[0015] Step 201, recover the upstream clock signal of the upstream network device on the first service board docking the upstream network device, calibrate the local clock signal of the first service board based on the upstream clock signal, and output the calibrated local clock signal of the first service board to the first multi-channel selector of the active main control board and the second multi-channel selector of the standby main control board;

[0016] Step 202, the first multi-channel selector of the active main control board outputs the calibrated local clock signal of the first service board to the first multi-channel driver of the active main control board;

[0017] Step 203, the second multi-channel selector of the standby main control board outputs the calibrated local clock signal of the first service board to the second multi-channel driver of the standby main control board;

[0018] Step 204, the first and second multi-channel drivers respectively output the first set of multi-channel clock signals and the second set of multi-channel clock signals to the phase-locked loop chips of each service board;

[0019] Step 205, the clock signal selectors of the first service board, the second service board docking the downstream network device, and other service boards select and pass the first set of multi-channel clock signals input to the phase-locked loop chips of each service board;

[0020] Step 206, the phase-locked loop chip of the first service board locks the recovered upstream clock signal, and the phase-locked loop chips of the second service board and other service boards lock the first set of multi-channel clock signals and calibrate the local clock signals.

[0021] The beneficial effect of this application is that it can reduce the frequency limitation of the clock signal output by the PHY chip on the service board due to the PLL chip on the main control board, and simplify the selection of the PHY chip on the service board of the frame network device.

[0022] Figure 3 Schematic diagram of synchronous clock for frame network devices in the synchronous Ethernet provided by this application; Network devices 1, 2, and 3 are three network nodes of the synchronous Ethernet network. Network device 1 serves as the clock source device and transmits clock information downward. Frame network device 2 is an intermediate node in the synchronous Ethernet, receives the clock information of the upstream network device 1, synchronizes the system clocks of PHY1 chip - PHYn chips and related service function blocks on each service board of this device, and simultaneously transmits clock information to the downstream network device 3. The frame network device 2 is provided with n service boards, a primary master control board, and a standby master control board. Network device 3 only receives clock information.

[0023] In the frame network device 2, the output end of the PHY1 chip of service board 1 is connected to the PLL1 chip on this board, and the output end of the PLL1 chip is connected to the multi - channel selector 1 of the primary master control board and the multi - channel selector 2 of the standby master control board. The output ends of the multi - channel selector 1 and the multi - channel selector 2 are respectively connected to the multi - channel drivers 1 and 2.

[0024] The output end of the multi - channel driver 1 is respectively connected to the first input end of the clock signal selectors of each service board 1 - service board n; the output end of the multi - channel driver 2 is respectively connected to the second input end of the clock signal selectors of each service board.

[0025] The PHY10 chip of network device 1 encodes the high - precision clock information of this device into the Ethernet packet and sends the Ethernet packet containing the clock information to network device 2 through the Ethernet.

[0026] The Ethernet port of service board card 1 in the frame network device 2 docks with network device 1 within the synchronous Ethernet and receives the Ethernet packet P1 containing the clock information.

[0027] The PHY1 chip of service board 1 restores the clock signal clock1 synchronized with the high - precision clock on network device 1 according to the received Ethernet packet P1 and inputs it to the PLL1 chip on service board 1. The PLL1 chip also receives the local clock signal input by the local crystal oscillator chip (not shown in the figure) on service board 1. Since the primary master control board has set the pin priority of the PLL1 on service board 1 to receive the clock signal clock1 from PHY1 higher than the pin for receiving the local clock signal, the frequency of the local clock signal is calibrated according to the frequency of the clock signal clock1, and at the same time, a high - precision clock signal u1 is output to the multi - channel selector 1 of the primary master control board and the multi - channel selector 2 of the standby master control board.

[0028] The multi - channel selectors 1 and 2 are respectively N - to - 1 logic devices independently controlled by controllers 1 and 2. The controllers 1 and 2 respectively select the pins of the multi - channel selectors 1 and 2 connected to the PLL1 chip.

[0029] Since only the service board 1 has an Ethernet port connection with the network device 1, only the clock signal clock u1 output by the PLL1 chip on the service board 1 is synchronized with the high-precision clock of the network device 1. The clock signals clock u2, … un output by the PLL2 - PLLn chips on the remaining service boards 2 - n are local clock signals output based on the frequencies of the local crystal oscillator chips on their respective boards, which are not synchronized with the network device 1. However, since the pins of the multi-channel selectors 1 and 2 connecting the service boards 2 - n are not selected, the signals will not be synchronized within the frame network device through the primary master control board and the standby master control board.

[0030] Based on the input clock signal clock u1, the multi-channel selector 1 on the primary master control board outputs the clock signal clock U1 to the multi-channel driver 1 on the master control board. The multi-channel driver 1 outputs n clock signals a1, a2 … an to the PLL1 - PLLn chips on each service board. Based on the input clock signal clock u1, the multi-channel selector 2 on the standby master control board outputs the clock signal clock U1 to the multi-channel driver 2 on the master control board. The multi-channel driver 2 outputs n clock signals a1’, a2’ … an’ to the PLL1 - PLLn chips on each service board.

[0031] The signal selectors 1 - n on the service boards 1 - n respectively select and enable the n clock signals a1, a2 … an output by the channel driver 1 of the primary master control board.

[0032] The PLL1 on the service board 1 locks the clock signal clock 1 output by the PHY1 chip and will not lock the input clock a1. The PLL2 - PLLn chips on the service boards 2 - n receive and lock the high-precision clock signals a2, … an distributed by the primary master control board and output reference clocks for the normal operation of the PHY2 - PHYn chips on their respective service boards.

[0033] In this application, the clock signal u1 output by the PHY1 chip of the service board 1 docking with the upstream network device 1 is synchronized with clock 1, and clock 1 is synchronized with the high-precision clock on the network device 1. Therefore, the reference clocks of the PHYs on each service board are synchronized with the high-precision clock of the network device 1, achieving clock synchronization between the network device 1 and the network device 2.

[0034] The service board n of the network device 2 is connected to the Ethernet port of the network device 3. The PHYn chip on the service board n encodes the clock information synchronized with the network device 1 in this device into the Ethernet packet P2 and sends the Ethernet packet P2 containing the clock information to the network device 3. The network device 3 is not a frame network device and does not need to perform Figure 3 the in-frame clock signal synchronization shown. The PHY chip 20 of the network device 3 decodes the clock information from the received Ethernet packet, thus achieving clock synchronization among the network device 1, the network device 2, and the network device 3.

[0035] In this application, when the primary main control board fails, the standby main control board switches to the new primary main control board and notifies each service board 1 - service board n through a control channel (not shown in the figure). Signal selectors 1 - signal selector n respectively select the channel drivers 2 of the new main control board to output n clock signals a1', a2'... an'.

[0036] In this application, the multi-channel selectors 1 and 2 can also be other independent programmable logic devices, such as CPLD and FPGA. The controller selects the pins of these programmable logic devices that connect to the clock signal clock u1 by controlling the control pins of these programmable logic devices.

[0037] Figure 3 If the clock signals of each service board component of the network device shown in the figure are synchronized using the clock signals calibrated by the PLL chips of the service boards, then the frequency limitation of the clock signals output by the PHY chips on the service boards caused by the PLL chips of the main control board can be reduced, and the selection of the PHY chips on the service boards of the chassis network device is simplified.

[0038] Figure 1 In the existing clock synchronization scheme shown, the clock synchronization of the standby main control board depends on the clock signals calibrated by the primary main control board. In this application, the primary main control board and the standby main control board are synchronized within the chassis network device based on the clock signals calibrated by docking with the service boards of the upstream network device, avoiding Figure 1 the dependence of the standby main control board on the calibrated signals of the primary main control board in the scheme.

[0039] The above are only the preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the scope of protection of this application.

Claims

1. A clock signal synchronization method is applied to a frame network device, characterized in that the first service board docking with the upstream network device restores the upstream clock signal of the upstream network device, calibrates the local clock signal of the first service board based on the upstream clock signal, and outputs the calibrated local clock signal of the first service board to the first multi-channel selector of the active main control board and the second multi-channel selector of the standby main control board; the first multi-channel selector of the active main control board outputs the calibrated local clock signal of the first service board to the first multi-channel driver of the active main control board; the second multi-channel selector of the standby main control board outputs the calibrated local clock signal of the first service board to the second multi-channel driver of the standby main control board; the first and second multi-channel drivers respectively output a first set of multi-channel clock signals and a second set of multi-channel clock signals to the phase-locked loop chips of each service board; the clock signal selectors of the first service board, the second service board docking with the downstream network device, and other service boards select and input the first set of multi-channel clock signals to the phase-locked loop chips of each service board; the phase-locked loop chip of the first service board locks the restored upstream clock signal, and the phase-locked loop chips of the second service board and other service boards lock the first set of multi-channel clock signals and calibrate the local clock signals. Among them, the first service board docking with the upstream network device restoring the upstream clock signal of the upstream network device means that the Ethernet physical layer chip of the first service board restores the encoded upstream clock signal from the first Ethernet packet received from the Ethernet port docking with the upstream device; the first service board calibrating the local clock signal of the first service board based on the upstream clock signal includes: the Ethernet physical layer chip of the first service board outputs the restored upstream clock signal to the phase-locked loop chip of the first service board; the phase-locked loop chip of the first service board determines that the priority of the upstream clock signal is higher than the local clock signal of the crystal oscillator chip of the first service board; and calibrates the frequency of the local clock signal of the first service board according to the frequency of the upstream clock signal.

2. The method according to claim 1, characterized in that, The method further includes: the phase-locked loop chips of the second service board and other service boards input the calibrated local clock signals as reference clock signals to the Ethernet physical layer chips of their respective boards; the Ethernet physical layer chip of the second service board encodes the local board reference clock signal into a second Ethernet packet; the second service board sends the second Ethernet through the Ethernet port docking with the downstream device.

3. The method according to claim 1, characterized in that, The method further includes: the standby main control board switches to a new active main control board and notifies the first service board, the second service board, and the other service boards; the clock signal selectors of the first service board, the second service board, and the other service boards select and input the second set of multi-channel clock signals to the phase-locked loop chips of each service board.

4. A clock signal synchronization device, which is applied to an Ethernet in-frame network device, is characterized in that The device includes an active main control board, a standby main control board, a first service board docking with the upstream network device, a second service board docking with the downstream network device, and more than one other service board; The output end of the Ethernet physical layer chip of the first service board is connected to the phase-locked loop chip of this board, and the output end of the phase-locked loop chip of the first service board is connected to the first multi-channel selector of the active main control board and the second multi-channel selector of the standby main control board; The output ends of the first multi-channel selector and the multi-channel selector are respectively connected to the multi-channel drivers of the active main control board and the standby main control board of this board; The output ends of the multi-channel drivers of the active main control board are respectively connected to the first input ends of the clock signal selectors of each service board; the output ends of the multi-channel drivers of the standby main control board are respectively connected to the second input ends of the clock signal selectors of each service board; The upstream clock signal of the upstream network device recovered by the Ethernet physical layer chip of the first service board is input into the phase-locked loop chip of the first service board. The phase-locked loop chip of the first service board calibrates the local clock signal of the first service board based on the upstream clock signal, and outputs the calibrated local clock signal of the first service board to the first multi-channel selector and the second multi-channel selector; The first multi-channel selector outputs the calibrated local clock signal of the first service board to the first multi-channel driver; the second multi-channel selector outputs the calibrated local clock signal of the first service board to the second multi-channel driver; The first and second multi-channel drivers respectively output a first set of multi-channel clock signals and a second set of multi-channel clock signals to the phase-locked loop chips of each service board; The clock signal selectors of the first service board, the second service board docking the downstream network device, and other service boards select and input the first set of multi-channel clock signals to the phase-locked loop chips of each service board; The phase-locked loop chip of the first service board locks the recovered upstream clock signal, and the phase-locked loop chips of the second service board and other service boards lock the first set of multi-channel clock signals and calibrate the local clock signals.

5. The device according to claim 4, characterized in that, The first service board recovers the upstream clock signal of the upstream network device, which means that the Ethernet physical layer chip of the first service board recovers the encoded upstream clock signal from the first Ethernet packet received from the Ethernet port docking the upstream device; The first service board calibrates the local clock signal of the first service board based on the upstream clock signal, including: The Ethernet physical layer chip of the first service board outputs the recovered upstream clock signal to the phase-locked loop chip of the first service board; The phase-locked loop chip of the first service board determines that the priority of the upstream clock signal is higher than the local clock signal of the crystal oscillator chip of the first service board; and calibrates the frequency of the local clock signal of the first service board according to the frequency of the upstream clock signal.

6. The device according to claim 4, wherein The phase-locked loop chips of the second service board and other service boards input the calibrated local clock signals as reference clock signals into the Ethernet physical layer chips of their respective boards; The Ethernet physical layer chip of the second service board encodes the local reference clock signal of this board into the second Ethernet packet; The second service board sends the second Ethernet through the Ethernet port docked to the downstream device.

7. The device according to claim 4, wherein The standby main control board is switched to a new active main control board, and notifies the first service board, the second service board, and the other service boards; The clock signal selectors of the first service board, the second service board, and the other service boards select and pass the second group of multiplexed clock signals input to the phase-locked loop chips of each service board.

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