Method for manufacturing a semiconductor device and semiconductor device

Abstract

Embodiments of the present disclosure relate to methods for manufacturing semiconductor devices and semiconductor devices. A method for manufacturing a semiconductor device includes: providing a silicon-based substrate; depositing an oxide layer on the substrate; depositing a polysilicon layer on the oxide layer and simultaneously depositing a crystalline silicon layer on the substrate; manufacturing an electronic device based on the polysilicon layer; and installing a glass or silicon-based cover on the crystalline silicon layer.

Description

Technical Field

[0001] The present disclosure relates to a method of manufacturing a semiconductor device and the semiconductor device. Background Art

[0002] Sensor devices are an important and growing subfield within the semiconductor device field. These sensor devices can be manufactured as microelectromechanical (MEMS) sensors and are typically constructed so that they include a cavity that houses the actual sensor. In the case of an acceleration sensor, this consists of an elastically suspended seismic mass. When an external acceleration is applied, inertial forces act on the seismic mass, causing a deflection that can be detected using various methods, such as capacitive, piezoresistive, or optical.

[0003] For acceleration sensors of this type, as well as for pressure or vibration sensors, gyroscopes, or time acquisition components, it is crucial to provide high quality, i.e., low damping of the oscillating seismic mass. It is particularly important that the damping present after production remains constant over the entire service life of the sensor component.

[0004] For these and other reasons, the present disclosure is necessary. Summary of the Invention

[0005] A first aspect of the present disclosure relates to a method for manufacturing a semiconductor device, wherein the method comprises:

[0006] providing a silicon-based substrate;

[0007] depositing an oxide layer on the substrate;

[0008] Depositing a polysilicon layer on the oxide layer and simultaneously depositing a crystalline silicon layer on the substrate; manufacturing an electronic device based on the polysilicon layer;

[0009] A glass or silicon based cover is mounted on the crystalline silicon layer.

[0010] A second aspect of the present disclosure relates to a semiconductor device, comprising:

[0011] Silicon-based substrate;

[0012] an oxide layer disposed on the substrate;

[0013] polysilicon-based electronic devices;

[0014] a crystalline silicon layer disposed on the substrate and on sides of the oxide layer; and

[0015] A glass or silicon based cover that is connected to the crystalline layer.

[0016] The present invention is based on the recognition that the friction of the oscillating seismic mass against gas molecules, particularly air molecules, in the cavity is the dominant factor in damping, while the mechanical damping generated by the mass's suspension plays a secondary role. Therefore, it is crucial that the cavity does not outgas into the environment during the device's service life. This is made possible by the method according to the first aspect, which provides for attaching a glass or silicon cover to the crystalline silicon layer. As will be described later, this allows for an optimally tight connection between the cover and the crystalline silicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The semiconductor device and method for manufacturing the semiconductor device according to the present invention are explained in more detail below with reference to the accompanying drawings. The devices shown in the drawings are not necessarily drawn to scale relative to each other. Identical reference symbols may represent identical devices. The same reference numerals represent identical or similar parts.

[0018] Figure 1 has Figure 1A and 1B , and along Figure 1B The vertical section of the plane (A) represented by AA and the vertical section along Figure 1A A horizontal cross section along a plane (B) indicated by line BB in FIG. 1 shows an embodiment of a semiconductor device, wherein the semiconductor device is designed as an acceleration sensor.

[0019] Figure 2 A flow chart of a method for manufacturing a semiconductor device is shown.

[0020] Figure 3 has Figures 3A to 3E , and shows side cross-sectional views of intermediate products and semiconductor devices to illustrate an embodiment of a method for manufacturing the semiconductor device of FIG. 1 . DETAILED DESCRIPTION

[0021] In the following detailed description, reference is made to the accompanying drawings which form a part of this specification and in which are shown for illustrative purposes specific embodiments in which the present disclosure may be practiced. Directional terms such as "upper," "lower," "front," "rear," "leading," and the like are used in relation to the direction of the figure being described. Because the components of the embodiments can be positioned in various orientations, the direction designations are for illustrative purposes and are in no way limiting. It should be understood that other embodiments may be used and structural or logical changes may be made without exceeding the scope of the present disclosure. Therefore, the following detailed description should not be taken as limiting, and the scope of the present disclosure is defined by the appended claims.

[0022] It should be noted that, unless explicitly stated otherwise, the features of the various embodiments described herein may be combined with each other.

[0023] As used herein, the terms “bonded,” “fixed,” “connected,” “coupled,” and / or “electrically connected / electrically coupled” do not necessarily mean that elements or layers are in direct contact with one another; an intermediate element or layer may be provided between the elements being “bonded,” “fixed,” “connected,” “coupled,” and / or “electrically connected / electrically coupled.” However, according to the present disclosure, the above terms may also optionally have a specific meaning, namely, that the elements or layers are in direct contact with one another, that is, no intermediate element or layer is provided between the elements being “bonded,” “fixed,” “connected,” “coupled,” and / or “electrically connected / electrically coupled.”

[0024] Furthermore, the term "on..." as used herein with respect to a component, element, or material layer being formed or disposed "on" a surface may mean, for example, that the component, element, or material layer is disposed (e.g., placed, formed, deposited, etc.) "indirectly" on the underlying surface, with one or more additional components, elements, or layers disposed between the underlying surface and the component, element, or material layer. However, the term "on..." as used with respect to a component, element, or material layer being formed or disposed "on" a surface may alternatively have a specific meaning where the component, element, or material layer is disposed (e.g., placed, formed, deposited, etc.) "directly" on the underlying surface, such as in direct contact with the underlying surface.

[0025] Figure 1 has Figure 1A and 1B , and along Figure 1B The vertical section of the plane (A) represented by AA and the vertical section along Figure 1A A horizontal section through a plane (B) denoted by BB in FIG. 1 shows an embodiment of a semiconductor device in which the semiconductor component is designed as an acceleration sensor.

[0026] Specifically, Figure 1 shows a semiconductor device 10, which has: a silicon-based substrate 1; an oxide layer 2 arranged on the substrate 1; an electronic device 3 based on polycrystalline silicon; a crystalline silicon layer 4, which is arranged on the substrate 1 and on the side surface of the oxide layer 2; and a glass or silicon-based cover 5, which is connected to the crystalline layer 4.

[0027] The semiconductor device 10 is in the present case a sensor device, and the electronic device is an acceleration sensor, which will be discussed in more detail below.

[0028] The semiconductor device 10 also has electrical contacts on one or both surfaces of the substrate or the lid, and plated through holes leading to these electrical contacts, both of which are not shown here for the sake of clarity and simplicity.

[0029] The crystalline silicon layer 4 is grown simultaneously with the polysilicon layer, and the polysilicon layer then constitutes the acceleration sensor 3. The crystalline silicon layer 4 is grown by epitaxial growth on the substrate 1. This will be described in detail below.

[0030] As shown in FIG1 , the cover 5 may have a protrusion 5A connected to the crystalline silicon layer 4. In addition, the crystalline silicon layer 4 may be annular around the electronic device, and the protrusion itself may also be annular and have spatial dimensions corresponding to the spatial dimensions of the annular silicon layer. In particular, as shown in the figure, the protrusion 5 may have a constant transverse diameter over its entire circumference, and the crystalline silicon layer 4 may also have a constant transverse diameter over its entire circumference, wherein the transverse diameter of the protrusion 5A is preferably slightly smaller than the transverse diameter of the crystalline silicon layer 4, so that the protrusion 5A is connected to the crystalline layer 4 over its entire width.

[0031] 1 , the spatial region annularly surrounded by the crystalline silicon layer 4 and provided for arranging the acceleration sensor 3 has a rectangular or square shape. However, this region may also be provided with another geometric shape, such as a circle.

[0032] In the case of a silicon-based cover 5, it can be provided that it is mounted by a wafer bonding process on the crystalline silicon layer 4. This is due to the fact that the epitaxially grown crystalline silicon layer 4 has a high crystalline quality on its surface.

[0033] In the case of a cover body 5 based on glass or quartz, it can be provided that it is mounted on the crystalline silicon layer 4 by means of an anodic bonding process.

[0034] The electronic component 3 can be designed as a MEMS component or comprise such a component.

[0035] The electronic device 3 may also include one or more of a group including an acceleration sensor, a pressure sensor, a vibration sensor, a gyroscope, or a time acquisition device.

[0036] The semiconductor device 10 also has the advantage that the cover 5 is electrically connected to the crystalline layer 4 and thus to the substrate 1, so that no potential difference occurs between the two. Such a potential difference can be disadvantageous because it can generate electrostatic forces on the MEMS.

[0037] Figure 2 A flow chart of a method for manufacturing a semiconductor device is shown.

[0038] A method (100) for manufacturing a semiconductor device comprises:

[0039] Providing a silicon-based substrate (110);

[0040] depositing an oxide layer (120) on the substrate;

[0041] depositing a polysilicon layer on the oxide layer and simultaneously depositing a crystalline silicon layer on the substrate;

[0042] Manufacturing electronic devices (140) based on polysilicon layers;

[0043] A glass or silicon based cover is mounted on the crystalline layer (150).

[0044] Examples are described below to illustrate the method.

[0045] Figure 3 has Figures 3A to 3E , and shows side cross-sectional views of intermediate products and semiconductor devices to illustrate an embodiment of a method for manufacturing the semiconductor device of FIG. 1 .

[0046] It may be provided that the semiconductor component is one of a plurality of semiconductor components that are to be produced on a substrate designed as a silicon wafer.

[0047] Figure 3A A cross-sectional view of an intermediate product comprising a silicon-based substrate 1 is shown, onto which a first oxide layer 2 (SiO2) has been applied, onto which a first polysilicon layer 3A has been applied, and onto which a second oxide layer 2A (SiO2) has been applied. A portion of the first oxide layer 2 remains in the device and serves as an insulating layer, while the second oxide layer 2A is a sacrificial layer, as will be seen later.

[0048] The substrate 1 may have a thickness in the range of 100 μm to 1 mm, the first oxide layer 2 may have a thickness in the range of 5 μm to 10 μm, the first polysilicon layer 3A may have a thickness in the range of 1 μm to 2 μm, and the second oxide layer 2A may have a thickness in the range of 5 μm to 10 μm.

[0049] Figure 3B A cross-sectional view of another intermediate product obtained after removing annular portions of the first oxide layer 2 and the second oxide layer 2A is shown. The spatial location of this annular portion corresponds to the spatial location of the crystalline silicon layer to be formed. Portions of the second oxide layer 2A above the first polysilicon layer 3A are also removed to expose the first polysilicon layer 3A in these portions. This is used to prepare for the subsequent epitaxial deposition process of the second polysilicon layer 3B. These portions can be removed by an etching step, particularly dry etching.

[0050] Figure 3C : A cross-sectional view of an intermediate product obtained after epitaxial deposition is performed is shown. In this case, a second polysilicon layer 3B is epitaxially grown on the exposed portion of the first polysilicon layer 3A. A crystalline silicon layer (c-Si) 4 is also epitaxially grown on the exposed annular portion of the crystalline substrate 1 (crystalline is used synonymously with single crystal throughout this document). The crystalline silicon layer 4 thus also covers the side surfaces of the oxide layer 2. The second polysilicon layer 3B can have a thickness in the range of 15 μm to 25 μm, and the crystalline silicon layer 4 can have a thickness in the range of 30 μm to 40 μm.

[0051] The deposition of the second polysilicon layer 3B and the crystalline silicon layer 4 can be carried out from the gas phase at reduced pressure in a conventional epitaxial reactor. Deposition can be performed by first depositing a thin (approximately 100 nm) seed layer composed of polysilicon and silane (SiH4) on the second oxide layer 2A in the subsequent sensor cell region at 800°C and 600 Torr in an H2 carrier with a SiH4 gas flow rate of 60 sccm for 90 seconds. Deposition can then be continued using dichlorosilane (DCS, SiH2Cl2) at 1080°C and 30 Torr to epitaxially form a second polysilicon layer 3B with a thickness of approximately 20 μm in an H2 carrier at a flow rate of 400 sccm. To impart conductivity to the second polysilicon layer 3B, the polysilicon is in situ n-doped during growth by adding monophosphine (PH3) at a flow rate of 100 sccm. Under the described deposition conditions, the growth rate during growth of the second polysilicon layer 3B can be approximately 1 μm / min.

[0052] The n-doping of second polysilicon layer 3B by the addition of monophosphine during growth naturally also results in n-doping of crystalline silicon layer 4, which then also becomes conductive. Even greater conductivity than in second polysilicon layer 3B can be expected due to the presence of grain boundaries in the latter, which have the property of trapping some of the dopant atoms, which are then no longer able to act as electron donors. Such grain boundaries do not exist in (single)crystalline silicon, or, if they do exist, only at a significantly lower density.

[0053] It should also be mentioned that doping during the growth process is not absolutely necessary. Undoped silicon can also be grown. If certain parts of the MEMS sensor need to be conductive, separate ion implantations can also be performed.

[0054] After the deposition process is completed, chemical mechanical polishing (CMP) may be performed on the surface of the second polysilicon layer 2A, in particular, because it is well known that a polysilicon layer grown from a gas phase has a high surface roughness.

[0055] Figure 3E 1 and how it is obtained after mounting a cover 5 based on glass or silicon on a crystalline silicon layer 4. The cover 5 is prefabricated so that it has an annular protrusion 5A which corresponds in its spatial dimensions to the spatial dimensions of the annular crystalline silicon layer 4.

[0056] As already mentioned, the substrate can be provided as a silicon-based wafer, thereby producing a large number of sensor elements using the above method steps. Similarly, a cover wafer can then be provided, on which a large number of cover elements are prefabricated. The cover elements are essentially defined by annular protrusions 5A, which are spatially distributed so that they lie above the MEMS sensors on the substrate wafer.

[0057] If both the substrate wafer and the cover wafer are designed as silicon wafers, the two can be connected to each other via direct silicon bonding. In this method, which is known per se, the two wafers are pressed together at high temperature and high pressure. The process temperature can, for example, range from 500°C to 1200°C, while the pressure can range from 15 MPa to 20 MPa. In the case of a cover wafer based on glass or quartz, anodic bonding can be used, in which a glass wafer is brought into contact with a silicon wafer and a voltage is applied such that the negative polarity is applied to the glass. The process temperature here is typically above 300°C, and the voltage is in the range of 50 to 1000 V.

[0058] It can be proposed that the bonding is carried out under ambient conditions so that the cavity in the manufactured sensor device is filled with air at atmospheric pressure. However, it can also be proposed that the bonding is carried out such that a weak vacuum is generated in the cavity or another gas is filled in the cavity.

[0059] Example

[0060] Hereinafter, the method and apparatus according to the present disclosure are explained using examples.

[0061] Example 1 is a method for manufacturing a semiconductor device, the method including:

[0062] providing a silicon-based substrate;

[0063] depositing an oxide layer on the substrate;

[0064] Depositing a polysilicon layer on the oxide layer and simultaneously depositing a crystalline silicon layer on the substrate; manufacturing an electronic device based on the polysilicon layer;

[0065] A glass or silicon based cover is mounted on the crystalline silicon layer.

[0066] Example 2 is a method according to Example 1, wherein the cover has a protrusion connected to the crystal layer.

[0067] Example 3 is the method of example 1 or 2, wherein the crystalline layer annularly surrounds the electronic device.

[0068] Example 4 is the method according to Examples 2 and 3, wherein the protrusion is formed in a ring shape, and the protrusion has a spatial size corresponding to a spatial size of the crystal layer.

[0069] Example 5 is a method according to any of the preceding examples, wherein mounting the silicon-based cover on the crystalline layer comprises wafer bonding.

[0070] Example 6 is the method of Example 5, wherein wafer bonding is performed at a temperature greater than 500°C.

[0071] Example 7 is a method according to any of the preceding examples, wherein mounting the glass-based cover on the crystalline layer comprises anodic bonding.

[0072] Example 8 is the method of any of the preceding examples, wherein depositing the polysilicon layer and depositing the crystalline layer include growing the layers from a vapor phase using silane.

[0073] Example 9 is a method according to any of the preceding examples, wherein manufacturing the electronic device includes manufacturing a MEMS device.

[0074] Example 10 is the method of Example 9, wherein the MEMS device has one or more of the group consisting of: an acceleration sensor, a pressure sensor, a vibration sensor, a gyroscope, or a time acquisition device.

[0075] Example 11 is a semiconductor device comprising:

[0076] Silicon-based substrate;

[0077] an oxide layer disposed on the substrate;

[0078] polysilicon-based electronic devices;

[0079] a crystalline silicon layer disposed on the substrate and on sides of the oxide layer; and

[0080] A glass or silicon based cover that is connected to the crystalline layer.

[0081] Example 12 is the semiconductor device of Example 11, wherein the cover has a protrusion connected to the crystalline silicon layer.

[0082] Example 13 is a semiconductor device according to Example 11 or 12, wherein the crystalline silicon layer annularly surrounds the electronic device.

[0083] Example 14 is the semiconductor device according to Examples 12 and 13, wherein the protrusion is formed in a ring shape, and has a spatial size corresponding to a spatial size of the crystalline silicon layer.

[0084] Example 15 is a semiconductor device according to any one of Examples 11 to 14, wherein the electronic device has a MEMS device.

[0085] Example 16 is a semiconductor device according to any one of Examples 11 to 15, wherein the MEMS device has one or more of the group consisting of: an acceleration sensor, a pressure sensor, a vibration sensor, a gyroscope, or a time acquisition device

[0086] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This proposal is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present disclosure is intended to be limited only by the claims and their equivalents.

Claims

1. A method (100) for manufacturing a semiconductor device, wherein the method comprises: Providing a silicon-based substrate (110); depositing an oxide layer (120) on the substrate; removing the annular portion of the oxide layer to expose the annular portion on the substrate; depositing a polysilicon layer on the oxide layer, and simultaneously depositing a crystalline silicon layer on the annular portion exposed on the substrate to form an annular crystalline silicon layer (130); manufacturing an electronic device (140) based on the polysilicon layer, wherein the crystalline silicon layer surrounds the electronic device in an annular shape; A glass or silicon based cover is mounted on the crystalline silicon layer (150). 2 . The method according to claim 1 , wherein the cover has a protrusion connected to the crystalline silicon layer. 3 . The method according to claim 2 , wherein the protrusion is formed in a ring shape, and has a spatial size corresponding to a spatial size of the crystalline silicon layer. 4 . The method of claim 1 , wherein mounting a silicon-based cover on the crystalline silicon layer comprises wafer bonding. The method according to claim 4 , wherein the wafer bonding is performed at a temperature above 500° C.

6. The method of any one of claims 1 to 3, wherein mounting a glass-based cover on the crystalline silicon layer comprises anodic bonding.

7. The method of any one of claims 1 to 3, wherein depositing the polysilicon layer and depositing the crystalline silicon layer comprises growing these layers from a vapor phase using silane.

8. The method according to any one of claims 1 to 3, wherein fabricating an electronic device comprises fabricating a MEMS device. 9 . The method according to claim 8 , wherein the MEMS device comprises one or more items selected from the group consisting of an acceleration sensor, a pressure sensor, a vibration sensor, a gyroscope, or a time acquisition device.

10. A semiconductor device (10), comprising: Silicon-based substrate (1); an oxide layer (2) disposed on the substrate (1); Polysilicon-based electronic devices (3); a crystalline silicon layer (4) arranged on the substrate (1) and on the side of the oxide layer (2), wherein the crystalline silicon layer (4) annularly surrounds the electronic device (3); and a cover (5) based on glass or silicon, said cover being connected to said crystalline silicon layer (4), The semiconductor device is manufactured by the method according to claim 1 .

11. The semiconductor device (10) according to claim 10, wherein the cover (5) has a protrusion (5A) connected to the crystalline silicon layer (4).

12. The semiconductor device (10) according to claim 11, wherein the protrusion (5A) is formed in a ring shape, and the protrusion has a spatial size corresponding to a spatial size of the crystalline silicon layer (4).

13. The semiconductor component (10) according to claim 10, wherein the electronic component (3) comprises a MEMS device.

14. The semiconductor device (10) according to any one of claims 10 to 12, wherein the electronic device (3) has one or more items selected from the group consisting of an acceleration sensor, a pressure sensor, a vibration sensor, a gyroscope, or a time acquisition device.

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