A circuit board for chip testing

Abstract

The present application discloses a circuit for chip testing. The chip includes at least a first peripheral pin and a second peripheral pin. The circuit board has opposite first and second surfaces. The circuit board includes: a first pad and a second pad located on the first surface, the first pad being used for electrically connecting to the first peripheral pin, and the second pad being used for electrically connecting to the second peripheral pin; a first single-ended trace and a second single-ended trace on the same layer, the first single-ended trace being electrically connected to the first pad; the second single-ended trace being electrically connected to the second pad; wherein, the impedances of the first single-ended trace and the second single-ended trace satisfy the same conditions, so that the first single-ended trace and the second single-ended trace can transmit a set of differential signals. When the technical solution of the present application is used for chip high-speed interface testing, it can reduce the influence of the impedance discontinuity of the reference plane in the circuit board on the test result, and improve the test accuracy and reliability.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and more specifically, to a circuit for chip testing. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily lives and work, bringing great convenience to people's daily lives and work and becoming an indispensable important tool for people today.

[0003] The core component of an electronic device to realize various components is a chip. With the continuous improvement of the performance of electronic devices, the performance of chips is also becoming more and more powerful, which requires the chip interface to have a high-speed interface to meet the performance requirements. Typical high-speed interfaces include PCIE interfaces, Ethernet interfaces, etc. High-speed interfaces generally use an AC-coupled differential low-voltage mode for transmission. Due to the high signal transmission rate, the signal integrity test of the chip high-speed interface has become a difficult problem. Summary of the Invention

[0004] In view of this, this application provides a circuit for chip testing, and the solution is as follows:

[0005] A circuit board for chip testing, the chip includes at least a first peripheral pin and a second peripheral pin, the circuit board has opposite first and second surfaces, and the circuit board includes:

[0006] A first pad and a second pad located on the first surface, the first pad is used for electrical connection with the first peripheral pin, and the second pad is used for electrical connection with the second peripheral pin;

[0007] A first single-ended trace and a second single-ended trace on the same layer, the first single-ended trace is electrically connected to the first pad; the second single-ended trace is electrically connected to the second pad;

[0008] Wherein, the impedances of the first single-ended trace and the second single-ended trace meet the same conditions, so that the first single-ended trace and the second single-ended trace can transmit a group of differential signals.

[0009] Preferably, in the above circuit board, the first single-ended trace and the second single-ended trace have the same line width, and the distance between the first single-ended trace and the second single-ended trace is at least greater than 3 times the line width.

[0010] Preferably, in the above circuit board, there is a single-ended trace layer in the circuit board between the first surface and the second surface, and the single-ended trace layer includes the first single-ended trace and the second single-ended trace.

[0011] Preferably, in the above circuit board, the circuit board includes:

[0012] Ground metal layers and wiring layers stacked alternately; One wiring layer located between two adjacent ground metal layers serves as the single-ended trace layer;

[0013] Wherein, the circuit board has a first signal hole and a second signal hole; The first signal hole is used to connect the first pad and the first single-ended trace; The second signal hole is used to connect the second pad and the second single-ended trace.

[0014] Preferably, in the above circuit board, the ground metal layer has an anti-pad, and the anti-pad is a hollowed-out area penetrating through the ground metal layer;

[0015] Wherein, the vertical projection of the first signal hole on the second surface and the vertical projection of the second signal hole on the second surface are both located within the vertical projection of the hollowed-out area on the second surface.

[0016] Preferably, in the above circuit board, the first pad is soldered to the first external pin, and the second pad is soldered to the second external pin;

[0017] The vertical projection of the first signal hole on the second surface is located within the vertical projection of the first pad on the second surface;

[0018] The vertical projection of the second signal hole on the second surface is located within the vertical projection of the second pad on the second surface.

[0019] Preferably, in the above circuit board, in a first direction, the hollowed-out area has opposite first and second sides; The first direction is perpendicular to the line connecting the centers of the first signal hole and the second signal hole, and parallel to the first surface and the second surface;

[0020] Both the first single-ended trace and the second single-ended trace cross the first side or the second side to lead out of the hollowed-out area;

[0021] Wherein, the distance between the first side and the second side in the first direction is less than Y; Y is the distance between the centers of the first signal hole and the second signal hole.

[0022] Preferably, in the above circuit board, in a second direction, both the first side and the second side have opposite first and second ends; The second direction is parallel to the line connecting the centers of the first signal hole and the second signal hole, and parallel to the first surface and the second surface;

[0023] The first end of the first side is connected to the first end of the second side by a first arc, and the second end of the second side is connected to the second end of the second side by a second arc; the radii of the first arc and the second arc are both Y / 2; the center of the first arc is the center of the first signal hole; the center of the second arc is the center of the second signal hole.

[0024] Preferably, in the above circuit board, the first side has a first straight side and a second straight side; the first straight side and the second straight side are located on a first straight line, and the two are connected by a first arc-shaped side;

[0025] The second side has a third straight side and a fourth straight side; the third straight side and the fourth straight side are located on a second straight line, and the two are connected by a second arc-shaped side;

[0026] In the second direction, both the first arc-shaped side and the second arc-shaped side are located between the first signal hole and the second signal hole;

[0027] Wherein, the first straight line and the second straight line are parallel, and both are parallel to the second direction; the first arc-shaped side and the second arc-shaped side protrude towards the connection line between the center holes of the first signal hole and the second signal hole;

[0028] And / or, Z = X - 1.5W, where Z is half of the distance between the first straight line and the second straight line; X is the center distance between the first signal hole or the second signal hole and a ground hole adjacent in the first direction; W is the line width of the first single-ended trace and the second single-ended trace.

[0029] Preferably, in the above circuit board, the vertical projections on the second surface of the parts of the first single-ended trace and the second single-ended trace led out from the anti-pad side do not overlap with the vertical projection of the hollowed-out area on the second surface.

[0030] As can be seen from the above description, in the circuit for chip testing provided by the technical solution of the present application, the chip includes at least a first peripheral pin and a second peripheral pin. The circuit board has opposite first and second surfaces, and the circuit board includes: a first pad and a second pad located on the first surface, the first pad being used for electrically connecting with the first peripheral pin, and the second pad being used for electrically connecting with the second peripheral pin; a first single-ended trace and a second single-ended trace on the same layer, the first single-ended trace being electrically connected to the first pad; the second single-ended trace being electrically connected to the second pad; wherein, the impedances of the first single-ended trace and the second single-ended trace satisfy the same conditions, so that the first single-ended trace and the second single-ended trace can transmit a set of differential signals. Compared with using single-ended traces to replace conventional differential traces, the technical solution of the present application can reduce the influence of the discontinuity of the reference plane impedance in the circuit board on the test results when used for chip high-speed interface testing, and improve the test accuracy and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0032] The structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those who are familiar with this technology to understand and read, and are not used to limit the limited conditions that the present application can be implemented. Therefore, they do not have technical substance. Any modification of the structure, change of the ratio relationship or adjustment of the size should still fall within the scope that can be covered by the technical content disclosed in the present application without affecting the effects that the present application can produce and the purposes that can be achieved.

[0033] Figure 1 It is a schematic structural diagram of a circuit board for chip testing;

[0034] Figure 2 It is a schematic structural diagram of a circuit board for chip testing provided by an embodiment of the present application;

[0035] Figure 3 It is a top view of a circuit board with a differential output method;

[0036] Figure 4 It is a top view of a circuit board provided by an embodiment of the present application;

[0037] Figure 5 It is a schematic structural diagram of the shape of an anti-pad in a circuit board provided by an embodiment of the present application;

[0038] Figure 6 Another structural schematic diagram of the anti-pad shape in the circuit board provided by the embodiment of the present application. Detailed implementation manners

[0039] Next, the embodiments in the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0040] Since the signal transmission rate of the high-speed interface is very high, and the common test probes for low-speed signal transmission have various parasitic parameters, directly using the probe to measure the electrical signal will bring great reflection and loss problems. The general practice in the industry is to design a dedicated test device to solder the chip to be tested on the device, and then connect the test connector led out from the device to the test instrument. Since this device is used for testing the high-speed interface of the chip, it means that the device itself needs to minimize the impact on the high-speed signal transmission of the interface to ensure the test accuracy of the high-speed signal. The design of the wire-out structure of the chip soldering part (package area) is very critical because the area is relatively small, and there are many traces, pads, vias, etc., which are likely to cause signal reflection. Therefore, it is particularly important to design an optimized wire-out structure.

[0041] Currently, the high-speed interface in the chip is generally a differential interface. The conventional circuit board for chip testing is generally connected to the high-speed interface in the chip through a differential wire-out method. The effect of the differential wire-out method of the circuit board in the chip package area is very poor. This is because the differential wire-out method requires two traces on the circuit board to be arranged in parallel at a short distance, resulting in the wire layout not being able to be arranged based on the space in the circuit board, resulting in a large occupied area. Moreover, due to the existence of the anti-pad in the chip package area of the circuit board, it is easy to cause the incompleteness of the reference planes of the upper and lower layers of the traces, resulting in a high impedance in the package area and affecting signal reflection.

[0042] Refer to Figure 1 as shown Figure 1 A structural schematic diagram of a circuit board for chip testing is shown. The circuit board shown adopts a differential wire-out method. The circuit board shown includes:

[0043] The first signal via Via11 and the second signal via Via12;

[0044] The first differential signal line L11 connected to the first signal via Via11;

[0045] The second differential signal line L12 connected to the second signal via Via12;

[0046] Multi - layer grounded metal layer 11;

[0047] Among them, the first differential signal line L11 and the second differential signal line L12 are on the same layer and are located between two adjacent layers of the grounded metal layer 11. There is an insulating layer between the two differential signal lines and the upper and lower grounded metal layers 11. The grounded metal layer 11 has an anti - pad 111, and the anti - pad 111 is a hollowed - out area provided on the grounded metal layer 111. The first signal via Via11 and the second signal via Via12 are located within the area of the anti - pad 111, so that the first signal via Via11 and the second signal via Via12 have no contact with the grounded metal layer 11. The grounded metal layer adjacent to the two differential signal lines is the reference plane.

[0048] The surface of the circuit board has a packaging area for bonding the chip to be tested. In the direction perpendicular to the circuit board, the anti - pad 111 is located within the packaging area. Due to the existence of the anti - pad 111, the reference plane is incomplete. When the differential signal line is led out from the signal via, in the direction perpendicular to the circuit board, the differential signal line and the anti - pad 111 have an overlapping part, as Figure 1 shown by the area of the two differential signal lines and the anti - pad 111 in the region indicated by the dashed ellipse in the figure. This overlapping part causes impedance polarization, affects the reflection of the signal, and thus affects the accuracy and reliability of the test. Moreover, since the two differential signal lines must be arranged in parallel at a close distance, and due to the limited wiring space in the circuit board, the differential signal line led out from the anti - pad 111 and the anti - pad 111 have an overlapping part, as Figure 1 shown by the area of one differential signal line and the anti - pad 111 in the region indicated by the dashed rectangle in the figure. This overlapping part also causes a high impedance, affects the reflection of the signal, and thus affects the accuracy and reliability of the test.

[0049] In view of this, the embodiment of the present application provides a circuit board for chip testing. The circuit board adopts single - ended routing. Compared with the differential routing method, the two single - ended signal lines connecting two differential high - speed interfaces do not need to be arranged in parallel at a close distance. Based on the space of the circuit board and the layout of the vias and other signal lines in the circuit board, the single - ended signal lines can be freely arranged, thereby reducing the overlapping area between the single - ended signal lines and the anti - pad, so as to solve the problem of high impedance caused by too large overlapping area and affecting signal reflection, and improve the accuracy and reliability of the test.

[0050] In order to make the above - mentioned objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] Refer to Figure 2 as shown Figure 2Schematic diagram of a circuit board for chip testing provided by an embodiment of the present application. The chip includes at least a first peripheral pin and a second peripheral pin. The first pin and the second pin are respectively connected to a signal interface of the chip to be tested. The signal interface can be a high-speed signal interface, including but not limited to a PCIE interface, an Ethernet interface, etc. The circuit board has opposite first surface S1 and second surface S2.

[0052] The circuit board includes:

[0053] A first pad PAD21 and a second pad PAD22 located on the first surface S1. The first pad PAD21 is used for electrically connecting to the first peripheral pin, and the second pad PAD22 is used for electrically connecting to the second peripheral pin;

[0054] A first single-ended trace L21 and a second single-ended trace L22 on the same layer. The first single-ended trace L21 is electrically connected to the first pad PAD21; the second single-ended trace L22 is electrically connected to the second pad PAD22;

[0055] Wherein, the impedances of the first single-ended trace L21 and the second single-ended trace L22 satisfy the same condition, that is, their impedances are the same or approximately the same, so that the first single-ended trace L21 and the second single-ended trace L22 can transmit a set of differential signals.

[0056] The first single-ended trace L21 and the second single-ended trace L22 do not need to be parallel, and the distance between them can be set very large. Therefore, they can be separately routed based on the routing space in the circuit board. The routing method is free, and it is easy to avoid anti-pads, vias, and other traces, which can reduce the occupied area of routing and is not easily affected by incomplete reference planes.

[0057] Specifically, assuming the line width is W and the gap between two differential signal lines in the differential output mode is m, in the cross-section perpendicular to the extension direction of the trace, a wide area of 2W + m is required for routing. While using the single-ended output mode of the present application, in the cross-section perpendicular to the extension direction of the trace, each of the two single-ended traces requires a width area of W, and a total of 2W wide area is required for routing. Since the two signal lines can be separately routed without the gap limit of m, the occupied area of routing is reduced.

[0058] In the embodiments of the present application, the circuit board adopts single-ended routing. Compared with the differential routing method, the two single-ended traces connecting two differential high-speed interfaces do not need to be arranged in parallel at a short distance. Based on the space of the circuit board and the layout of vias and other traces in the circuit board, the single-ended traces can be freely arranged, thereby reducing the overlapping area between the single-ended traces and anti-pads, so as to solve the problem of high impedance caused by too large overlapping area and affecting signal reflection. It can be seen that the technical solution of the present application sets the outgoing lines of the high-speed interfaces of the chips to be tested as single-ended traces, reducing the impact of impedance discontinuity caused by incomplete reference planes.

[0059] Set the first single-ended trace L21 and the second single-ended trace L22 to have the same line width, so that the two meet the condition of the same impedance, so as to be able to transmit differential signals adapted to the high-speed interfaces of the chips to be tested. And set the distance between the first single-ended trace L21 and the second single-ended trace L22 to be at least greater than 3 times the line width, so that the two have no coupling.

[0060] In the embodiments of the present application, the single-ended inner-layer outgoing line method is adopted to arrange the two single-ended traces inside the circuit board. Specifically, a single-ended trace layer is provided inside the circuit board between the first surface S1 and the second surface S2, and the single-ended trace layer includes the first single-ended trace L21 and the second single-ended trace L22. The single-ended inner-layer outgoing line method reduces the electroplating process during PCB processing compared with the outer-layer routing method, and can make the line width consistency of the inner-layer single-ended traces better.

[0061] In order to ensure that the differential impedance matching between the two single-ended traces and the chips to be tested is not affected after the outgoing lines, the impedance of each individual trace is set to be equal to half of the differential impedance of the chips to be tested. The line width of the single-ended trace can be determined based on the following formula according to the PCB material selected for the circuit board, the distance between the single-ended trace and the reference plane, and the thickness of the trace.

[0062] Zo = [60 / sqrt(Er)]ln{4H / [0.67π(T+0.8W)]} (1)

[0063] Where Zo is the impedance of a single-ended trace, W is the line width of a single-ended trace, T is the thickness of a single-ended trace, H is the distance between a single-ended trace and the reference plane, and Er is the dielectric constant of the PCB material. The two single-ended traces W meet the same conditions, T meet the same conditions, and H meet the same conditions, so that their Zo meet the same conditions. In the embodiments of the present application, meeting the same conditions means being equal or approximately equal.

[0064] Such as Figure 2As shown, the circuit board includes: a ground metal layer 21 and a wiring layer 22 that are alternately stacked; the wiring layer is used to form traces in the circuit board. One wiring layer 22 located between two adjacent ground metal layers 21 serves as the single-ended trace layer, that is, the traces in the wiring layer 22 serving as the single-ended trace layer surround the first single-ended trace L21 and the second single-ended trace L22. In this way, by adopting the single-ended inner-layer trace-out method, the two single-ended traces are arranged inside the circuit board. The single-ended inner-layer trace-out method reduces the electroplating process during PCB processing compared with the outer-layer trace method, and can make the line width consistency of the inner-layer single-ended traces better. Figure 2 Only the wiring layer 22 serving as the single-ended trace layer is shown in [Figure], and other wiring layers are not marked and shown. There is an insulating layer between the adjacent ground metal layer 21 and the wiring layer 22. Each ground metal layer 21 is connected through a ground via Via23.

[0065] Wherein, the circuit board has a first signal via Via21 and a second signal via Via22; the first signal via Via21 is used to connect the first pad PAD21 and the first single-ended trace L21; the second signal via Via22 is used to connect the second pad PAD22 and the second single-ended trace L22.

[0066] To avoid short circuits between the traces in the wiring layer 22 and the ground metal layer 21, the ground metal layer 21 is provided with an anti-pad 211, and the anti-pad 211 is a hollowed-out area penetrating the ground metal layer 21; wherein, the vertical projection of the first signal via Via21 on the second surface S2 and the vertical projection of the second signal via Via22 on the second surface S2 are both located within the vertical projection of the hollowed-out area on the second surface S2. Among the ground metal layers 21 of each layer, the anti-pads 211 are the same and are arranged vertically and oppositely, that is, in the direction perpendicular to the circuit board, the anti-pads 211 in each ground metal layer 21 coincide.

[0067] Wherein, the shape of the anti-pad 211 can be set based on requirements. Figure 2 Only a rectangle is used to illustrate the anti-pad 211 in [Figure]. In other cases, the anti-pad 211 can also be set as a runway shape, or a circular shape corresponding to each signal via separately, or other shapes, etc. The embodiments of the present application do not make specific limitations on this.

[0068] Refer to Figure 3 As shown in Figure 3It is a top view of a circuit board with a differential routing method. In the shown circuit board, the through-holes are all connected to the corresponding pads through fan-out lines. For example, the first signal hole Via11 connecting the first differential signal line is connected to the pad PAD11 through the fan-out line 01, the second signal hole Via12 connecting the second differential signal line is connected to the pad PAD12 through the fan-out line 02, and the ground hole Via13 is connected to the pad PAD13 through the deletion line 03. Since the anti-pad 111 is provided on the ground metal layer 11, and the fan-out line routing method is used to connect the pad and the signal hole, there is an overlapping area between the fan-out line and the anti-pad 111 (such as Figure 3 the area shown by the dashed ellipse in

[0069] ), which will cause the reference plane of the fan-out line to be missing in this overlapping area, resulting in a high impedance, signal reflection, and affecting the accuracy and reliability of the test. Figure 4 shown.

[0070] Refer to Figure 4 shown, Figure 4 This is a top view of a circuit board provided by an embodiment of the present application. Combining Figure 2 and Figure 4 , the first pad PAD21 is soldered to the first peripheral pin, and the second pad PAD22 is soldered to the second peripheral pin; the vertical projection of the first signal hole Via21 on the second surface S2 is located within the vertical projection of the first pad on the second surface; the vertical projection of the second signal hole Via22 on the second surface is located within the vertical projection of the second pad on the second surface.

[0071] In Figure 4 the shown method, the through-hole-in-pad routing method is directly adopted. Therefore, there is no need for fan-out lines on the first surface S1, and there is no problem of signal reflection in the overlapping part of the fan-out line and the anti-pad caused by the missing reference plane, reducing the impact of impedance discontinuity caused by wire fan-out.

[0072] There are multiple vias provided in the circuit board, and the vias are used as signal holes or ground holes. Generally, the impedance of the vias in the circuit board is mainly capacitive, that is, compared with the wire impedance, the impedance of the vias is lower. The anti-pad 211 in the circuit board is the isolation part between the via and the reference layer. The larger the isolation part, the smaller the capacitance. Therefore, the area of the anti-pad is inversely proportional to the impedance.

[0073] In order to increase the via impedance, it is necessary to maximize the area of the anti-pad 211 as much as possible. In the embodiment of the present application, the shape of the anti-pad 211 can be as Figure 5 shown.

[0074] Refer to Figure 5 shown,Figure 5 This is a schematic structural diagram of the shape of an anti-pad in a circuit board provided by an embodiment of the present application. In this method, the anti-pad 211 includes two circular regions (as shown by the two dashed circles in Figure 5 ). The radii of the two circular regions are the same, and the radius is equal to half of the center distance between the first signal via Via21 and the second signal via Via22. Figure 5 The two dashed circles in Figure 5 are only used to indicate the two circular regions. The actual boundary of the anti-pad 211 is as shown by the solid hollowed-out region in

[0075] In Figure 5 The shown method is beneficial to improving the via impedance. However, due to the problem of incomplete reference plane caused by the anti-pad, when the single-ended trace leads out from the corresponding signal via to the anti-pad 211 region, there will be a large overlapping part between the single-ended trace and the anti-pad 211 region, which is not conducive to the impedance continuity of the single-ended trace and will cause multiple reflections. Therefore, it is necessary to consider the via impedance and the impedance continuity of the single-ended trace as a compromise.

[0076] In order to make the signal via in the anti-pad 211 have a large impedance while ensuring good impedance continuity when the single-ended trace leads out from the corresponding signal via, it is necessary to first determine the aperture of the via, the distance Y between adjacent signal vias, and the width W of the trace, and then calculate the anti-pad 211 with appropriate size and shape. By optimizing the shape and size of the anti-pad 211 in the circuit board, the influence of impedance discontinuity caused by the via is reduced. At this time, the shape of the anti-pad in the circuit board can be as shown in Figure 6 .

[0077] Refer to Figure 6 shown in Figure 6 This is another schematic structural diagram of the shape of an anti-pad in a circuit board provided by an embodiment of the present application. In this method, in the first direction, the hollowed-out region has opposite first and second side edges. The first direction is perpendicular to the center line connecting the center of the first signal via Via21 and the center of the second signal via Via22, and parallel to the first surface S1 and the second surface S2, that is, Figure 6 the horizontal direction in

[0078] In Figure 6In it, the left and right sides of the anti-pad 211 are divided into a first side and a second side. Taking the left side of the anti-pad 211 as the first side and the right side as the second side as an example, both the first single-ended trace L21 and the second single-ended trace L22 cross the first side and lead out of the hollow area. Obviously, in other ways, it is also possible to set both the first single-ended trace L21 and the second single-ended trace L22 to cross the second side and lead out of the hollow area.

[0079] Wherein, the distance between the first side and the second side in the first direction is less than Y, that is Figure 6 The maximum distance between the left and right sides of the anti-pad 211 in it is less than Y; Y is the center distance between the first signal hole Via21 and the second signal hole Via22.

[0080] Figure 5 In the shown way, the maximum distance between the left and right sides of the anti-pad 211 is Y. In this application, the maximum distance between the left and right sides is less than Y. Therefore, compared with Figure 5 the shown way, Figure 6 the shown way can shorten the size of the anti-pad 211 in the first direction. Since the size of the anti-pad 211 in the first direction is shortened, and both the first single-ended trace L21 and the second single-ended trace L22 cross the first side or the second side and lead out of the hollow area, therefore, Figure 6 the shown way can reduce the overlapping part of the single-ended trace and the anti-pad 211 area, thereby improving the continuity of the trace impedance and reducing signal reflection caused by incomplete reference planes.

[0081] The first pad PAD21 and the second pad PAD22 have the same shape and size, such as both can be circular. The first pad PAD21 and the second pad PAD22 have a preset non-zero distance from the boundary of the hollow area serving as the anti-pad 211 to avoid short-circuiting between the first pad PAD21 and the second pad PAD22 and the ground metal layer 21.

[0082] In Figure 6 the shown way, in the second direction, both the first side and the second side have opposite first ends and second ends. The second direction is parallel to the center line connecting the center of the first signal hole and the center of the second signal hole, and parallel to the first surface S1 and the second surface S2, that is Figure 6 the vertical direction in it is the second direction. The first end of the first side is connected to the first end of the second side by a first arc, and the second end of the second side is connected to the second end of the second side by a second arc; the radii of both the first arc and the second arc are Y / 2; the center of the first arc is the center of the first signal hole; the center of the second arc is the center of the second signal hole.

[0083] In Figure 6 the shown manner, the upper ends of the left and right sides of the anti-pad 211 can be used as the first end, and the lower ends as the second end. Then, the first arc is Figure 6 the arc connecting the left and right sides at the upper end of the anti-pad 211 in Figure 6 and the second arc is

[0084] the arc connecting the left and right sides at the lower end of the anti-pad 211 in Figure 6 Taking the left side in Figure 6 as the first side as an example, the left side includes a first straight side and a second straight side. The first straight side and the second straight side are located on the first straight line, and the two are connected by a first arc side in the middle to Figure 6 make the left side in

[0085] The distance between the first straight line and the second straight line is less than Y and greater than the diameters of the first pad PAD21 and the second pad PAD22, that is, Z is less than Y / 2. The diameters of the first pad PAD21 and the second pad PAD22 are the same.

[0086] Wherein, the first straight line and the second straight line are parallel, and both are parallel to the second direction; the first arc side and the second arc side protrude towards the center line connecting the center holes of the first signal hole Via21 and the second signal hole Via22. In this way, the distance between the middle part of the first side and the middle part of the second side can be shortened.

[0087] There are multiple ground holes in the circuit board, such as Figure 6As shown, when the second single-ended trace L22 leads out from the anti-pad 211 on the left side, in order to avoid the adjacent ground via Via23 on the left side, after the second single-ended trace L22 extends horizontally to the left for a certain distance from the second signal via Via22, it needs to extend vertically downward for a certain distance to bend around the adjacent ground via Via23 on the left side. Since the distance between the middle part of the first side and the middle part of the second side is shortened, the overlapping part between the vertically downward extension and the anti-pad 211 can be reduced, thereby improving the impedance continuity of the trace and reducing signal reflection caused by incomplete reference planes.

[0088] In the embodiment of the present application, Z = X - 1.5W is set. Z is half of the distance between the first straight line and the second straight line; X is the center distance between the first signal via Via21 or the second signal via Via22 and the adjacent ground via Via23 in the first direction; W is the line width of the first single-ended trace and the second single-ended trace, and the line widths of the two single-ended traces are the same. Figure 6 In the shown manner, X is the center distance between the second signal via Via22 and the adjacent ground via Via23 in the first direction.

[0089] Considering the integrity problem of the reference plane corresponding to the single-ended trace, the single-ended trace is in the middle of the two adjacent vias on the left and right (such as Figure 6 in the middle of the adjacent ground via Via23 and the second signal via Via22 on the left and right for the second single-ended trace), and the reference plane edges above and below the single-ended trace must ensure a line width of one time. Therefore, the length of the left and right sides of the anti-pad 211 from the center of the via is Z = X - 1.5 * W. Since there is no problem with the reference plane of the trace for the upper and lower arc edges of the anti-pad 211, the length of the upper and lower arc edges from the center of the hole is Y / 2. Finally, the designed structure of the anti-pad is as Figure 6 shown, which is an oval with an inward depression in the waist. The single-ended trace needs to come out from the left side or the right side inside the anti-pad 211 to ensure the integrity of the trace reference plane as much as possible.

[0090] In the embodiment of the present application, the circuit board adopts single-ended traces, and the two single-ended traces can be freely arranged on the circuit board. In order to reduce the overlapping part between the single-ended trace and the hollowed-out area serving as the anti-pad 211 and ensure the integrity of the trace reference plane as much as possible, it is set that the vertical projections of the parts of the first single-ended trace L21 and the second single-ended trace L22 led out from the side of the anti-pad 211 on the second surface S2 do not overlap with the vertical projection of the hollowed-out area on the second surface S2, thereby avoiding the overlap between the trace and the hollowed-out area as shown in the dashed rectangular area in Figure 1

[0091] ​As can be seen from the above description, the embodiments of the present application provide a circuit board for testing the signal integrity of a chip high-speed interface. By optimizing the wire-out method and pad structure in the circuit board, the reflection and loss of signals during transmission can be reduced during the chip high-speed interface test, improving the accuracy and reliability of the test.

[0092] Specifically, by optimizing the wire-out method in the circuit board, the influence of the circuit board as a test device on the measured signal can be minimized when testing the performance of the chip high-speed interface. By improving the conventional differential wire-out method and via fan-out method, the high-speed performance during signal transmission can be enhanced, and the problem of impedance mismatch can be reduced. In addition, according to the current wire-out method, the shape of the anti-pad 211 is optimized, which not only ensures the improvement of the via impedance but also solves the problem of incomplete reference plane during wire-out, further reducing the influence of various reflections and ensuring the integrity of high-speed signal transmission.

[0093] In this specification, the various embodiments are described in a progressive, or parallel, or a combination of progressive and parallel manners. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0094] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same drawing reference numerals throughout the embodiments of the specification identify the same structures. Additionally, for the sake of understanding and ease of description, some layers, films, panels, regions, etc. may be exaggerated in thickness in the drawings. At the same time, it can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or there may be intermediate elements. Further, "on" means positioning the element on or below another element, but essentially does not mean positioning on the upper side of another element according to the direction of gravity.

[0095] The orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be intermediate components present.

[0096] It should also be noted that, in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising the above elements.

[0097] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A circuit board for chip testing, characterized in that, The chip includes at least a first peripheral pin and a second peripheral pin. The circuit board has opposite first and second surfaces, and the circuit board includes: A first pad and a second pad located on the first surface. The first pad is used for electrically connecting to the first peripheral pin, and the second pad is used for electrically connecting to the second peripheral pin; A first single-ended trace and a second single-ended trace on the same layer. The first single-ended trace is electrically connected to the first pad; the second single-ended trace is electrically connected to the second pad; there is a single-ended trace layer in the circuit board between the first surface and the second surface, and the single-ended trace layer includes the first single-ended trace and the second single-ended trace; Alternately stacked ground metal layers and wiring layers; a wiring layer located between two adjacent ground metal layers serves as the single-ended trace layer; Wherein, the circuit board has a first signal hole and a second signal hole; the first signal hole is used for connecting the first pad and the first single-ended trace; the second signal hole is used for connecting the second pad and the second single-ended trace; The ground metal layer has an anti-pad, and the anti-pad is a hollowed-out area penetrating the ground metal layer; wherein, the vertical projection of the first signal hole on the second surface and the vertical projection of the second signal hole on the second surface are both located within the vertical projection of the hollowed-out area on the second surface; The vertical projections on the second surface of the portions of the first single-ended trace and the second single-ended trace led out from the side of the anti-pad do not overlap with the vertical projection of the hollowed-out area on the second surface; The impedances of the first single-ended trace and the second single-ended trace meet the same conditions, so that the first single-ended trace and the second single-ended trace can transmit a set of differential signals.

2. The circuit board according to claim 1, characterized in that, The first single-ended trace and the second single-ended trace have the same line width, and the distance between the first single-ended trace and the second single-ended trace is at least greater than 3 times the line width.

3. The circuit board according to claim 1, characterized in that, The first pad is soldered to the first peripheral pin, and the second pad is soldered to the second peripheral pin; The vertical projection of the first signal hole on the second surface is located within the vertical projection of the first pad on the second surface; The vertical projection of the second signal hole on the second surface is located within the vertical projection of the second pad on the second surface.

4. The circuit board according to claim 1, wherein, In a first direction, the hollowed-out area has opposite first and second sides; the first direction is perpendicular to the line connecting the centers of the first signal hole and the second signal hole, and parallel to the first surface and the second surface; Both the first single-ended trace and the second single-ended trace cross and lead out of the hollowed-out area from the first side or the second side; Wherein, the distance between the first side and the second side in the first direction is less than Y; Y is the distance between the centers of the first signal hole and the second signal hole.

5. The circuit board according to claim 4, wherein In the second direction, both the first side and the second side have opposite first and second ends; the second direction is parallel to the line connecting the centers of the first signal hole and the second signal hole, and is parallel to the first surface and the second surface. The first end of the first side is connected to the first end of the second side by a first arc, and the second end of the second side is connected to the second end of the second side by a second arc; the radii of both the first arc and the second arc are Y / 2; the center of the first arc is the center of the first signal hole; the center of the second arc is the center of the second signal hole.

6. The circuit board according to claim 4, characterized in that, The first side has a first straight side and a second straight side; the first straight side and the second straight side are located on a first straight line, and the two are connected by a first curved side. The second side has a third straight side and a fourth straight side; the third straight side and the fourth straight side are located on a second straight line, and the two are connected by a second curved side. In the second direction, both the first curved side and the second curved side are located between the first signal hole and the second signal hole. Wherein, the first straight line and the second straight line are parallel, and both are parallel to the second direction; the first curved side and the second curved side protrude towards the line connecting the center holes of the first signal hole and the second signal hole. And / or, Z = X - 1.5W, where Z is half of the distance between the first straight line and the second straight line; X is the center distance between the first signal hole or the second signal hole and a grounding hole adjacent in the first direction; W is the line width of the first single-ended trace and the second single-ended trace.

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