Lithographic process method and extreme ultraviolet lithographic process method

Abstract

A photolithography process includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer in a field; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer in the field; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer in the field. The second pattern and the third pattern are identical to the first pattern; and the first exposure process, the second exposure process, and the third exposure process collectively form a latent image of the first pattern on the resist layer in the field.

Description

Technical Field

[0001] This invention relates to a photolithography process method for reducing the impact of photomask defects. Background Technology

[0002] The semiconductor device industry has experienced rapid growth. Technological advancements in integrated circuit materials and design have resulted in generations of integrated circuits, each with smaller and more complex circuits than the previous one. In the course of integrated circuit development, functional density (defined as the number of interconnect elements per chip area) has generally increased as geometric dimensions (i.e., the smallest building blocks (or lines) that can be formed using a process) have decreased. Size reduction typically brings benefits such as increased manufacturing efficiency and reduced costs, but it also increases the complexity of designing and manufacturing semiconductor devices. However, such reductions also increase the complexity of integrated circuit (IC) fabrication and manufacturing, requiring similar advancements in IC fabrication and manufacturing to achieve these progresses. For example, high-resolution lithography processes, such as extreme ultraviolet (EUV) lithography, are implemented to meet size constraints at the 32-nanometer technology node and below, approaching critical size tolerances. EUV lithography uses a reflective photomask (also called a reticle) to transfer the pattern of one layer of an integrated circuit device onto a wafer. A reflective photomask typically consists of a reflective multilayer coating (multilayer mirror stack) located on a substrate. Any defects on the substrate, including minute defects, can cause disturbances (or deformations) in the material layers of the reflective multilayer coating, and these deformations will affect the transfer of the pattern on the reflective photomask. Such defects are often difficult to detect, and even if detected, difficult to repair. Therefore, although existing EUV photomasks and the methods for manufacturing EUV photomasks are generally suitable for their intended uses, they are still not ideal in all aspects. Summary of the Invention

[0003] An embodiment of the present invention provides a photolithography method, comprising: forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first photomask onto a resist layer in a primary field; performing a second exposure process to image a second pattern of a second sub-region of the first photomask onto the aforementioned resist layer in a secondary field; and performing a third exposure process to image a third pattern of a first sub-region of a second photomask onto the resist layer in the secondary field. The second and third patterns are identical to the first pattern; and the first, second, and third exposure processes together form a latent image of the first pattern on the resist layer in the secondary field. Attached Figure Description

[0004] This invention can be understood in more detail by reading the following detailed description and examples, along with the corresponding drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of explanation, the dimensions of the various features can be arbitrarily increased or decreased.

[0005] Figure 1 This is a side cross-sectional view of a photomask according to some embodiments of the present invention.

[0006] Figure 2 This is a flowchart of a method for forming a patterned resist layer according to some embodiments of the present invention.

[0007] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E According to some embodiments of the present invention Figure 2 A schematic cross-sectional view of a resist layer during each stage of the method.

[0008] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E For use according to some embodiments of the present invention Figure 2 Different methods of photomask patterning are used to pattern a resist layer (e.g.) Figures 3A-3E A schematic diagram of the top of the resist layer in the image.

[0009] Figure 5 This is a flowchart of a method for a hybrid photolithography exposure process according to some embodiments of the present invention.

[0010] Figure 6A This is a top view of a photomask according to some embodiments of the present invention.

[0011] Figure 6B This is a top view of a photomask according to some embodiments of the present invention.

[0012] Figure 7 This is a flowchart of a method for forming a patterned resist layer by a hybrid photolithography exposure process according to some embodiments of the present invention.

[0013] Figure 8 According to some embodiments of the present invention, for use Figure 7 A flowchart of an operation to form a patterned resist layer using a hybrid photolithography process.

[0014] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G , Figure 9H , Figure 9I , Figure 9J , Figure 9K , Figure 9L , Figure 9M , Figure 9N , Figure 9O , Figure 9P This is a top view of a resist layer patterned by a hybrid photolithography exposure process according to some embodiments of the present invention.

[0015] Figure 10 According to some embodiments of the present invention Figure 8 The flowchart shows the first set of exposure processes used to form a patterned resist layer through a hybrid photolithography exposure process.

[0016] Figure 11-1 , Figure 11-2 , Figure 11-3 , Figure 11-4 , Figure 11-5 , Figure 11-6 , Figure 11-7 , Figure 11-8 , Figure 11-9 , Figure 11-10 , Figure 11-11 , Figure 11-12 , Figure 11-13 , Figure 11-14 , Figure 11-15 , Figure 11-16 , Figure 11-17 , Figure 11-18 , Figure 11-19 , Figure 11-20 , Figure 11-21 , Figure 11-22 , Figure 11-23 , Figure 11-24 , Figure 11-25 , Figure 11-26 , Figure 11-27 , Figure 11-28 , Figure 11-29 , Figure 11-30 , Figure 11-31 , Figure 11-32 , Figure 11-33 , Figure 11-34 as well as Figure 11-35 This is a top view of a resist layer patterned by a hybrid photolithography exposure process according to some embodiments of the present invention.

[0017] Explanation of reference numerals in the attached figures:

[0018] 100, 600, 1100 ~ Photomask

[0019] 1110, 920 ~ the apex of the secondary field

[0020] 112~Substrate surface

[0021] 114~Substrate surface

[0022] 120~Reflective Multi-Layer Coating

[0023] 1221~122N~Material Layer

[0024] 130 - Defect

[0025] 200, 500, 700 ~ Method

[0026] 210~230, 510~540, 705~720, 810~830~ Operation

[0027] 310~Substrate

[0028] 320~Resist layer

[0029] 320A - Patterned Resist Layer

[0030] 330 - First Exposure Process

[0031] 332 - Latent Image

[0032] 340 ~ Second Exposure Process

[0033] 350 ~ Third Exposure Process

[0034] 362~Open

[0035] 370~Second Session

[0036] 610 ~ Photomask frame area

[0037] 910~field Detailed Implementation

[0038] The following are many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of various elements and configurations are disclosed below to simplify the description of the invention. These are merely examples and are not intended to limit the scope. For example, a structure in which a first feature is located above a second feature in the specification may include a form in which the first feature and the second feature are in direct contact, or a form in which an additional feature is inserted between the first feature and the second feature, such that the first feature and the second feature are not in direct contact. Furthermore, reference numerals and / or letters will be repeated in various examples. The above repetitions are for simplification and clarity and are not intended to specify relationships in various embodiments and / or configurations described above. Additionally, spatially related terms such as “below,” “below,” “lower,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature illustrated in the figures and another element or feature. Spatially related terms may include different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or to other orientations), and the spatially related descriptive terms used herein should be understood accordingly.

[0039] Figure 1 This is a schematic side cross-sectional view of a photomask 100 (also referred to as a photomask or reticle) according to some embodiments of the present invention. In the depicted embodiments, the photomask 100 is a blank photomask to undergo a photomask fabrication process, which patterns the blank photomask using a design of a layer of an integrated circuit (IC) device, so that the photomask 100 can be used in the fabrication of the integrated circuit device. For clarity, Figure 1 The invention has been simplified to better understand the inventive concept of the embodiments thereof. Additional features may be added to the photomask 100, and some features described below in other embodiments of the photomask 100 may be replaced or removed.

[0040] Photomask 100 includes a substrate 110. Substrate 110 has a surface 112 and a surface 114 opposite to surface 112. In this example, substrate 110 includes a low thermal expansion material (LTEM). In one example, the LTM substrate includes titanium dioxide (TiO2) doped with fused silica (SiO2). Alternatively, depending on the design requirements of photomask 100, substrate 110 may include other materials, such as quartz or glass.

[0041] A reflective multilayer coating (RMLC) 120 (also known as a multilayer mirror (MLM)) is deposited on the substrate 110, particularly on the surface 112 of the substrate 110. The RMLC 120 comprises multiple material layers 1221, 1222, 1223, 1224..., where N is the total number of material layers in the RMLC 120. For ease of discussion, "a material layer" or "multiple material layers" will be simply referred to as "a layer" or "layer". In this example, with respect to the surface 112 of the substrate 110, layer 1221 may be referred to as the bottom layer of the RMLC 120, and layer 122... NThis can be referred to as the top layer of RMLC 120. Further, multiple layers 1221, 1222, 1223, 1224, ..., 122N form multiple layer pairs, where each layer pair includes two layers with different reflectivities (i.e., a combination of a first material and a second material, where the reflectivity of the first material differs from that of the second material). For example, one layer pair includes layers 1221 and 1222, another layer pair includes layers 1223 and 1224, and so on. The combination of materials in the layer pair is chosen to provide a large difference in reflectivity between the two layers (e.g., achieving a large reflectivity at an interface between the two layers according to the Fresnel equation), but to provide a small extinction coefficient for the layers (e.g., to minimize absorption). In one example, RMLC 120 includes a molybdenum-silicon (Mo / Si) layer pair. In another example, RMLC 120 includes a molybdenum-beryllium (Mo / Be) layer pair. The thickness of each layer in each layer pair of the RMLC 120 is adjusted according to a wavelength and an incident angle of the light (e.g., extreme ultraviolet (EUV) radiation) incident on the photomask 100, so that the photomask 100 achieves maximum constructive interference of light reflected from different interfaces of the RMLC 120. Generally, the reflectivity of the RMLC 120 increases with the number of RMLC 120 layer pairs. Therefore, in principle, if the number of layer pairs is large enough and the extinction coefficient of the layer materials is close to zero, the reflectivity of the RMLC 120 can approach 100% regardless of the reflectivity differences between the layers in the pair. However, in the EUV wavelength range, the highest achievable reflectivity is limited by the extinction coefficient of the RMLC 120 layer materials. In this example, the number of RMLC 120 layer pairs is 20–80. For example, in the depicted embodiment, in order to achieve a maximum achievable reflectivity of greater than 90% for the RMLC 120 (by the selected material) and to minimize the photomask manufacturing time and cost, the RMLC 120 includes approximately forty layer pairs, such as forty Mo / Si pairs (where N = 80; including silicon and having a thickness of approximately 3 to 5 nm (e.g., approximately 4 nm)).

[0042] The RMLC 120 includes a phase-defect region that alters the phase of light reflected from the RMLC 120. In the depicted embodiment, defect 130 (e.g., bump defect) is located on surface 112 of substrate 110. Figure 1 As shown, defect 130 causes deformation in multiple layers of RMLC 120 deposited on surface 112 of substrate 110. More specifically, deformation occurs in each layer 1221, 1222, 1223, 1224, ... 122 NTherefore, defect 130 is formed in each successively formed layer, such that the phase defect region of RMLC 120 extends from the bottom layer (layer 1221) to the top layer (layer 122). N Alternatively, the phase defect region extends through a finite number of layers 1221, 1222, 1223, 1224, ... of the RMLC 120. In another embodiment, the phase defect region extends through a finite number of layers 1221, 1222, 1223, 1224, ... N Defects in / on a certain layer cause deformation in subsequently deposited layers, and the deformation in subsequently deposited layers is related to defects in / on the layers, rather than to defects on the surface of substrate 110 (e.g., defect 130). The deformation of RMLC 120 can have different profiles, depending on the layers 1221, 1222, 1223, 1224, ..., 1225 in which RMLC 120 is formed. N The types of defects related to deformation and process conditions during the process.

[0043] The light reflected from the RMLC 120 includes all light reflected from the various interfaces of the RMLC 120. In this example, some of the reflected light is phase-shifted (i.e., has a phase error) because of layers 1221, 1222, 1223, 1224, ..., 122 in the RMLC 120. N The deformation (caused here by defect 130). The phase defect region shown (the set of deformations in the layers of RMLC 120) primarily affects the phase of the light reflected from RMLC 120, although it may only slightly affect the amplitude of this reflected light. When photomask 100 is illuminated with a small imaging wavelength (e.g., EUV wavelength), although 1221, 1222, 1223, 1224, ..., 122 NWhile the degree to which layer deformation relates to the phase defect region of the RMLC 120 may be small, it can still potentially cause a large phase error in that region. For example, at an imaging wavelength of 13.5 nm, a defect with a height or depth of approximately 3.4 nm (about a quarter of the imaging wavelength) can cause a phase error of up to 180°. This phase shift (error) caused by the phase defect region of the RMLC 120 negatively impacts the photolithography process using the photomask 100. In fact, a phase difference relatively small than 180° (e.g., 30°) can negatively affect the photolithography process window or the fidelity of the pattern generated using the photomask 100. Therefore, it is desirable for the substrate 110 (especially surface 112 of the substrate 110) and the RMLC 120 to be defect-free (e.g., protrusion defects, pit defects, and other types of defects). However, achieving a defect-free substrate and a defect-free RMLC using conventional techniques is difficult. The following discusses how to reduce the impact of these defects, particularly the impact of defect regions. Furthermore, embodiments of the present invention provide a method for implementing EUV lithography, which effectively eliminates the influence of defects and further reduces or minimizes manufacturing costs.

[0044] Figure 2 This is a flowchart of a method for forming a patterned resist layer according to some embodiments of the present invention. Method 200 begins at block 210, where a resist layer is formed on a substrate. At block 220, an optimal exposure dose (E) is determined. OP In a given photolithography process, a given resist layer has a predetermined threshold exposure dose (E). THA predetermined threshold exposure dose is the minimum exposure dose, which reliably alters the exposed portion of the resist layer relative to the unexposed portion (when the pattern on the photomask is large compared to the wavelength of the radiation source used). For example, when the resist layer comprises a positive resist material, the exposed portion of the resist layer becomes soluble at the threshold exposure dose. Thus, in the development process, the exposed portion of the resist layer is removed, leaving the developed resist layer containing the pattern. In another example, the resist layer comprises a negative resist material, and at the threshold exposure dose, the exposed portion of the resist layer becomes insoluble. Thus, in the development process, the unexposed portion of the resist layer is removed, leaving the developed resist layer containing the pattern. However, various practical effects can lead to insufficient threshold doses. For example, when the pattern size on the photomask is close to or smaller than the wavelength of the radiation source used, diffraction effects that reduce the contrast of the aerial image become significant. In another example, the post-exposure baking process may exhibit effects such as acid diffusion (chemically amplified impedance) and acid annihilation (quencher effect). To correct for these effects, in some embodiments, an optimal exposure dose can be determined based on the exposure dose used for a pre-specified test pattern to achieve a predetermined target dimension on a wafer in a corresponding single exposure process.

[0045] In block 230, a pattern is formed in the resist layer by a hybrid photolithography exposure process and a development process. The hybrid photolithography exposure process includes multiple exposure processes using different photomasks and different pattern regions of the same photomask. A detailed description follows. In some embodiments, the multiple exposure process uses extreme ultraviolet (EUV) light, and the radiation from each exposure process may have approximately the same wavelength. In the multiple exposure process of block 230, each exposure process may utilize an exposure dose less than the optimal exposure dose, and the total exposure dose (E) of the multiple exposure process is... T It is approximately equal to the optimal exposure dose (in other words, E1). <E OP E2 <E OP ..., E L <E OP and E T =E1+E2+E3+…+E L ≈E OP L represents the total number of exposure processes performed.

[0046] During a multiple exposure process, the resist layer is exposed multiple times in the same area with the same pattern (e.g., the same integrated circuit (IC) pattern). However, the same IC pattern comes from different mask patterns, including multiple masks (the number of masks is M) and multiple portions of each mask (the number of portions is N). A portion of a mask is also referred to as a sub-region in the following description. Each exposure process is implemented using a different mask or a different portion of a mask. Therefore, multiple exposure processes are collectively referred to as hybrid lithography processes. A hybrid lithography process includes a total of L exposure processes, where L = M * N. A more detailed explanation follows.

[0047] Multiple exposure processes are divided into multiple exposure processes, each associated with the same photomask. In this case, each exposure process in the same group associated with a photomask uses a different portion of that photomask to expose the resist layer, where each portion of the photomask has the same pattern. Another group of exposure processes uses a different photomask to expose the resist layer in the same manner. The different photomasks and the different portions of a photomask may include defects (such as protrusions, depressions, other types of defects, or combinations thereof) and phase defect regions. However, these defects are typically randomly distributed and contribute only to one of the multiple exposure processes, for example, contributing less than E to the exposure dose. T / L. When L is large enough, such as L>10, then the dose change from a defect is too small (much smaller than the total exposure dose E). T This process does not cause any actual change to the developed photoresist pattern. Therefore, hybrid lithography reduces the impact of defects. Thus, even if the photomask has a reasonable number of defects (e.g., 1 or 2), it is still usable. Overall, this reduces manufacturing costs.

[0048] The step of forming a pattern in the resist layer may further include a developing process, wherein a developing solution is applied to the exposed resist layer. The resist layer may also undergo a baking process before and / or after exposure. Additional steps may be provided before, during, and after method 200, and some of these steps may be replaced, removed, or moved to other embodiments of method 200. The following discussion illustrates various embodiments of a resist layer, which may be adapted according to… Figure 2 The method is to pattern it.

[0049] Figures 3A-3E for Figure 2 The diagram shows different resist layers at different stages of the method. Figures 3A-3E The concepts disclosed in the embodiments of the present invention have been simplified for a better understanding. Figure 3AThe invention provides a wafer 310. Wafer 310 is a substrate, a photomask (also referred to as a photomask or intermediate photomask), or any base material on which multiple material layers can be provided to form various feature components of an integrated circuit device. In the described embodiment, wafer 310 is a semiconductor substrate comprising silicon (i.e., a silicon wafer). Alternatively, wafer 310 includes another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In another alternative, wafer 310 is a semiconductor on an insulator substrate (SOI). Wafer 310 may also be referred to as a material layer, or wafer 310 may include a material layer to form a resist layer thereon. In one example, the material layer is a metal layer, a semiconductor layer, or a dielectric layer. In another example, the material layer is a hard mask layer, such as a silicon oxide layer or a silicon nitride layer.

[0050] A resist layer 320 is applied to wafer 310 using a spin coating technique. The resist layer 320 is also referred to as a photoresist layer, photosensitive layer, imaging layer, patterning layer, or radiation-sensitive layer. A rinsing process (e.g., deionized water rinsing) may be performed on wafer 310 before applying the resist layer 320. The resist layer 320 may be subjected to a baking process, such as a soft bake (also known as a post-application bake). In the described embodiment, the resist layer 320 comprises a positive resist material. Alternatively, the resist layer 320 may comprise a negative resist material. The resist layer 320 has a suitable thickness, such as approximately 10–1000 nanometers.

[0051] exist Figures 3B-3E In this process, the resist layer 320 is patterned to form a patterned resist layer 320A. The step of patterning the resist layer 320 includes performing a hybrid photolithography exposure process, which includes... Figures 3B-3D The diagram illustrates one or more exposure processes. Each exposure process uses an exposure dose less than the optimal exposure dose E for that single exposure process. OP In the described embodiment, the first exposure process 330 ( Figure 3B ), second exposure process 340 ( Figure 3C) and the third exposure process 350 ( Figure 3D Each of the three exposure processes involves selectively irradiating the resist layer 320 with radiation at different exposure doses (E1, E2, and E3) using a different photomask pattern, thereby forming a latent image 332 in the resist layer 320. The photomask pattern referred to herein refers to the same IC pattern formed in different portions of the photomask or on different photomasks. In this example, only three exposure processes are described illustratively for explanation. The total number of exposures is not limited to L. The first exposure dose (E1), second exposure dose (E2), and third exposure dose (E3) are all less than the optimal exposure dose (E3). OP Furthermore, in the current example, the total exposure dose (E) of the first exposure dose (E1), the second exposure dose (E2), and the third exposure dose (E3) is... T Approximately equal to the optimal exposure dose (E) OP (That is, ET = E1 + E2 + E3 ≥ E) OP Thus, the latent image 332 becomes developable after the third exposure process 350. In the described embodiment, the first exposure process 330, the second exposure process 340, and the third exposure process 350 irradiate the resist layer 320 with radiation having a wavelength less than about 100 nanometers (e.g., extreme ultraviolet (EUV) range, X-ray range, deep ultraviolet range, vacuum ultraviolet range, or a combination thereof). In one example, the radiation is EUV radiation with a wavelength equal to 13.5 nanometers. Alternatively, the wavelength range of the radiation is greater than 100 nanometers. For example, a radiation source may be a light source (e.g., a krypton fluoride (KrF) excimer laser with a wavelength of 248 nanometers, an argon fluoride (ArF) excimer laser with a wavelength of 193 nanometers, a fluoride (F2) excimer laser with a wavelength of 157 nanometers, or other light sources). It is worth noting that in alternative embodiments, only two or more exposure processes may form a developable latent image pattern on the resist layer 320.

[0052] The photomask patterns used in the first exposure process 330, the second exposure process 340, and the third exposure process 350 include a pattern (e.g., an integrated circuit pattern according to a design layout) that is transferred to the resist layer during each exposure process 330, 340, and 350. In one example, different photomask patterns having the same integrated circuit pattern are used in the first exposure process 330, the second exposure process 340, and the third exposure process 350.

[0053] The following example further describes a set of exposure processes associated with a photomask. Different portions of the same photomask having the same integrated circuit pattern are used in the first exposure process 330, the second exposure process 340, and the third exposure process 350, respectively. For example, see [link to example]. Figures 4A-4E The first portion of the photomask used in the first exposure process 330 has an integrated circuit pattern, the second portion of the photomask used in the second exposure process 340 (different from the first portion) has the same integrated circuit pattern, and the third portion of the photomask used in the third exposure process 350 (different from both the first and second portions) has the same integrated circuit pattern. These portions of the photomask are referred to as sub-regions of the photomask. The IC pattern defined on the sub-regions of the photomask is identical. Figure 4A In the described embodiment, a photomask includes a photomask imaging region and a photomask frame region. The photomask imaging region includes a first portion (or a first photomask sub-region) containing an integrated circuit pattern 1, a second portion (or a second photomask sub-region) containing an integrated circuit pattern 2, and a third portion (or a third photomask region) containing an integrated circuit pattern 3. In the described embodiment, integrated circuit patterns 1, 2, and 3 are identical integrated circuit patterns. The photomask is used to transfer integrated circuit patterns 1, 2, and 3 (which are all identical to each other) to a wafer 310, particularly to a resist layer 320 on the wafer 310 multiple times. Figures 4A-4E (Not shown in the image). For example, this photomask is used in a multiple exposure process to transfer an integrated circuit pattern to various subfields of wafer 310. The sub-regions of the photomask have the same pattern. Each field represents an area of ​​wafer 310 that will be exposed for a given time, and each field corresponds to a photomask image area. Each subfield represents an area of ​​wafer 310 exposed for a given time; in the described embodiment, each subfield corresponds to a photomask sub-region. Figure 4A In this context, a primary field is denoted as 370. A primary field can define an integrated circuit chip, which will eventually be diced from wafer 310 and packaged into a circuit chip. Alternatively, a secondary field can define multiple integrated circuit chips, which will eventually be packaged into multiple circuit chips. In existing methods, photolithography is a field-based process, while the method of this embodiment is a secondary field-based process. This will be further explained below. In one example, an exposure tool (e.g., a stepper or scanner) processes one or more secondary fields, then processes the next one or more secondary fields, and so on, so that each secondary field 370 is exposed to integrated circuit patterns 1, 2, and 3 that respectively define the first, second, and third sub-regions of the photomask.

[0054] For ease of discussion, this example shows all the exposure procedures for a single integrated circuit device region 370 (the integrated circuit device regions 370 on the upper and left sides of wafer 310). However, it must be understood that during wafer fabrication, multiple integrated circuit device regions 370 are processed and fully exposed. Reference Figure 3B as well as Figure 4B In the first exposure process 330, a first sub-region of the photomask containing the integrated circuit pattern 1 is aligned with one of the secondary fields 370 (here, the upper left secondary field 370), and radiation of a first exposure dose (E1) is projected onto the photomask. A portion of the radiation is transferred to the resist layer 320, thereby transferring the integrated circuit pattern 1 of the first sub-region of the photomask to the resist layer 320 to form a latent image pattern 332, wherein the latent image pattern 332 includes a latent image portion 332A. In the described embodiment, the resist layer 320 comprises a positive resist material, and the latent image portion 332A becomes partially soluble. Next, see... Figure 3C by Figure 4C In the second exposure process 340, the second portion of the photomask containing the integrated circuit pattern 2 is aligned with the same primary field 370 (here, the upper left secondary field 370), and radiation of the second exposure dose (E2) is projected onto the photomask. During the second exposure process, the first sub-region of the photomask is also aligned with another sub-field 370 of the wafer 310. A portion of the radiation is transferred to the resist layer 320, thereby transferring the integrated circuit patterns of the first and second regions of the photomask to the resist layer 320, respectively. In this example, the solubility of the latent image pattern 332 (especially the latent image portion 332A) is increased in the upper left secondary field 370. The latent image pattern 332 therefore includes a latent image portion 332B, which is more easily dissolved than the latent image portion 332A. The solubility of the latent image portion is increased due to the additional exposure dose provided in the second exposure process 340. To further illustrate this example, the other secondary fields 370 exposed to the first portion of the photomask include the latent image portion 332A, as it only accepts the second exposure process 340. See Figure 3D as well as Figure 4DIn the third exposure process 350, the third sub-region of the photomask containing the integrated circuit pattern 3 is aligned with the same primary field 370 (here, the upper left secondary field 370), and radiation of the third exposure dose (E3) is exposed onto the photomask. A portion of the radiation is transferred to the resist layer 320, thereby transferring the integrated circuit patterns of the first, second, and third sub-regions of the photomask to the resist layer 320, respectively. In this example, the solubility of the latent image pattern 332 (especially the latent image portion 332B) is increased in the upper left secondary field 370. The latent image pattern 332 therefore includes a latent image portion 332C, which is more easily dissolved than the latent image portion 332B. This process is repeated on other photomasks before all M photomasks are processed. Due to the first exposure dose (E1), second exposure dose (E2), third exposure dose (E3), ..., and Lth exposure dose... th The exposure dose is approximately equal to the optimal exposure dose (EOP), and the latent image portion is soluble, thus allowing the latent image 332 to be developed in the upper left integrated circuit device area 370. According to various embodiments, the exposure dose (EOP)... i These can be the same as or different from each other. In one example, the exposure dose (E) i For each exposure dose E that is the same as the others, i =E op / L=E op / (M*N)=E op / (M*N x *N y In the aforementioned formula, N represents the total number of sub-regions of the photomask, and the secondary field configuration on the photomask is N. x ×N y Array. In Figure 4A In the photomask example, the photomask includes three sub-regions configured in a 1*3 array. Therefore, in this example, N, N x and N y They are 3, 1, and 3 respectively.

[0055] exist Figure 4EIn the process of subsequent exposure, the upper left subfield 370 is fully exposed due to the optimal exposure dose. The aforementioned multiple exposure process perfectly matches the actions taken by the scanner when stepping and scanning to expose the entire wafer. The scanner stage only needs to move a portion of the field size (one or more subfields of the wafer or one or more sub-regions for the mask) in the scanning direction, and the entire field size along the scanning direction during scanning. Therefore, the impact of the multiple exposure process on wafer productivity can be minimized. In addition to reducing the impact of randomly distributed mask defects (including phase defects, pattern defects, and particles), this method can also effectively reduce the impact of other random errors, such as line edge roughness and registration error of the mask pattern.

[0056] A multiple exposure process is used to form a latent image pattern 332 in the resist layer 320, wherein each exposure process exposes the resist layer 320 to the same pattern using an exposure dose less than the optimal exposure dose, in order to reduce the impact of defects or defective regions in the photomask used in the multiple exposure process. For example, in the described embodiment, the photomask used in the first exposure process 330, the second exposure process 340, and the third exposure process 350 has defects or defective regions, such as... Figure 1 The photomask 100 is shown. When different photomask patterns are used (including different photomasks or different sub-regions of photomasks), one or more different photomask patterns include a phase defect region. Because the exposure dose projected onto a photomask pattern (the exposure dose defined in a sub-region of a photomask) is less than the optimal exposure dose, it only accounts for a small fraction of the total exposure dose (e.g., in one example, E...). OP / (M*N x *N y The effect of the phase defect on a corresponding sub-region of a photomask will be significantly reduced. Since these defects are randomly distributed on different photomasks or in different sub-regions of the photomask, no defect will receive the full exposure dose. More specifically, the aerial image intensity affected by each individual defect will be reduced, thereby reducing the transferability of such defects. Different embodiments may have different advantages, and no particular advantage is required for any embodiment. In one example, the exposure dose for each exposure process is approximately equal to the optimal exposure dose (E). OP Divide the exposure dose by L, where L is the total number of exposure processes. Therefore, in this example, the first exposure dose (E1), the second exposure dose (E2), ..., the Lth exposure dose (E...) l ) equals the optimal exposure dose (E) OP 1 / L of the first exposure dose (E1), the second exposure dose (E2), ... and the Lth exposure dose (E...). lApproximately equal to the optimal exposure dose (E) OP Different fractions of the EUV exposure process can be used to adjust the exposure dose based on the transferability of the defect. For example, if the defect on the photomask is transferable, the exposure dose of the photomask can be reduced to make it non-transferable.

[0057] Subsequently, the resist layer 320 may be subjected to a post-exposure bake (PEB) step. See also Figure 3EA development process is performed on resist layer 320 to form a patterned resist layer 320A. In the development process, a developing solution is applied to resist layer 320. In one example, the developing solution is an alkaline solution, such as tetramethylammonium hydroxide (TMAH). Any concentration level of TMAH developing solution is used depending on the characteristics of resist layer 320, for example, approximately 2.38% TMAH. Depending on the resist material, the developing solution removes either the exposed or unexposed portions of the resist layer. For example, in this example, resist layer 320 includes a positive resist material, therefore the exposed portion (latent pattern 322) of resist layer 320 is removed during the development process, leaving the unexposed portion of resist layer 320 on wafer 310. Alternatively, the resist layer 320 may include a negative resist material. During the development process, the unexposed portions of the resist layer 320 are removed, leaving the exposed portions 320 on the wafer 310. The rinsing process includes, for example, rinsing with deionized (DI) water. The rinsing process removes residual particles. The patterned resist layer 320A includes openings 362 that expose portions of the underlying wafer 310. Subsequent processes may include etching the portions of the wafer 310 exposed in the openings of the patterned resist layer 320A. Alternatively, metal deposition, ion implantation, or other processes may be performed on the wafer 310. The patterned resist layer 320A can be removed (or stripped) using any suitable process. For example, the patterned resist layer 320A can be removed using a fluid (or stripping solution). In some cases, the exposed portions of wafer 310 are subjected to ion bombardment or plasma treatment processes. This fluid strips the ion-bombarded patterned resist layer 320A and / or the plasma-treated patterned resist layer 320A. After the patterned resist layer 320A is removed, subsequent processes can continue to complete the fabrication of the integrated circuit device. For example, additional patterning processes, etching processes, deposition processes, and other processes can be performed to form other features of the integrated circuit device.

[0058] Figure 5This is a flowchart of a hybrid photolithography process 500 according to some embodiments of the present invention. The method begins at block 510, receiving an IC design layout or simply an IC pattern. The IC pattern may be part of an integrated circuit, such as a pattern formed on a material layer of a semiconductor chip. The IC pattern is designed by an integrated circuit designer or further modified by a photomask manufacturer according to semiconductor manufacturing technology. For example, the IC pattern is further combined with various virtual features of the IC pattern to improve its manufacturing, such as reducing load effects (etching or polishing load effects) and smoothing pattern density. In another example, the IC pattern is modified according to optical proximity correction (OPC) to enhance the resolution of the photolithography process.

[0059] The method proceeds to operation 520, which determines the available sub-regions (also known as candidate sub-regions) based on the IC pattern. Operation 520 is for reference only. Figure 4A Describe it. For example... Figure 4A As shown, a photomask includes a photomask image region, which further includes multiple photomask image sub-regions. These photomask image sub-regions are also simply referred to as sub-regions. The patterns formed in the sub-regions of the photomask are identical. Furthermore, the patterns formed in the sub-regions of the M photomask are all identical. In one example, any sub-region includes an integrated circuit pattern of a chip. As previously mentioned, a sub-region may include patterns of multiple chips, such as a chip array. The number of sub-regions depends on the size of the wafer, as each sub-region includes at least one chip. Figure 4A In the photomask example, the photomask includes three sub-regions, each containing an IC pattern, which may correspond to one or more chips. The number of sub-regions (N) is determined based on the IC pattern in operation 520. The number N can be 1*3, 2*2, 2*3, or other suitable integers.

[0060] Figure 6A Displaying a photomask 600 with four sub-regions. The photomask 600 includes a photomask frame region 610 and four photomask image regions labeled 1, 2, 3, and 4 respectively. Each sub-region includes an IC pattern formed therein. The four sub-regions are arranged in a 2x2 array. Or, as... Figure 6B As shown, four sub-regions are arranged in a 1x4 array. Generally, sub-regions are arranged in an array, and the array has a direction (...). Figure 6A N arranged in the X direction x Sub-regions and along another direction ( Figure 6A N arranged in the Y direction y The number of sub-regions N on the photomask is N. x *N y , or N = N x *N y Therefore, operation 520 also determines the available N.x and N y In this example, the available N x and N y The values ​​are 2 and 2 respectively. Each sub-region can include an integrated circuit pattern corresponding to a single chip or multiple chips. For example, each sub-region can represent a pattern of 2*2 chips. Therefore, the following operations can freely choose 2*2, 2*4, 4*2, or 4*4 sub-regions. In other words, the available N... x *N y This includes 2*2, 2*4, 4*2, and 4*4.

[0061] When a photomask is imaged onto a wafer, the corresponding region on the wafer becomes a field. Similarly, sub-regions correspond to sub-regions of the field. These sub-regions on the wafer are called secondary fields.

[0062] Method 500 proceeds to operation 530, where sub-region N is determined based on the available sub-regions and the manufacturing cost function. x N y And the number of photomasks M. Sub-region N x and N y Only the available sub-regions determined in operation 520 can be selected. For example, the available sub-region N x *N y Including 2x2, 2x4, 4x2, and 4x4. Subregion N x and N y Only available regions can be selected. In operation 530, sub-region N is also determined based on the manufacturing cost function. x and N yThe manufacturing cost function is a function that evaluates the overall manufacturing cost, including the photomask manufacturing cost and the wafer manufacturing cost associated with the hybrid lithography process. The photomask manufacturing cost also includes the cost of a blank photomask (the cost of the photomask substrate without a pattern) C1, the photomask pattern cost C2, and the photomask repair cost C3. In some examples, the photomask cost also includes costs related to photomask complexity, for example, expressed as a photomask complexity parameter. The photomask pattern cost is higher when the photomask pattern is more complex. In this example, multiple photomasks (number M) are used. The cost of a blank photomask is equal to the cost of a single blank photomask multiplied by M. However, since defective photomasks can be used for this purpose, and defective photomasks are cheaper, the cost of a blank photomask (N times the cost of a defective blank photomask) is even lower than the cost of a defect-free blank photomask. The photomask pattern cost includes the cost of patterning the blank photomask and other related expenses. This cost will be significantly reduced as multiple electron beam writing technologies mature. The photomask repair cost includes the cost of repairing defective photomasks. Since the hybrid lithography process can tolerate most defects, this cost can be reduced or eliminated. The wafer manufacturing cost C4 includes costs associated with the photolithography process. Hybrid photolithography is more expensive because it involves multiple exposure processes, each with associated costs for scanning and stepping times. Each photolithography process includes the movement to a field and the time required to scan that field. As mentioned earlier, the scanning time of a hybrid photolithography process is essentially similar to that of a single conventional photolithography process, since each exposure process in a hybrid photolithography process uses a segment of the scanning time of a single conventional photolithography process (approximately 1 / L). However, the stepping time of a hybrid photolithography process is greater than that of a single conventional photolithography process. The manufacturing cost function Fc can be defined as Fc = f(C1, C2, C3, C4). This function can be linear, for example, Fc = a1*C1 + a2*C2 + a3*C3 + a4*C4. The coefficients a1, a2, a3, and a4 are determined based on the cost model described above. In the available sub-region N... x and N y In the middle, sub-region N x and N y It is determined by the available sub-regions, where the manufacturing cost is minimized, or the manufacturing cost function is minimized. In different examples, M, N x and N y It is determined to be [3,2,2], [3,4,1] or [3,1,4].

[0063] Method 500 proceeds to operation 540, where multiple photomasks are fabricated, the number M of which is determined in operation 530. These photomasks have identical patterns. Specifically, an IC pattern is formed on each photomask. x and N yOn the sub-region. The photomask fabrication process can use multiple electron beams for writing.

[0064] Figure 7 This is a flowchart of a hybrid photolithography exposure process according to some embodiments of the present invention. In one embodiment, method 700 follows and continues from method 500. For example, method 700 may begin at block 705 by receiving M photomasks as defined in operation 540.

[0065] Method 700 proceeds to operation 210 to form a resist layer on a substrate (e.g., a semiconductor wafer).

[0066] Method 700 enters operation 220, such as Figure 2 As mentioned above, the optimal exposure dose (E) is determined. OP ).

[0067] Method 700 proceeds to operation 710, whereby a hybrid photolithography exposure process is performed to form a pattern in a resist layer, wherein the hybrid photolithography exposure process includes a multiple exposure process using M masks, wherein the exposure dose used in each exposure process is less than the optimal exposure dose (E). OP Hybrid lithography involves many exposure processes, where L equals M*N. x *N y Parameters M and N x and N y This is determined in operation 530 of method 500. Furthermore, M identical photomasks are manufactured in operation 540 of method 500.

[0068] In hybrid lithography, the multiple exposure process is divided into M groups and matched with M masks. Each group uses a matched mask for the multiple exposure process (e.g., N). x *N y Each group is similar to the others.

[0069] Continue reading Figure 7 After completing the hybrid photolithography exposure process in operation 710, method 700 proceeds to operation 720 to form a patterned resist layer. Operation 720 includes a development process using a suitable developer. Operation 720 may also include other process steps. For example, operation 720 may include post-exposure baking before the development step, post-development cleaning, and post-development hard baking.

[0070] See Figure 8Operation 710 includes M sets of exposure processes, such as the first set of exposure processes in block 750 using a first photomask to expose a resist layer on a substrate; the second set of exposure processes in block 760 using a second photomask to expose a resist layer on a substrate; ... and the Mth set of exposure processes in block 770 using an Mth photomask to expose a resist layer on a substrate. Since each set of exposure processes is identical to the others except for using its own photomask, only one set of exposure processes (e.g., the first set of exposure processes in block 750) will be described in detail here. Each set of exposure processes is performed using the same photomask, i.e., one of the M photomasks.

[0071] As an example, such as Figure 6A As shown, assume N x and N y The values ​​are 2 and 2 respectively, which means that the photomask 600 includes 2*2 sub-regions and a set of exposure processes including 2*2 exposure processes. Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G , Figure 9H , Figure 9I , Figure 9J , Figure 9K , Figure 9L , Figure 9M , Figure 9N , Figure 9O , Figure 9P This displays a set of exposure processes. In Figure 9A In this configuration, substrate 310 includes only six exemplary fields (or 3*2 fields) 910. Each field includes N... x *N y Each subfield corresponds to the N of the photomask 310. x *N y Sub-regions. In this example, each field includes 2*2 sub-fields, which correspond to 2*2 sub-regions of the photomask 310. The sub-fields on the wafer are labeled (i,j), which represent the i-th sub-field along the X direction and the j-th sub-field along the Y direction, with the sub-fields starting from the lower left as (1,1).

[0072] The first exposure process in block 750 is in Figures 9A to 9P The text is a joint description and explanation. From... Figure 9A Initially, the photomask 600 is moved to a position such that the first field (1,1) is covered by the first sub-region of the photomask 310. Specifically, the photomask 600 is moved a first distance D along the X direction from the vertex 920 of the first field (1,1). x (Corresponding to the dimension of the secondary field) and the second distance D along the Y direction. y(Corresponding to the dimension of the secondary field). It is worth noting that... Figure 9A To illustrate in a more understandable way, generally, the sub-regions and subfields have different dimensions. However, the images of the IC patterns within the sub-regions are aligned and mapped to the subfields, which have the same dimensions. It's worth noting that stepping is the relative movement between the photomask and wafer 310. Generally, the wafer moves relative to the photomask. For simplicity and better understanding, it is described as the photomask moving in steps relative to the wafer. Then, at a dose less than the optimal exposure dose E... op The exposure dose is scanned on the photomask 600 to form an IC pattern in the first field (1,1). Based on the position of the photomask, a sub-region of the photomask 600 is exposed only in the first field.

[0073] See Figure 9B The photomask 600 moves along the Y direction D y The photomask 600 is then scanned to form IC patterns on the two subfields (1,1) and (1,2). In other words, only the two subfields (1,1) and (1,2) are exposed.

[0074] See Figure 9C The photomask 600 moves along the Y direction to another D y To cover another subfield. Then, the photomask 600 is scanned to form IC patterns on the two subfields (1,2) and (1,3).

[0075] See Figure 9D The photomask 600 moves along the Y direction to another D y Next, the photomask 600 is scanned to form IC patterns on the two subfields (1,3) and (1,4). In this example, the two subfields will still be exposed.

[0076] See Figure 9E The photomask 600 moves along the Y direction D y Next, the photomask 600 is scanned to form an IC pattern on a subfield (1,4).

[0077] See Figure 9F The photomask 600 moves along the X direction by D x Next, the photomask 600 is scanned to form IC patterns on the two subfields (1,4) and (2,4).

[0078] See Figure 9G The photomask 600 moves along the -Y direction by D y Next, the photomask 600 is scanned to form an IC pattern in a complete field including four subfields (1, 4), (1, 3), (2, 3), and (2, 4).

[0079] See Figure 9HThe photomask 600 moves along the -Y direction by D y Next, the photomask 600 is scanned to form IC patterns on four subfields (1,2), (1,3), (2,2), and (2,3).

[0080] See Figure 9I The photomask 600 moves along the -Y direction by D y Next, the photomask 600 is scanned to form IC patterns on four subfields (1,1), (1,2), (2,1), and (2,2).

[0081] See Figure 9J The photomask 600 moves along the -Y direction by D y Next, the photomask 600 is scanned to form IC patterns only on the two subfields (1,1) and (2,1).

[0082] See Figure 9K The photomask 600 moves along the X direction by D x Next, the photomask 600 is scanned to form IC patterns only on the two subfields (2,1) and (3,1).

[0083] Similarly, such as Figures 9K to 9P As shown, this step-scanning process continues until the secondary field of the substrate 310 is exhausted. Specifically, this step-scanning process continues until each secondary field of the substrate 310 is respectively controlled by the N-type photomask 600. x *N y IC pattern exposure in sub-region N x *N y This process continues until the next exposure. In this example, each subfield is exposed 2*2 times in four sub-regions with the same IC pattern. Therefore, the first set of exposure processes is complete. It is worth noting that D x and D y The step size differs from that of traditional exposure processes. In typical exposure processes, the step size corresponds to the dimension of the entire field, i.e., N. x *D x and N y *D y (or 2D in this example) x and 2D y Since a subset of the scans described above does not expose a full field size (some expose only one subfield, while others expose only two subfields), more steps and scans are needed to achieve complete coverage (each subfield needs to be exposed over N fields). x *N y In this case, the first set of exposure processes requires (3*N). x +1)*(2*N y+1) step scan operations (cycles). This will be understood from the following: In a conventional single lithography process, if the substrate 310 includes 3*2 fields, then the step scan operations include 3*2. In a hybrid lithography exposure process, each subfield is exposed N times. x *N y Times. All step scan actions should be (3*N) x )*(2*N y However, because some steps and scanning operations do not cover the entire field (or, in this example, four subfields), additional actions are required. Therefore, the first set of exposure processes ultimately has (3*N) x +1)*(2*N y +1) step scan operations. This should take into account the wafer manufacturing cost in the manufacturing cost function.

[0084] Please see Figure 8 The hybrid photolithography exposure process continues to other exposure processes (similar to the first group mentioned above), such as the second exposure process in block 760 using a first photomask to apply a photoresist layer to the substrate; ... and the m-th exposure process in block 770 using the M-th photomask to apply a photoresist layer to the substrate.

[0085] exist Figures 9A to 9P The descriptions collectively describe the first set of exposure processes. However, as long as each subfield is composed of an N of a 600-degree photomask... x *N y IC pattern exposed in individual areas N x *N y This allows for the design of different step-scan sequence sequences. N within the group x *N y The exposure processes can be implemented in different sequences. The first group of exposure processes includes N. x *N y There are two exposure processes (2x2 in this example). Each of the first set of exposure processes includes a stepping and a scanning action, but with three differences. First, the starting stepping position is different, thus resulting in different displacements in different exposure processes. Second, the step size is the dimension of the entire field (i.e., a movement of N along the X direction). x *D x Move N along the Y direction y *D y Therefore, there is overlap between adjacent scan actions in the same exposure process. Third, each exposure process may require a different number of step scan cycles.

[0086] Let's take a further example using a photomask 600. The photomask 600 comprises four sub-regions. Therefore, there are four exposure processes in each group associated with a photomask. The first exposure process in the first group includes a first stepping action, which has the following characteristics: Figure 9A The starting position is shown. In this case, the first scan action exposes the field (1,1) only once, followed by... Figure 9C As shown, it moves N along the Y direction. y *D y The second scan only exposes two subfields (1,2) and (1,3). Then, as... Figure 9E As shown, it moves N along the Y direction. y *D y The third scan only exposes the field (1,4) once, then moves N along the X direction. x *D x Subsequent scanning only exposed two subfields, (2,4) and (3,4). For example... Figure 9L As shown, this continues until the last step reaches the subfield (6,1), and then the subfield is scanned. The first exposure process requires a total of 12 step scan cycles.

[0087] The first group of second exposure processes includes a first step, which has the following characteristics: Figure 9B The starting position is shown. In this case, the first scan action exposes only two subfields (1,1) and (1,2). Then, as... Figure 9D As shown, it moves N along the Y direction. y *D y The second scan only exposes two subfields (1,3) and (1,4). Then, it moves N along the X direction. x *D x To cover four subfields: (2,3), (3,3), (2,4), and (3,4). For example... Figure 9M As shown, this continues until the last stepping action reaches the subfields (6,1) and (6,2). Subsequent scanning actions expose these two subfields. The second exposure process requires a total of 8 stepping scan cycles.

[0088] The first group of third exposure processes includes a first step, which has the following characteristics: Figure 9J The starting position is shown. In this case, the first scan action exposes two subfields (1,1) and (2,1). Then, as... Figure 9H As shown, it moves N along the Y direction. y *D y The second scan exposure includes four subfields (1,2), (2,2), (1,3), and the entire field (2,3). Then, as... Figure 9F As shown, it moves N along the Y direction.y *D y This covers two subfields (1,4) and (2,4). Subsequent scans expose these two subfields. This continues until the last step reaches subfields (5,4) and (6,4). Subsequent scans expose these two subfields again. The third exposure process requires a total of 9 step scan cycles.

[0089] The first group of fourth exposure processes includes a first step, which has the following characteristics: Figure 9I The starting position is shown in the figure. In this example, the first scan action exposure includes the entire field of four subfields (1,1), (2,1), (1,2), and (2,2). Then, as shown... Figure 9G As shown, it moves N along the Y direction. y *D y The second scan only exposes the entire field, including the four subfields (1,3), (2,3), (1,4), and (2,4). Then, it moves N along the X direction. x *D x This covers four subfields (3,3), (4,3), (3,4), and (4,4). Subsequent scans expose the entire field of the aforementioned four subfields until the last step reaches subfields (5,3), (6,3), (5,4), and (6,4). Subsequent scans will expose these four subfields. The fourth exposure process requires only 6 scan cycles in total. The total scan cycle of the fourth exposure process in the first group is 35, which, as mentioned earlier, is equal to (2*N). x +1)*(2*N y +1). The above description is based on Figure 6A The photomask 600 has 2*2 subfields. Other hybrid lithography exposure processes use other photomasks, such as... Figure 6B The photomask is 600.

[0090] The aforementioned hybrid lithography process in Figure 10 The flowchart is further summarized as the first group of exposure processes 750 using the first photomask. The other groups are similar. The first group of exposure processes 750 includes a first exposure process 810, a second exposure process 820, ..., an Nth exposure process 830. The number of exposure processes in the first group is equal to N, which is further equal to N... x *N y(In this example, it's 2*2). The first exposure process 810 is applied to the resist layer with a first starting step position and a first number of step scan cycles; the second exposure process 820 is applied to the resist layer with a second starting step position and a second number of step scan cycles; ...; the Nth exposure process 830 is applied to the resist layer with an Nth starting step position and an Nth number of step scan cycles. The starting step positions for the N exposure processes are different, so each subfield exposes the IC pattern of the Nth sub-region of the first photomask N times. Each exposure process may include different numbers of step scan cycles due to different starting step positions. Each exposure process exposes the same subfield with IC patterns present on different sub-regions of the first photomask.

[0091] In the example above, the step size is a constant (fixed) when the photomask moves to the next position in the same direction. However, not only can the step size and scanning order be different, but the step size can also be different or changed. Figures 11-1 to 11-35 Another example is provided, which further describes a hybrid exposure process with different step sizes. Figures 11-1 to 11-35 This displays the complete stepping and scanning sequence of a photomask. The above process can be repeated up to the Mth photomask, such as... Figure 8 As shown. Figure 11-1 As shown, the photomask 1100 includes 2*3 sub-regions. The sub-regions on the photomask are labeled as sub-regions (i,j), representing the i-th sub-region along the X direction and the j-th sub-region along the Y direction, starting from the bottom left (1,1). The wafer 310 includes 9 fields, each field comprising 2*3 sub-fields. Therefore, in this example, N x and N y The values ​​are 2 and 3 respectively. Similarly, the secondary fields on the photomask are labeled as secondary field (i,j), which represents the i-th secondary field along the X direction and the j-th secondary field along the Y direction, with the sub-region starting from the lower left as (1,1).

[0092] from Figure 11-1 Initially, photomask 1100 is moved to a position such that the first field (1,1) is covered by a sub-region (in this example, sub-region (2,3)). Assume the sub-field dimensions in the X and Y directions are D respectively. x and D y In this example, starting from vertex 1110 of the first field (1,1), the distance to the first distance in the X direction is 0, and the distance to the second distance in the Y direction is D. y Or, as it is called step (0,D) y It is worth noting that, Figure 11-1To illustrate in a more understandable way, as mentioned above, the sub-region and the subfield have different dimensions. However, the images of the IC patterns in the sub-region are aligned and mapped to the subfield, which has the same dimensions. It is worth noting that stepping is the relative movement between the photomask and the wafer 310. Generally, it refers to the wafer moving relative to the photomask. For simplicity and better understanding, it is described as the photomask moving relative to the wafer. Next, the photomask 1100 is moved at a dose less than the optimized exposure dose E. op The exposure dose is scanned to form an IC pattern in the first field (1,1). Due to the position of the photomask, only a sub-region of the first field is exposed by the photomask 1100. Here, the first field (1,1) is marked as "1", which indicates that the first field (1,1) has been exposed once.

[0093] Please see Figure 11-2 The photomask 1100 moves 2*D along the Y direction. y To cover another subfield, the photomask 1100 is then scanned to form IC patterns on the three subfields (1,1), (1,2), and (1,3). In other words, only the three subfields (1,1), (1,2), and (1,3) are exposed. The numbers in these subfields represent the number of exposure processes completed so far. Note that in this step size of 2*D... y ,and Figure 11-1 The step size is different. Similarly, the numbers in the subfields indicate the number of exposure processes that have been completed for that subfield. In this example, the number of exposure processes for subfields (1,1), (1,2), and (1,3) are 2, 1, and 1, respectively.

[0094] Please see Figure 11-3 The photomask 1100 moves another D in the Y direction. y To cover another subfield. Then, the photomask 1100 is scanned to form IC patterns on the three subfields (1,2), (1,3) and (1,4) respectively.

[0095] To simplify the explanation, the hybrid lithography exposure process for a photomask will be described according to... Figures 11-1 to 11-35 The explanation will proceed in the following order. Figures 11-1 to 11-35 The step size in the step scan cycle is (0, D) y (0,2D) y (0,D) y (0,2D) y (0,D) y ), (D x ,0)(0,-D y (0, -2D) y (0,-D) y (0, -2D) y ), (Dx ,0), (0,2D y (0,D) y (0,2D) y (0,D) y ), (D x ,0)(0,-D y (0, -2D) y (0,-D) y (0, -2D) y ), (D x ,0), (0,2D y (0,D) y (0,2D) y (0,D) y ), (D x ,0)(0,-D y (0, -2D) y (0,-D) y (0, -2D) y ), (D x ,0), (0,2D y (0,D) y (0,2D) y ) and (0,D y ).like Figure 11-35 As shown, after supplementing the sequence, each subfield is exposed an average of 4 times. This example illustrates various alternatives. First, the step size is not constant. For example, from Figures 11-1 to 11-4 The first four steps have step sizes D along the Y direction. y 2D y D y and 2D y Secondly, by employing hybrid lithography processes with different, staged steps, the number of exposure processes obtained from a single photomask is not N=N. x *N y Instead, N' is smaller than N. In this example, the number of exposure processes obtained by one photomask is 2*2=4, not 2*3. In other words, N'=N x '*N y ', where N x 'and N y 'less than or at most equal to N' x and N y In particular, one pattern can be identified during the process. For example... Figures 11-1 to 11-35For each subfield of the wafer 310 shown, the subfield of each row 1 (e.g., (1,1), (2,1), ..., and (6,1)) is exposed four times by the corresponding sub-regions (1,1), (1,3), (2,1), and (2,3) of the photomask 1100. The subfield of each row 2 (e.g., (1,2), (2,2), ..., and (6,2)) is exposed four times by the four sub-regions (1,2), (1,3), (2,2), ..., and (2,3) of the photomask 1100. The subfield of each row 3 (e.g., (1,3), (2,3), ..., and (6,3)) is exposed four times by the four sub-regions (1,2), (1,3), (2,1), ..., and (2,3) of the photomask 1100. The same pattern is repeated for the fourth, fifth, and sixth rows.

[0096] Generally, this hybrid lithography process is achieved by using different and periodic steps, with the number of exposure processes being L' = M * N' = M * N. x '*N y ', which may be equal to or less than L=M*N=M*N x *N y In the formula above, N x ' is an integer, which can be 1, 2, ..., or N. x and N y ' is an integer, which can be 1, 2, ..., or N. y The additional condition is N x '*N y 'Greater than 1. In other words, N' x 'and N y 'Cannot all be 1.' Figures 11-1 to 11-35 In photomask 1100, the number of exposure processes for one photomask is N' = N x '*N y It can be 1*2, 2*1, 2*2 or 2*3.

[0097] Some embodiments of the present invention provide an extreme ultraviolet lithography (EUVL) method. The EUVL method is a hybrid exposure process comprising multiple exposure processes, each using an IC pattern defined in a different photomask image region. This IC pattern is associated with multiple photomasks and multiple sub-regions of each photomask. The EUVL method may further include determining an optimal exposure dose; determining available sub-regions of a photomask based on the IC pattern; and determining the number of photomasks M and a sub-region parameter N of a photomask based on the available sub-regions and a manufacturing cost function. x and N yThe manufacturing cost function defines a manufacturing cost associated with a hybrid lithography process as a function of both mask manufacturing cost and wafer manufacturing cost. The mask cost also includes blank mask cost, patterning cost, and mask repair cost. Wafer cost includes the cost of step-by-step scanning actions. A hybrid lithography process comprises multiple exposure processes, each using an exposure dose less than the optimal exposure dose, and the sum of the exposure doses of each of the multiple exposure processes approximately equal to the optimal exposure dose.

[0098] When different mask patterns (including different masks and different sub-regions of a mask) are used to expose the same IC pattern, a phase defect region may be included in one or more different mask patterns through a hybrid lithography process with multiple exposures. Since the exposure dose under different mask patterns is less than the optimal exposure dose, the impact of the phase defect region under different mask patterns is greatly reduced. Because these defects or defect regions are randomly distributed among various masks or their sub-regions, no single defect or defect region will receive a full exposure dose. More specifically, the aerial image intensity affected by each defect or defect region will be reduced, thereby decreasing the transferability of that defect or defect region.

[0099] Therefore, some embodiments of the present invention provide a photolithography method, including: forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first photomask onto a resist layer in a primary field; performing a second exposure process to image a second pattern of a second sub-region of the first photomask onto the aforementioned resist layer in a secondary field; and performing a third exposure process to image a third pattern of a first sub-region of a second photomask onto the resist layer in the secondary field. The second and third patterns are identical to the first pattern; and the first, second, and third exposure processes together form a latent image of the first pattern on the resist layer in the secondary field.

[0100] According to some embodiments of the present invention, the photolithography process further includes a fourth exposure process for imaging a fourth pattern of a second sub-region of the second photomask onto a resist layer in the subfield. The fourth pattern is identical to the first pattern.

[0101] According to some embodiments of the present invention, images of a first pattern, a second pattern, a third pattern, and a fourth pattern from various exposure processes are superimposed on a resist layer.

[0102] According to some embodiments of the present invention, the photolithography process further includes developing a resist layer to form a patterned photoresist having a pattern associated with a first pattern.

[0103] According to some embodiments of the present invention, the step of performing a first exposure process includes performing the first exposure process with a first exposure dose; the step of performing a second exposure process includes performing the second exposure process with a second exposure dose; the step of performing a third exposure process includes performing the third exposure process with a third exposure dose; the step of performing a fourth exposure process includes performing the fourth exposure process with a first exposure dose; the first exposure dose, the second exposure dose, the third exposure dose, and the fourth exposure dose are cumulatively accumulated to a cumulative exposure dose D. s Together, they determine a critical dimension (CD) of the first pattern on the resist layer.

[0104] According to some embodiments of the present invention, the cumulative exposure dose D s Equal to an optimal exposure dose E op The first and second photomasks have the same pattern, such that each of the first and second photomasks includes multiple sub-regions, and each sub-region displays the same pattern as the first pattern.

[0105] Some embodiments of the present invention provide an extreme ultraviolet lithography (EUVL) method, comprising: receiving an integrated circuit (IC) design layout; determining multiple candidate sub-regions based on the IC design layout; and determining a sub-region parameter N based on a manufacturing cost function and the candidate sub-regions. x With N y And a photomask parameter M; and according to the integrated circuit design layout, a first number of identical photomasks are manufactured. The first number is equal to the photomask parameter M, and each photomask is included in an array of N. x *N y Each sub-region is represented by a light mask, and each sub-region on each mask displays the same pattern.

[0106] According to some embodiments of the present invention, the manufacturing cost function is defined as a function of a photomask manufacturing cost and a photolithography exposure cost.

[0107] According to some embodiments of the present invention, the photomask manufacturing cost also includes a photomask fabrication cost, a blank photomask cost, and a photomask repair cost; the photolithography exposure cost is a function of a step time cost and a scanning time cost.

[0108] According to some embodiments of the present invention, the extreme ultraviolet lithography process further includes: forming a resist layer on a substrate; and performing a second number of exposure processes on an identical region in the resist layer using a photomask. The second number is equal to M*N. x '*N yEach of the exposure processes uses only one of the photomasks; the exposure process includes M groups that are paired with a first number of photomasks, thereby implementing each group of exposure processes using a paired photomask; each group of exposure processes also includes N sub-regions of the paired photomasks. x '*N y A first exposure process; a second number of exposure processes together form a latent image of a pattern in the region of the resist layer, wherein N x 'The value is 1, 2, ... or N x integers, and N y 'The value is 1, 2, ... or N y integers, where N x '*N y 'Greater than 1'.

[0109] According to some embodiments of the present invention, the extreme ultraviolet lithography process further includes: developing a resist layer to form a patterned photoresist with a pattern in the region.

[0110] According to some embodiments of the present invention, the extreme ultraviolet lithography process further includes determining an optimal exposure dose E for the resist layer. op .

[0111] According to some embodiments of the present invention, the region of the resist layer is exposed to M*N by a second number of exposure processes with corresponding exposure doses. x '*N y Each time, the exposure dose is less than the optimal exposure dose.

[0112] According to some embodiments of the present invention, the corresponding exposure doses from the exposure process are summed to a cumulative exposure dose E. s The cumulative exposure dose E s Equal to the optimal exposure dose E op .

[0113] According to some embodiments of the present invention, the corresponding exposure dose is equal to E op / M*N x '*N y '.

[0114] Some embodiments of the present invention provide a photolithography process method, comprising: receiving a first number (M) of photomasks, each of the photomasks having N... x *N y N sub-regions are configured in an array, where N x and N yThe values ​​are integers, and the number of sub-regions along the x and y directions are defined respectively, wherein the patterns of the sub-regions of the photomask are all the same as a circuit pattern; a resist layer is formed on a substrate; and a second number of exposure processes are performed on the resist layer. The second number is equal to M*N. x '*N y The exposure process includes M groups that are paired with a first number of photomasks, thereby implementing each exposure process using a paired photomask; each exposure process also includes N groups having a corresponding step position that is different from each other. x '*N y A first exposure process; a second number of exposure processes together form a latent image of a circuit pattern on the resist layer; N x 'For 1, 2, ... or N x integers, and N y 'For 1, 2, ... or N y integers, where N x '*N y 'Greater than 1'.

[0115] According to some embodiments of the present invention, each of the exposure processes provides a corresponding exposure dose to a resist layer in a region; the corresponding exposure doses from each of a second number of exposure processes are summed to a cumulative exposure dose E. s These factors collectively determine a critical dimension (CD) of the circuit pattern on the region of the resist layer.

[0116] According to some embodiments of the present invention, the step of performing a second number of exposure processes on the photoresist layer includes performing the second number of exposure processes with different step actions, wherein N x 'less than N' x and N y 'less than N' y .

[0117] According to some embodiments of the present invention, the step of performing a second number of exposure processes on the photoresist layer includes performing the second number of exposure processes with a constant stepping action, wherein N x 'equals N x and N y 'equals N y .

[0118] The foregoing embodiments or examples have outlined the features of the present invention, and those skilled in the art will better understand one embodiment of the invention. Those skilled in the art should understand that they can readily use the present invention to design or modify other processes and structures to achieve the same purpose and / or realize the same advantages of the embodiments or examples described herein. It will be understood by those skilled in the art that the above equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. An extreme ultraviolet (EUV) lithography process, comprising: Receiver integrated circuit design layout; Based on the aforementioned integrated circuit design layout, several candidate sub-regions are determined; Based on a manufacturing cost function and the aforementioned candidate sub-regions, determine the parameter N of a sub-region. x , one sub-region parameter N y And a photomask parameter M; Based on the above integrated circuit design layout, a first number of identical photomasks are manufactured; Wherein the first quantity is equal to the photomask parameter M, and each of the photomasks is included in an array configured with the sub-region parameter N. x *The above sub-region parameter N y Multiple sub-regions, and each of the aforementioned sub-regions on each of the aforementioned photomasks defines the same pattern; A resist layer is formed on a substrate; Determine the optimal exposure dose E for the above-mentioned resist layer op ;as well as Using the aforementioned photomask, a second number of multiple exposure processes are performed on the same area of ​​the aforementioned resist layer, wherein: The second quantity mentioned above is equal to M*N x '*N y '; Each of the above exposure processes uses only one of the above photomasks; The above exposure process includes M groups that are paired with the first number of photomasks, thereby using a paired photomask to perform the above exposure process for each group. The above exposure process for each group also includes using N of a corresponding sub-region of the above-mentioned matched paired photomasks. x '*N y 'One exposure process, the above N x '*N y An exposure process includes at least a first exposure process, a second exposure process, and a third exposure process, wherein: The first exposure process includes stepping the paired photomasks by a first distance to position a first pattern of a first sub-region of the paired photomasks in a primary field of the resist layer and exposing it to image the first pattern of the first sub-region of the paired photomasks onto the resist layer in the secondary field. The second exposure process includes stepping the paired photomasks by a second distance different from the first distance to position a second pattern of a second sub-region of the paired photomasks in the subfield of the resist layer and exposing it to image the second pattern of the second sub-region of the paired photomasks onto the resist layer in the subfield. The aforementioned third exposure process includes stepping the matched photomasks a third distance and exposing them, wherein the third distance is equal to the first distance and different from the second distance; and The aforementioned second number of exposure processes together form a latent image of the aforementioned pattern in the aforementioned region of the aforementioned resist layer, wherein N x 'The value is 1, 2, ... or N x integers, and N y 'The value is 1, 2, ... or N y integers, where N x '*N y 'Greater than 1'.

2. The extreme ultraviolet lithography process method as described in claim 1, wherein the manufacturing cost function is defined as a function of a photomask manufacturing cost and a lithography exposure cost.

3. The extreme ultraviolet lithography process method as described in claim 2, wherein the above-mentioned photomask manufacturing cost also includes a photomask production cost, a blank photomask cost, and a photomask repair cost.

4. The extreme ultraviolet lithography process method as described in claim 2, wherein the lithography exposure cost is a function of the step time cost and the scan time cost.

5. The extreme ultraviolet lithography process as described in claim 1 further includes developing the resist layer to form a patterned photoresist having the pattern described above in the region.

6. The extreme ultraviolet lithography process as described in claim 1, wherein the region of the resist layer is exposed to M*N by the second number of exposure processes with multiple corresponding exposure doses. x '*N y Each of the above exposure doses is less than the above optimal exposure dose.

7. The extreme ultraviolet lithography process method as described in claim 6, wherein the corresponding exposure doses from the above-described exposure processes are summed to a cumulative exposure dose E. s To jointly determine a critical size of the pattern on the aforementioned area of ​​the aforementioned resist layer.

8. The extreme ultraviolet lithography process as described in claim 7, wherein the cumulative exposure dose E s Equal to the above-mentioned optimal exposure dose E op .

9. The extreme ultraviolet lithography process as described in claim 7, wherein the corresponding exposure dose is equal to the optimal exposure dose E. op / M*N x '*N y '.

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