Calibration of RF attenuators

Abstract

Embodiments of the present disclosure relate to calibration of RF attenuators. The present disclosure relates to a circuit comprising an input terminal configured to receive a first signal at a first frequency; a demodulation chain connected with the input terminal and comprising a low noise amplifier having an input coupled with the terminal; a controllable variable impedance connected between a first node and a node configured to receive a reference potential, the first node being connected to the input terminal and / or the amplifier input; and a current source configured to deliver a current at the first frequency to the first node.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of French patent application No. 2101889, filed on February 26, 2021, which is incorporated herein by reference. Technical Field

[0003] This description relates generally to electronic circuits, and more specifically to wireless receiving circuits for sub-GHz radio frequency signals. Background Technology

[0004] Sub-GHz radio frequency signals have frequencies ranging from, for example, from 300MHz to 1GHz. These sub-GHz signals are used to wirelessly transmit data between a transmitting circuit configured to transmit sub-GHz signals and a receiving circuit configured to receive sub-GHz signals.

[0005] The receiving circuit is coupled to the antenna via an impedance matching network. The receiving circuit includes a demodulation chain for extracting data from the signal supplied to the receiving circuit by the antenna.

[0006] The demodulation chain, also known as the receiver chain, typically includes a low-noise amplifier. To prevent receiver chain saturation when the received signal power is too high, or to prevent excessively low receiver chain gain when the received signal power is too low, the receiver chain includes a controllable attenuator. The receiver chain gain is then related to attenuator control, or in other words, to the attenuation applied by the controllable attenuator to the sub-GHz signal received by the receiving circuitry. By appropriately controlling the attenuator, the receiver chain gain can be adapted to the power of the sub-GHz signal received by the antenna.

[0007] In practice, a calibration phase is provided for attenuator control. During this calibration phase, the sub-GHz signal is passed to the antenna, and the value of the corresponding signal at the receiver chain output is observed by changing the attenuator impedance. The attenuation introduced by the attenuator on the sub-GHz signal received by the demodulation chain is then derived for each of these impedance values. Therefore, when the receiver circuit operates, the attenuation value is selected based on the amplitude of the chain's output signal, and the attenuator impedance value corresponding to that attenuation is selected during the calibration phase.

[0008] However, this calibration phase is cumbersome to implement, especially since it requires accurate transmission of sub-GHz signals in an echo-free environment. Furthermore, particularly when the antenna is positioned close to conductive elements, this step does not account for the interference experienced by the antenna and its impedance matching network in their operating environment. Summary of the Invention

[0009] Therefore, it is necessary to overcome all or part of the shortcomings of known attenuator calibration methods for radio frequency signal receiver chains (more specifically, sub-GHz signal receiver chains).

[0010] It is also necessary to overcome all or part of the shortcomings of known circuits, including the receiver chain, in which such calibration methods are implemented.

[0011] One embodiment overcomes all or part of the drawbacks of known calibration methods for attenuators in radio frequency signal receiver chains (more specifically, sub-GHz signal receiver chains) and known circuits configured to implement these known methods.

[0012] One embodiment provides a circuit comprising: an input terminal configured to receive a first signal at a first frequency; a demodulation chain connected to the input terminal and including a low-noise amplifier having an input coupled (preferably connected) to the terminal; a controllable variable impedance connected between a first node and a node configured to receive a reference potential, the first node being connected to the input terminal and / or the amplifier input; and a current source configured to deliver a current at the first frequency to the first node.

[0013] According to one embodiment, the current source includes: a first circuit configured to transmit a second signal at the frequency of a local oscillator in the demodulation chain; a second circuit configured to transmit a third signal at an intermediate frequency in the demodulation chain; a mixer configured to receive the second and third signals, the output of the mixer being coupled (preferably connected) to an internal node of the current source; and a resistor coupling the internal node to the first node.

[0014] According to one embodiment, the third signal is a square wave signal and the mixer is a switch-mode mixer controlled by the third signal.

[0015] According to one embodiment, the second circuit includes an oscillator and a frequency divider, the oscillator being configured to transmit a signal at a frequency greater than the intermediate frequency of the demodulation chain, and the frequency divider being configured to transmit a third signal based on the signal transmitted by the oscillator.

[0016] According to one embodiment, the oscillator of the second circuit is a quartz oscillator.

[0017] According to one embodiment, the mixer includes a first switch connected between the mixer's output and a node configured to receive a second signal, and a second switch connected between the mixer's output and a node configured to receive a reference potential, the first and second switches being configured to be controlled to be in reverse phase according to a third signal.

[0018] According to one embodiment, the first circuit includes: a circuit configured to transmit a fourth square wave signal at a frequency equal to four times the frequency of a local oscillator; a first frequency divider configured to divide the frequency of the fourth signal by two; a second frequency divider configured to divide the frequency of the fourth signal by four; a dual-input gate configured to receive the output signals of the first and second frequency dividers, the gate being configured to perform an XOR function between the signals received by its inputs; a first resistor coupling the output of the second frequency divider to the output of the first circuit; and a second resistor coupling the output of its gate to the output of the first circuit.

[0019] According to one embodiment, the value of the first resistor is substantially equal to, for example, 0.348 / 0.84 times the value of the second resistor.

[0020] According to one embodiment, the current source includes a common-mode removal capacitor element, and a resistor coupling an internal node of the current source to a first node is connected in series with the common-mode removal capacitor element between the internal node and the first node.

[0021] According to one embodiment, the current source is also configured to selectively turn on or off.

[0022] Another embodiment provides a method of using the circuit, the method comprising the steps of: a) selecting a value of a controlled variable impedance; b) acquiring a signal at the output of the demodulation chain while current is passed to a first node through a current source; and c) deriving, for the impedance value selected in step a), at least from the signal acquired in step b) the attenuation value introduced into the receiver chain by the variable impedance.

[0023] According to one embodiment, the method further includes: step b') between steps a) and c), step b') including acquiring a signal at the output of the demodulation chain when the current source is turned off, and wherein at step c), the attenuation value is derived from at least the signal acquired at step b) and the signal acquired at step b').

[0024] According to one embodiment, steps a) and c) are repeated for each of the multiple values ​​of the variable impedance.

[0025] According to one embodiment, at one step of step a), the variable impedance is equivalent to an open circuit for the selected value.

[0026] According to one embodiment, at each step c), when the variable impedance is equivalent to an open circuit, the attenuation value is derived from at least the signal observed at the corresponding step b) and the signal observed at step b. Attached Figure Description

[0027] The above-described features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration rather than limitation, in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 An example of a device applying the type of the described embodiment is schematically shown in boxes;

[0029] Figure 2 It is shown in the form of an equivalent circuit. Figure 1 Part of the device;

[0030] Figure 3 The equivalent circuit is shown as... Figure 1 An embodiment of a device similar to that of a device;

[0031] Figure 4 It is shown schematically in the form of a box. Figure 3 An example of a current source for a circuit;

[0032] Figure 5 A schematic diagram of an embodiment is shown in the form of a box. Figure 4 Details of the current source;

[0033] Figure 6 A schematic diagram of an embodiment is shown in the form of a box. Figure 4 Other details about the current source; and

[0034] Figure 7 An embodiment of a circuit including an RF receiver chain is schematically shown in the form of a box. Detailed Implementation

[0035] In the various figures, the same features are indicated by the same reference numerals. Specifically, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0036] For clarity, only steps and elements useful for understanding the embodiments described herein are illustrated and described in detail. Specifically, common demodulation chains for sub-GHz wireless signal receiving circuits are not described in detail, and the described embodiments, implementations, and variations are compatible with common demodulation chains.

[0037] Unless otherwise stated, when referring to two elements connected together, it means a direct connection without any intermediate elements other than conductors, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0038] In the following disclosure, unless otherwise stated, when referring to absolute positional qualifiers such as “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or relative positional qualifiers such as “above,” “below,” “up,” “down,” etc., or directional qualifiers such as “horizontal,” “vertical,” etc., refer to the orientation shown in the figure.

[0039] Unless otherwise stated, the terms “approximately,” “about,” “basically,” and “on the order of…” indicate less than 10%, preferably less than 5%.

[0040] Figure 1 An example of a device 1 of the type described in the embodiment is illustrated schematically in the form of a box.

[0041] Device 1 includes circuitry 100. Circuitry 100 includes an input terminal RFin configured to receive a sub-GHz signal at frequency FRF. Circuitry 100 includes a receive chain 101 connected to the terminal RFin. Receiver chain 101 is configured to extract data from the signal received at the terminal RFin. Receiver chain 101 includes a low-noise amplifier LNA having an input coupled (e.g., connected) to the terminal RFin. The output of the amplifier LNA is connected to the remainder of receive chain 101.

[0042] As those skilled in the art will know, in addition to the amplifier LNA, the receiver chain 101 includes at least one local oscillator LO configured to transmit a signal at frequency FLO.

[0043] Furthermore, the receiver chain 101 includes at least one mixer 102. The mixer 102 is configured to multiply or combine a signal at frequency FRF, which is transmitted at the output of the amplifier LNA, with a signal at a local frequency FLO. The output signal of the mixer 102 therefore includes two frequencies, f1 and f2, which are equal to FRF+FLO and FRF-FLO, respectively. One of these frequencies (e.g., frequency f2) is referred to as the intermediate frequency Fint of the receiver chain 101. For example, the frequency Fint is in the range of 200 kHz to 500 kHz, such as being equal to 300 kHz.

[0044] As an example, the receiver chain 101 includes only one mixer 102, which has an input coupled (e.g., connected) to the output of the amplifier LNA and another input configured to receive a signal at frequency FLO.

[0045] According to another example, the receive chain 101 includes a first mixer 102 and a second mixer 102 ( Figure 1(Not shown above), each mixer has an input coupled (e.g., connected) to the output of an amplifier LNA. The first mixer 102 has another input configured to receive a first signal at frequency FLO. The second mixer 102 has another input configured to receive a second signal at frequency FLO, the second signal being 90° out of phase with the first signal.

[0046] The receiver chain 101 also includes at least one filter IF, configured to receive the output signal of at least one mixer 102 and transmit a filtered signal that does not contain a frequency f1 or f2 that is not equal to the frequency Fint. The filtered signal includes a frequency f1 or f2 that is equal to the frequency Fint.

[0047] As an example, when chain 101 includes a unique mixer 102, chain 101 includes a unique filter IF.

[0048] According to another example, when chain 101 includes two mixers 102, as described above as an example, chain 101 includes a first filter IF configured to receive the output signal of the first mixer 102 and a second filter IF configured to receive the output signal of the second mixer 102. One of these two filter IFs then transmits signal I, while the other filter IF transmits a signal Q that is orthogonal to signal I.

[0049] According to yet another example, when chain 101 includes two mixers 102, as described above as an example, chain 101 includes a single filter IF, typically referred to as a complex or polyphase filter, which receives the output signal from each of the two mixers 102. Filter IF delivers two signals, I and Q.

[0050] The receiver chain 101 also includes at least one analog-to-digital converter (ADC). The ADC is configured to sample the analog signal of the receiver chain 101 at a frequency Fint. Preferably, the ADC is positioned after (multiple) filters IF, i.e., downstream of the filters IF relative to the direction of signal propagation in chain 101.

[0051] As an example, when chain 101 includes only one mixer 102 and only one filter IF, chain 101 includes only one converter ADC, which has an input coupled to the output of filter IF.

[0052] According to another example, when chain 101 includes two mixers 102 and one or two filters IF configured to provide signals I and Q, receiver chain 101 includes a first converter ADC and a second converter ADC, the input of the first converter ADC being coupled to the output of the filter providing signal I, and the input of the second converter ADC being coupled to the output of the filter providing signal Q.

[0053] The receiver chain transmits at least one output signal, and more specifically, at least one digital output signal. The output signals(s) of receiver chain(s) 101 are, for example, provided to the digital processing circuitry of circuit 100. Figure 1 (Not shown in the image).

[0054] Furthermore, despite Figure 1 Not shown above, but preferably, the receiver chain 101 includes a mirror frequency suppression device or function. When the frequency FRF is equal to FLO+Fint and FLO-Fint respectively, the mirror frequency Fim is equal to FLO-Fint and FLO+Fint respectively.

[0055] As an example, a mirror frequency suppression device is a bandpass filter that allows frequency FRF to pass through but blocks frequency Fim. This filter is positioned, for example, between terminal RFin and the input of amplifier LNA, or between the output of amplifier LNA and mixer(s) 102. However, this type of filter is often difficult to implement, especially when the frequency Fint is low, for example below 10MHz, and particularly difficult to integrate monolithically.

[0056] According to another example, image frequency suppression is achieved by a filter IF, in the case where the most recent one is a complex or polyphase filter. In this case, the possible contributions of image frequencies in the signals I and Q provided by the complex or polyphase filter are suppressed.

[0057] According to another example, the image suppression device is implemented after the filter IF that provides signals I and Q. For example, the image frequency suppression device includes a phase shifter configured to apply a 90° phase shift to signal Q and sum the signal I with the phase-shifted signal Q available at the phase shifter output. An image frequency Fim suppression device is configured to pass signals at frequency Fint, where any possible contribution from the image frequency Fim is suppressed. This image frequency suppression device can be implemented analogically and then placed before the converter ADC for signals I and Q, or digitally and then placed after the converter ADC coupled to the output of the filter IF.

[0058] All the content described above regarding receiving chain 101 is common to those skilled in the art, and the described embodiments, implementations, and variations are not limited to the examples of chain 101 given above.

[0059] To adjust the amplitude of the output signal of the amplifier LNA, circuit 100 includes... Figure 1 The controllable attenuator 104 is defined by the dashed line.

[0060] Attenuator 104 corresponds to a controllable impedance connected between node 106 and the input or terminal RFin of amplifier LNA, node 106 being configured to receive a reference potential, preferably ground (GND). In other words, impedance 104 has a conductive terminal coupled to, preferably, node 106, and another conductive terminal coupled to, preferably, the input RFin or the input of amplifier LNA. Alternatively, impedance 104 has a conductive terminal coupled to, preferably, node 106, and another conductive terminal coupled to, preferably, node 105, which is connected to the input and / or terminal RFin of amplifier LNA. Preferably, terminal RFin is the same as the input of amplifier LNA.

[0061] Circuit 100, such as its receive chain, further includes a circuit AGC configured to control attenuator 104, i.e., control the value of impedance 104. The circuit AGC is programmed, for example, during a calibration phase, such that, based on one or more output signals of receive chain 101, the circuit AGC controls the value of attenuator 104 to vary such that the gain of attenuator 104 is adapted to the power of the sub-GHz signal received at terminal RFin. For example, when the output signal of receive chain 101 has an amplitude higher than a given maximum amplitude, such as corresponding to half the full scale of the (multiple) converter ADCs, attenuator 104 is controlled to add a given step size to the attenuation of the signal received at terminal RFin. Again, by way of example, conversely, when the output signal of receive chain 101 has an amplitude lower than a given minimum amplitude, such as corresponding to one-tenth or one-quarter of the full scale of the (multiple) converter ADCs, attenuator 104 is controlled to remove a given step size from the attenuation of the signal received at terminal RFin. As an example, in order to determine the control of attenuator 104, the output signal of chain 101, which has an amplitude compared with the minimum and maximum values, corresponds to the modulus of signals I and Q, that is, to the signal that is equal to the square root of the sum of the squares of signal I and the squares of signal Q.

[0062] Device 1 also includes an antenna 108 and an impedance matching network IMP. The network IMP couples the antenna 108 to a terminal RFin. Therefore, when the antenna 108 receives a sub-GHz signal, a corresponding signal is received at the terminal RFin. In practice, the antenna 108 and the network are external to circuit 100. For example, circuit 100 is implemented on an integrated circuit chip, where the antenna 108 and the network IMP do not form part of that chip.

[0063] As mentioned earlier, in device 1, the calibration steps for attenuator 104 are cumbersome and do not take into account the external interference that antenna 108 and network IMP may be subject to in their operating environment.

[0064] Figure 2 It is shown in the form of an equivalent circuit. Figure 1 Part of device 1. More specifically, Figure 2 It shows Figure 1 The antenna 108 of device 1 and the components of network IMP, and Figure 1 The circuit 100 includes attenuator 104 and amplifier LNA.

[0065] Figure 2 This illustrates that when a sub-GHz signal is received by the antenna, for example during the calibration phase, the antenna 108 and the network IMP (by voltage source 200 and impedance Zs connected in series between node 106 and terminal RFin of circuit 100) are connected. Figure 1 The components are defined by the dashed lines in the diagram. In other words, the antenna 108 and the network IMP (in...) Figure 1 The component (demarcated by a dashed line) is equivalent to, for example, Figure 2 The voltage source 200 and impedance Zs are shown connected in series between node 106 and terminal RFin of circuit 100.

[0066] In addition, Figure 2 In the diagram, the amplifier LNA is shown as a gain G and an input impedance Zin. In other words, the amplifier LNA is equivalent to a gain G and an impedance Zin. The input impedance Zin is connected, for example, between the input of the amplifier LNA and node 106.

[0067] Let Zatt be the impedance of attenuator 104, Vs be the voltage delivered by voltage source 200, Vin be the voltage on terminal RFin, and Zeq be the impedance equivalent to the parallel connection of attenuator 104 and impedance Zin between terminal RFin and node 106.

[0068] When attenuator 104 is absent, i.e., when impedance Zatt is infinite and attenuator 104 corresponds to an open circuit, voltage Vin equals voltage Vs multiplied by Zin / (Zin+Zs). When attenuator 104 is present, i.e., when impedance Zatt is not infinite and attenuator 104 does not correspond to an open circuit, voltage Vin equals voltage Vs multiplied by Zeq / (Zeq+Zs).

[0069] Therefore, in Figure 2 In this context, the attenuation produced by attenuator 104, expressed in dB, is equal to 20*log((Zeq / (Zeq+Zs))*((Zin+Zs) / Zin))).

[0070] Figure 3 The equivalent circuit is shown as... Figure 1 An embodiment of a device 1' similar to device 1'.

[0071] Specifically, similar to device 1, device 1' is with Figure 2 The same method includes antenna 108 and Figure 3 The network IMP shown Figure 1 The component of the device 1'. The device 1' further includes circuitry 100', which, instead of circuitry 100, includes a terminal RFin and a receiver chain 101 connected to the terminal RFin. Figure 3 In the diagram, only the attenuator 104 and amplifier LNA of circuit 100' are shown; the rest of the receiver chain 101 is shown, for example, in relation to... Figure 1 Similar to or the same as described. The input of the amplifier LNA is coupled (e.g., connected) to terminal RFin.

[0072] and Figure 1 and Figure 2 Compared to circuit 100, circuit 100' further includes a current source 300. The current source 300 is connected in parallel with impedance 104. In other words, when impedance 104 is connected between terminal RFin and node 106, the current source 300 is connected between terminal RFin and node 106, or when impedance 104 is connected between the input of amplifier LNA and node 106, the current source 300 is connected between the input of amplifier LNA and node 106. In other words, the current source 300 is connected between nodes 105 and 106, with node 105 connected to terminal RFin and / or the input of amplifier LNA. The current source 300 is configured to deliver a current ical to node 105, the frequency of which is equal to the frequency FRF of the signal Vin received at terminal RFin. Figure 3 In the example shown, the input of the amplifier LNA and the terminal RFin are the same. However, in another example not shown, a filter that implements image frequency suppression is connected between the terminal RFin and the input of the amplifier LNA, that is, between the terminal RFin and node 105, or between node 105 and the input of the amplifier LNA.

[0073] In addition, with Figure 2 In comparison, Figure 3 In one embodiment, voltage source 200 is shown as short-circuited.

[0074] like Figure 2 As shown, Zatt is referred to as the impedance of attenuator 104, Vin as the voltage on terminal RFin, and Zeq as the impedance equivalent to the parallel connection of attenuator 104 and impedance Zin between terminal RFin and node 106.

[0075] When attenuator 104 is absent, voltage Vin equals current ical multiplied by (Zin*Zs) / (Zin+Zs). When attenuator 104 is present, voltage Vin equals current ical multiplied by (Zeq*Zs) / (Zeq+Zs). Therefore, as Figure 2 In the case described above, the attenuation of the voltage Vin generated by attenuator 104, expressed in dB, is equal to 20*log((Zeq / (Zeq+Zs))*((Zin+Zs) / Zin))).

[0076] Therefore, in Figure 2 During the calibration phase of receiving sub-GHz signals, antenna 108 is at least partially equivalent to voltage source 200, and the corresponding signal Vin is available at terminal RFin. However, in Figure 3 During the calibration phase, instead of transmitting a sub-GHz signal to antenna 108 to acquire the signal Vin at terminal RFin, it is assumed that antenna 108 does not receive a signal (source 200 is short-circuited) and the signal Vin is acquired using current source 300. The calibration phase can therefore be implemented using current source 300.

[0077] In device 1', if the calibration phase of attenuator 104 is implemented in device 1, the phase calibration of attenuator 104 is achieved by passing current ical to node 105 due to current source 300, which makes it possible to avoid transmitting sub-GHz signals to antenna 108.

[0078] One advantage of circuit 100' is that, during the calibration phase of attenuator 104, even when the impedance Zs is altered by the environment of device 1', consideration is given to the interaction with antenna 108 and network IMP ( Figure 1 The impedance of the component is the impedance Zs corresponding to the impedance of device 1'. Therefore, the calibration phase can be performed in the operating environment of device 1'.

[0079] According to one embodiment, the calibration steps are implemented as follows.

[0080] At step a), the impedance value Zatt of attenuator 104 is selected. At the next step b), the output signal of the receiver chain is observed when the current ic is passed to node 105. At the next step c), the attenuation introduced by the attenuator for the value Zatt selected at step a) is determined at least in part based on the signal observed at step b).

[0081] Steps a), b), and c) are repeated for multiple values ​​of impedance Zatt. Therefore, when device 1' is operating, the gain of the receiver chain is adapted by selecting an attenuation value based on the output signal of receiver chain 101, that is, by selecting an impedance Zatt value corresponding to that attenuation value determined during the calibration phase.

[0082] Among the values ​​of Zatt selected during the calibration phase, according to one embodiment, one of these values ​​corresponds to the case where attenuator 104 is equivalent to an open circuit. In other words, one of the Zatt values ​​selected during the calibration phase is infinite. In this case, the attenuation introduced by attenuator 104 is zero, and the signal observed at the output of the chain corresponds to the maximum gain Gmax of the receiving chain. Therefore, for each of the other values ​​of impedance Zatt, the attenuation introduced by attenuator 104 relative to gain Gmax can be determined.

[0083] For example, when the selected impedance Zatt is infinite at step a), the signal observed at the output of the receiver chain at the corresponding step b) is equal to Gmax*Vin. And when the selected impedance is equal to the value Zatt1 at another step a), the signal observed at the output of the receiver chain at the corresponding step b) is equal to G1*Vin, where G1 is the gain of the receiver chain for the value Zatt1. The gain G1 is equal to Gmax - Att1, where Att1 is the attenuation introduced by attenuator 104 when the impedance Zatt is equal to Zatt1. Therefore, by calculating the ratio of the signal observed at step b) when the impedance Zatt is equal to Zatt1 to the signal observed at step b) when the impedance Zatt is infinite, the ratio of gain G1 to gain Gmax is obtained, and thus the attenuation value Att1 corresponding to the impedance Zatt being equal to Zatt1 is obtained.

[0084] According to another example, after obtaining an output signal equal to Gmax*Vin, the value of the impedance Zattx corresponding to a given attenuation Attx is searched. To do this, at each step a), the value of the impedance Zattx is modified so that the output signal of the demodulation chain is observed at the corresponding step b), and the output signal is equal to (Gmax-Attx)*Vin. When this signal is observed at step b), in the next step c), this means that the attenuation is actually equal to Attx, and therefore the last value chosen for the impedance Zattx at step a) is the value Zattx. The attenuation Attx is thus associated with the value Zattx of the impedance Zattx, and in operation, when attenuation Attx is required, choosing the attenuator value Zattx is sufficient.

[0085] Outside of the calibration phase, for example by providing a switch connected between current source 300 and node 105 ( Figure 3 (Not shown in the image), and then the switch is controlled to the off state to turn off the current source 300, which is then turned off. According to another example, the current source 300 is turned off or on by a control signal directly received by the current source 300.

[0086] In fact, in device 1', short-circuiting source 200 is equivalent to short-circuiting antenna 108. Figure 1 This is impossible. Therefore, according to one embodiment, the calibration phase includes a step b') between every two consecutive steps a) and b), where step b') includes obtaining the output signal of the demodulation chain when the current source 300 is turned off. This makes it possible to determine the contribution of antenna 108 to the output signal based on this output signal of the demodulation chain. Therefore, during the next step c), the attenuation introduced by the attenuator is determined by the signals obtained at the corresponding steps b) and b'), and is independent of the contribution of antenna 108. In other words, the attenuation is determined as if antenna 108 were effectively short-circuited.

[0087] The advantage of device 1', and more specifically circuit 100', is that the calibration phase of attenuator 104 can be implemented automatically by circuit 100', for example, through digital processing circuitry connected at the output of the receiver chain and / or through circuit AGC. In other words, the entire calibration phase can be performed directly by circuit 100'.

[0088] Another advantage of circuit 100' is that the attenuation ratio corresponding to each impedance value Zatt is determined more accurately in circuit 100. This improved accuracy is particularly due to the fact that the environment of device 1' is taken into account for each determined attenuation. This improved accuracy also stems from the fact that the current ical during the calibration phase implemented in device 1' is better controlled than the voltage Vin during the calibration phase implemented in device 1. Therefore, the hysteresis value of the control of attenuator 104 in circuit 100' can be smaller than that of the control of attenuator 104 in circuit 100. In fact, providing a hysteresis value in the control of attenuator 104 can avoid instability when modifying the Zatt value to adapt to the power attenuation of the received sub-GHz signal. This reduction in hysteresis value can increase the dynamics of the receiver chain and reduce the impact of receiver chain noise.

[0089] Another advantage of circuit 100' is that the calibration step can be performed after each modification of the operating frequency FRF of device 1'. Therefore, device 1', more specifically its circuit 100', can operate over a wide frequency range, for example, from 300 MHz to 1 GHz, simply by modifying the frequency of source 300 to make the frequency of current ical equal to the operating frequency FRF. In other words, the calibration of attenuator 104 is performed against the operating frequency FRF of device 1'.

[0090] Another advantage of circuit 100' is that the impedance seen at terminal RFin by the sub-GHz signal supplied to terminal RFin, i.e., the input impedance of circuit 100', may be higher than the typical impedance of 50 ohms or 75 ohms, for example, it can be equal to about 100 ohms. This allows the circuit to operate with lower current in the receiver chain, thereby reducing the power consumption of circuit 100'. This would not be the case if attenuator 104 were replaced by a common or standard attenuator Pi. In fact, particularly due to the fact that the impedance of the components of the antenna and impedance matching network is altered by the environment, these attenuators Pi are adapted for receiver chains with well-controlled 50-ohm or 75-ohm input impedances, but not for higher input impedances that require the use of an external impedance matching network to couple the antenna to the input of the receiver chain.

[0091] According to one embodiment, the value or amplitude of the current ical is determined by the maximum power transmitted by antenna 108, for example, to comply with radio frequency transmission standards and not exceed this maximum power. For example, the current ical has a root mean square value of, for example, about 10 μA, such that when the current ical is passed to node 105, the power transmitted by antenna 108 does not exceed -57 dBm per 100 kHz range.

[0092] According to one embodiment, attenuator 104 is a variable resistor. For example, attenuator 104 includes a MOS transistor, preferably formed of a MOS transistor (“metal-oxide-semiconductor”). The MOS transistor has a first conductive terminal (e.g., its source when the transistor has an N-channel), which is coupled and preferably connected to node 106; and a second conductive terminal (e.g., its drain when the transistor has an N-channel), which is coupled and preferably connected to node 105. The gate of the transistor receives a control signal for attenuator 104. The on-resistance value of the transistor is then determined by the control signal for attenuator 104, and the impedance of the attenuator is preferably equal to the on-resistance of the transistor.

[0093] According to one embodiment, source 300 is configured such that current ical is a pure sine curve at the operating frequency FRF of device 1'.

[0094] However, such a current source can be bulky and complex to implement. Therefore, an embodiment of a current source 300 that enables the reuse of components or elements already present in circuit 100' will now be described.

[0095] Figure 4 It is shown schematically in the form of a box. Figure 1 An embodiment of the current source 300 of circuit 100'.

[0096] In this embodiment, an advantage is that the receiver chain of circuit 100' includes at least one local oscillator configured to transmit signals at frequency FLO, where frequency FLO is equal to FRF-Fint or FRF+Fint.

[0097] Therefore, in Figure 4 In this circuit, current source 300 includes a circuit or local oscillator LO'. Oscillator LO' is configured to transmit at the FLO frequency (i.e., to the frequency of the local oscillator of the receiving chain, for example, regarding...). Figure 1 The frequency of the oscillator (LO) described (the signal or voltage). For example, regarding... Figure 1 The circuit LO' described is the same as the local oscillator LO.

[0098] The current source 300 also includes circuit FI. Circuit FI is configured to transmit a signal or voltage at the intermediate frequency Fint of the demodulation chain.

[0099] The current source 300 also includes a mixer 400. The mixer 400 is configured to receive a signal at frequency FLO transmitted by the oscillator LO' and a signal at frequency Fint transmitted by the circuit FI. The mixer 400 is configured to multiply or combine these signals together.

[0100] According to one embodiment, the output signals of oscillator LO' and circuit FI are sinusoidal. In this embodiment, the signals or voltages available at the output of mixer 400 include a frequency f3 equal to FLO-Fint and a frequency f4 equal to FLO+Fint. One of frequencies f3 and f4 therefore corresponds to the operating frequency FRF. The other of frequencies f3 and f4 corresponds to the mirror frequency Fim. The output of mixer 400 is coupled, for example, to node 401.

[0101] According to one embodiment, in receive chain 101, the image frequency in the output signal of mixer 400 is filtered by an image frequency suppression device in the same manner as chain 101 filters the image frequency Fim when it is a sub-GHz signal provided by antenna 108 to terminal RFin. For example, the output of mixer 400 is then connected to node 401.

[0102] According to another embodiment, the receiver chain does not have a mirror frequency suppression device, and the source 300 includes a mirror frequency suppression function to suppress frequency mirrors Fim.

[0103] For example, although not shown, source 300 then besides Figure 4In addition to the first mixer 400 shown, a second mixer 400 is also included. The second mixer 400 is configured to multiply the output signal of circuit FI with a signal at frequency FLO but phase-shifted by 90° relative to the signal at frequency FLO received by the first mixer 400. Furthermore, the output of the second mixer 400, after undergoing a new phase shift of 90° relative to the output signal of the first mixer 400, is either added to or subtracted from the output of the first mixer 400 to obtain a signal without a mirror frequency Fim at node 401.

[0104] To convert the available voltage at node 401 into a corresponding current ical, resistor Rcal couples node 401 to the output 402 of source 300, and the output 402 of current source 300 is coupled, preferably, to node 105. Figure 3 The value of resistor Rcal is determined, for example, by the expected value of current ical, which itself is determined, for example, by the maximum power transmitted by the antenna that is not exceeded.

[0105] According to one embodiment, a decoupling capacitor element Ccal is connected in series with a resistor Rcal between node 401 and the output 402 of the current source 300. The capacitor Ccal enables the removal of any possible DC (“direct current”) component present in the signal available at node 401. In other words, the capacitor element Ccal is a common-mode removal capacitor element.

[0106] Figure 5 A schematic diagram of an embodiment is shown in the form of a box. Figure 4 Details of the 300 current source.

[0107] exist Figure 5 In this embodiment, circuit FI delivers a square wave output signal at frequency Fint. This allows for a simple implementation of mixer 400.

[0108] Therefore, according to one embodiment, mixer 400 is a switchable frequency mixer configured to be controlled by the square wave output signal of circuit FI. For example, mixer 400 is configured such that when the output signal of circuit FI is at a first level, its output signal is substantially equal to the output signal of oscillator LO', the first level, for example, corresponding to a high-level state of the signal, and such that when the output signal of circuit FI is at a second level, its output signal is empty, the second level, for example, corresponding to a low-level state of the signal.

[0109] According to one embodiment, mixer 400 includes a switch 500 that couples node 502 to the output 504 of the mixer, and a switch 506 that couples the output 504 of mixer 400 to node 106, wherein node 502 is configured to receive the output signal of oscillator LO'. Switches 500 and 504 are controlled to be in opposite phase by the output signal of circuit FI. In other words, mixer 400 includes switches controlled by the output signal of circuit FI, the switches being configured to selectively couple the output 504 of mixer 400 to either node 106 or the output of circuit FI.

[0110] According to one embodiment, circuit FI includes an oscillator XO and a frequency divider DIV. The oscillator XO is configured to transmit a signal at a frequency higher than the demodulation chain frequency Fint. The frequency divider DIV is configured to receive the output signal of the oscillator XO. The frequency divider is also configured to transmit the output signal of circuit FI based on the signal transmitted by the oscillator XO. For example, the output signal of the oscillator XO is a square wave signal. Preferably, the frequency divider DIV is implemented by a chain of flip-flops.

[0111] According to one embodiment, oscillator XO is a quartz oscillator configured to transmit a square wave signal, for example, at a frequency in the range of 47 MHz to 50 MHz. An advantage lies in the fact that such quartz oscillators are typically present in circuit 100', which is used for other functions, such as generating clock signals for digital circuitry of circuit 100'. Figure 3 In other words, according to one embodiment, the quartz oscillator XO is configured to pass its output signal to at least another circuit of circuit 100' other than circuit DIV, which is not part of current source 300.

[0112] exist Figure 5 In one embodiment, the signal transmitted by circuit FI is a square wave signal with frequency Fint, and according to another embodiment, the signal transmitted by circuit L0' is a sine wave signal. In this case, the output signal of mixer 400 includes frequency FRF, a mirror frequency, and frequencies equal to FLO-n*Fint and FLO+n*Fint, where n is a strictly positive integer and, for example, an odd number.

[0113] According to one embodiment, the image frequency Fim will be filtered by the image frequency suppression device of the receiver chain 101, and the harmonic frequency will also be filtered by the receiver chain, for example by (a plurality of) filters IF.

[0114] As a variant, current source 300 implements image frequency suppression, resulting in the signal at node 401 having no image frequency Fim. According to... Figure 4The relevant functional and structural indications indicate that implementing this image frequency suppression function in source 300 is within the capabilities of those skilled in the art. The harmonic frequencies of the signal on node 401 will be filtered by receiver chain 101, for example by filter IF.

[0115] Figure 6 A schematic diagram of an embodiment is shown in the form of a box. Figure 4 Other details about the current source 300. More specifically, Figure 6 An embodiment of the oscillator LO' is illustrated.

[0116] In this embodiment, oscillator LO' includes oscillator LO". Oscillator LO" is configured to transmit a square wave signal sigl with a frequency FLO4 equal to four times the frequency FLO. The low state of signal sigl is equal to 0V, or in other words, equal to the reference potential GND.

[0117] The oscillator LO' also includes frequency dividers DIV2 and DIV4.

[0118] Frequency divider DIV2 is configured to receive signal sigl and divide its frequency FLO4 by two. In other words, frequency divider DIV2 is configured to transmit signal sig2, which corresponds to the frequency FLO4 of signal sig1 divided by two. The frequency FLO2 of signal sig2 is therefore equal to twice the frequency FLO. Signals sig1 and sig2 have the same amplitude.

[0119] More precisely, the frequency divider DIV2 is configured to switch the signal sig2 at each edge of the first type signal sigl, for example, at each falling edge of the signal sigl.

[0120] Frequency divider DIV4 is configured to receive signal sigl and divide its frequency FLO4 by four. In other words, frequency divider DIV4 is configured to transmit signal sig3, which corresponds to the frequency FLO4 of signal sig1 divided by four. The frequency of signal sig3 is therefore equal to the frequency FLO. Signals sig1 and sig3 have the same amplitude.

[0121] More precisely, the frequency divider DIV4 is configured to switch the signal sig3 between the two edges of each second type signal sigl, for example, between each two rising edges of the signal sigl, the first type edge being different from the second type edge, and to select the first type and the second type between rising and falling types.

[0122] Oscillator LO' includes Figure 6The XOR gate in the diagram has a reference of 600. Gate 600 has two inputs. The first input of gate 600 is configured to receive signal sig2, and the second input of gate 600 is configured to receive signal sig3. Gate 600 is configured to transmit signal sig4. As is well known to those skilled in the art, gate 600 implements the XOR function between signals sig2 and sig3. In other words, when signals sig2 and sig3 are in different high and low states, signal sig4 is in a high state, and when signals sig2 and sig3 are in the same high or low state, signal sig4 is in a low state.

[0123] The oscillator LO' also includes a resistor Rf that couples the output of the frequency divider DIV4 to the output 602 of the oscillator LO', and a resistor R4f that couples the output of the frequency divider DIV2 to the output 602 of the oscillator LO'.

[0124] The value of resistor Rf is essentially equal to, preferably equal to, 0.348 / 0.84 times the value of resistor R4f. Therefore, the signal sig5 available at the output 602 of oscillator LO” is essentially equal to (for example, equal to) 0.84 times signal sig3 plus 0.38 times signal sig4. Thus, signal sig5 has a sinusoidal shape, but signal sig5 is not a sinusoidal signal. The fundamental frequency of signal sig5 is frequency FLO.

[0125] In the example shown, resistor Rf is connected between the output of frequency divider DIV4 and node 603, and resistor Rf4 is connected between the output of gate 600 and node 603, and node 603 is connected to node 602.

[0126] In another example not shown, resistor Rf is connected between the output of frequency divider DIV4 and node 603, and resistor R4f is connected between the output of gate 600 and node 603. Node 603 is coupled to output 602 through a common-mode removal capacitor element, such that signal sig5 is centered at potential GND, or in other words, has a zero average value.

[0127] It has been observed that, compared to a square wave signal with frequency FLO, signal sig5 does not contain harmonics of order 6 or less. In other words, besides lacking the 2nd, 4th, and 6th harmonics, signal sig5 does not include the 3rd and 5th harmonics present in a square wave signal.

[0128] This is particularly advantageous because when the signal sig5 is passed to the switching mode mixer 400 controlled by a square wave signal at frequency Fint, the 3rd and 5th harmonics of the signal sig5 cause unwanted currents to be superimposed on the current ical. These unwanted currents are not filtered by the receiver chain and contribute to the output signal of the receiver chain due to their frequency. In fact, although the receiver chain, especially due to the filter IF within it, is frequency selective, using the square wave signal sig5 and the circuit IF ( Figure 4 and Figure 5 The square wave output signal of mixer 400 will result in the output signal of mixer 400 having many different frequencies, especially when mixer 102 is a switching mode type, in which at least some frequencies can be brought to the intermediate frequency Fint by mixer 102 of receiving chain 101.

[0129] Although harmonics of order greater than 6 in the signal sig5 may also cause this undesirable current, their contribution to the output signal of the receiver chain is considered negligible. In fact, in the output signal of a switching-mode mixer whose switching is controlled by a square wave signal, such as mixer(s) 102 of receiver chain 101, the power of the harmonics from the square wave signal decreases with the order of the harmonics considered. Therefore, even if the signal sig5, i.e., the current ical, includes harmonics of order greater than 6, and these harmonics are brought back to frequency Fint when combined with harmonics of the square wave signal at frequency FLO in the switching-mode mixer 102, their effect on the power carried by frequency Fint of the output signal of mixer 102 is negligible. However, optionally, the oscillator LO' includes a low-pass filter (not shown), preferably tunable. This filter is configured to filter harmonics of order greater than 6 in the signal sig5. As an example, this filter is implemented by a preferably variable resistor and a capacitor element connected in series between node 106 and the output 602 of oscillator LO'. The adjustable resistor is implemented, for example, by a MOS transistor, and then corresponds to the on-resistance of that MOS transistor.

[0130] Preferably, the oscillator L0' includes a smoothing capacitor element Cf. The capacitor element Cf is configured to smooth or filter the shape of the signal sig5. The capacitor element Cf is connected between the output 602 of the oscillator L0' and node 106 at potential GND. In other words, the capacitor element Cf associated with the resistance of node 603 forms a simple and insignificant low-pass filter that filters out harmonics greater than the 6th order of the signal sig5 without affecting the fundamental frequency of the signal sig5.

[0131] According to one embodiment, oscillator L0” and preferably frequency dividers DIV2 and DIV4, one and / or the other, are also used in circuit 100' to generate at least one signal at frequency FLO, the at least one signal being configured to be passed to at least one corresponding mixer in the receiving chain. At least one mixer, such as mixer 102 ( Figure 1 For example, it is configured to multiply or mix at least one signal at frequency FLO with the output signal of the amplifier LNA in the receiver chain. In other words, oscillator LO” and preferably, one and / or the other of frequency dividers DIV2 and DIV4 form part of at least one local oscillator, such as the oscillator LO of the receiver chain. Figure 1 This allows for the reuse of the oscillator LO” and preferably one and / or the other of the frequency dividers DIV2 and DIV4 already present in circuit 100'. Figure 6 The oscillator LO'.

[0132] Figure 7 The combination is schematically shown in the form of a box. Figure 3 An embodiment of the circuit 100' is described, and more precisely, the combination is shown. Figure 3 An embodiment of the described device 1'.

[0133] exist Figure 7 In the device 1', there are circuit 100', antenna 108 and impedance matching network IMP that couples antenna 108 to input terminal RFin of circuit 100'.

[0134] Circuit 100' includes a receiver chain 101, which includes an amplifier LNA coupled to terminal RFin. Circuit 100' also includes a controllable impedance 104 connected between node 105 and node 106. In the example shown, the remainder of receiver chain 101 is related to... Figure 1 The same as described. Therefore, chain 101 includes at least one mixer 102, a local oscillator LO, at least one filter IF, and at least one converter ADC. However, regarding Figures 3 to 7 The described embodiments and variations are not limited to those concerning Figure 1 The example of receiver chain 101 described herein, and other examples of receiver chains including amplifier LNAs coupled to, preferably connected to, terminal RFin of circuit 100', will be provided to those skilled in the art.

[0135] Furthermore, circuit 100' includes an AGC circuit for controlling attenuator 104. As an example, the AGC circuit is configured to receive the moduli of signals I and Q, compare the moduli of signals I and Q with their maximum and minimum values, and, based on the results of these comparisons, increase or decrease the attenuation of the signal received at terminal RFin. As an example, the AGC circuit includes digital circuitry, such as a state machine, configured to receive the comparison results and select the impedance value of attenuator 104 based on these comparison results. As an example, the AGC circuit includes a lookup table storing the attenuation value of attenuator 104 and its corresponding impedance value determined during the calibration phase. As an example, each impedance value of attenuator 104 is stored in the lookup table in the form of a digital code. Each digital code is, for example, configured to, when provided to the digital-to-analog converter (DAC) of the AGC circuit, cause the DAC to provide a corresponding analog control signal to attenuator 104.

[0136] In addition, circuit 100' includes source 300, which is configured to deliver current ical to node 105, which is connected to terminal RFin and / or the input of amplifier LNA.

[0137] exist Figure 7 In the embodiment, source 300 is combined with Figure 5 To achieve this, the oscillator LO' is combined with... Figure 6 The above is to achieve this.

[0138] As an example, in Figure 7 In this example, switch 500 of mixer 400 is an N-channel MOS transistor, whose source is coupled, preferably, to node 502, and whose drain is coupled, preferably, to the output 504 of mixer 400. Switch 506 of mixer 400 is also an N-channel MOS transistor, whose source is coupled, preferably, to node 106, and whose drain is coupled, preferably, to the output 504 of mixer 400. In this example, the gate of transistor 500 receives the complementary signal of the output signal of circuit FI, and the gate of transistor 506 receives the output signal of circuit FI, but inversion is also possible. For example, the complementary signal of the output signal can be obtained at the output of inverter INV, which receives the output signal of circuit FI at its input.

[0139] Preferably, when the switches 500 and 506 of the mixer 400 are N-channel MOS transistors and the oscillator LO' is as described above... Figure 6In the described implementation, the common-mode removal capacitor element Cdc couples node 603 to the output 602 of oscillator LO'. When transistor 500 is controlled to be on and its gate receives a voltage corresponding to the high state of the output signal of circuit FI, this allows for an increase in the minimum amplitude of the voltage between the gate and source of transistor 500. In other words, this allows for a reduction in the on-resistance of transistor 500. Furthermore, the capacitor element Cdc allows the low levels or low states of signals sig1, sig2, sig3, and sig4 to correspond to ground GND, causing voltage dividers DIV2 and DIV4 and gate 600 to not draw DC current, which increases the power consumption of oscillator LO'.

[0140] As an example, in Figure 7 In this example, source 300 can be turned off by deactivating divider DIV, such that the output of circuit FI is in a state where transistor 506 is on and transistor 500 is off. According to another example, source 300 can be turned off by grounding the gate of transistor 506 to GND. Other methods of turning off source 300 will be within the capabilities of those skilled in the art.

[0141] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and other variations will occur to those skilled in the art. Specifically, while an example of chain 101 having multiple converters (ADCs) positioned at the chain end, after (multiple) filter(s) IFs, or even after a mirror frequency suppression device has been described, in other examples of the receive chain, (multiple) filter(s) IFs and / or mirror frequency suppression devices can be implemented as digital functions, and the converters (ADCs) are then positioned upstream of these digital functions, for example, by being connected to the output of mixer 102.

[0142] Furthermore, although the controllable impedance 104 has been described as being outside of chain 101 in the above description, impedance 104 and / or circuit AGC can be considered as part of receiving chain 101.

[0143] Furthermore, although not described or illustrated, the above embodiments and variations are applicable to situations where image frequency suppression is achieved through a filter (often referred to as an antenna filter) externally positioned in circuit 100' (i.e., upstream of terminal RFin relative to the propagation direction of the RF signal in device 1'). Note that in this case, the impedance of the antenna filter is included in the combination... Figure 2 and Figure 3 The impedance Zs is described.

[0144] Finally, based on the functional indications given above, the actual implementation methods of the described embodiments and variations are within the capabilities of those skilled in the art. Specifically, the implementation details of the calibration phase of attenuator 104 and / or the implementation details of the circuit AGC are within the capabilities of those skilled in the art based on the functional indications given above. Furthermore, according to... Figure 4 The relevant functional and / or structural indications allow those skilled in the art to understand the current source 300 as per relevant information. Figure 5 , Figure 6 and Figure 7 In the case of any of the descriptions, the image frequency suppression function is directly implemented in the current source 300.

Claims

1. A circuit comprising: The input terminal is configured to receive a first signal at a first frequency; The demodulation chain includes a low-noise amplifier having an input coupled to the input terminal; A controllable variable impedance is connected between a first node and a node configured to receive a reference potential, wherein the first node is connected to the input terminal and / or the amplifier input; as well as A current source is configured to deliver current at the first frequency to the first node.

2. The circuit according to claim 1, wherein the current source comprises: A first circuit is configured to transmit a second signal at the frequency of a local oscillator in the demodulation chain; The second circuit is configured to transmit a third signal at an intermediate frequency of the demodulation chain; A mixer is configured to receive the second signal and the third signal, wherein the output of the mixer is coupled to an internal node of the current source; as well as A resistor couples the internal node to the first node.

3. The circuit according to claim 2, wherein the third signal is a square wave signal, and the mixer is a switch-mode mixer controlled by the third signal.

4. The circuit of claim 3, wherein the second circuit comprises: An oscillator is configured to transmit a signal at a frequency greater than the intermediate frequency of the demodulation chain; And a frequency divider, configured to transmit the third signal from the signal transmitted by the oscillator.

5. The circuit according to claim 4, wherein the oscillator of the second circuit is a quartz oscillator.

6. The circuit of claim 3, wherein the mixer comprises: A first switch connected between the output of the mixer and a node configured to receive the second signal, and a second switch connected between the output of the mixer and the node configured to receive the reference potential, wherein the first switch and the second switch are configured to be controlled to be in reverse phase according to the third signal.

7. The circuit according to claim 2, wherein the first circuit comprises: A circuit configured to transmit a fourth square wave signal at a frequency equal to four times the frequency of the local oscillator. The first frequency divider is configured to divide the frequency of the fourth square wave signal by two. The second frequency divider is configured to divide the frequency of the fourth square wave signal by four. A dual-input gate is configured to receive the output signal of the first frequency divider and the output signal of the second frequency divider, wherein the gate is configured to perform an XOR function between the signals received by its inputs. The first resistor couples the output of the second frequency divider to the output of the first circuit. as well as The second resistor couples the output of the gate to the output of the first circuit.

8. The circuit of claim 7, wherein the ratio between the value of the first resistor and the value of the second resistor is equal to 0.348 / 0.

84.

9. The circuit of claim 2, wherein the current source includes a common-mode removal capacitor element, wherein the resistor coupling the internal node of the current source to the first node is connected in series with the common-mode removal capacitor element between the internal node and the first node.

10. The circuit of claim 1, wherein the current source is further configured to selectively turn on or off.

11. A method of operating a circuit, the method comprising: a) Receive a first signal at a first frequency through the input of a low-noise amplifier in the demodulation chain; b) A current at the first frequency is transmitted to a first node coupled to the input of the low-noise amplifier via a current source; c) Select the value of the controlled variable impedance that couples between the first node and the reference potential node; d) When the current is transmitted from the current source to the first node, acquire a signal at the output of the demodulation chain; as well as e) For the value of the variable impedance selected at step c), determine the attenuation value introduced into the demodulation chain by the variable impedance, based at least on the signal obtained at step d).

12. The method of claim 11, further comprising: Step d'), between steps c) and e), includes acquiring another signal at the output of the demodulation chain when the current source is turned off; as well as At step e), the attenuation value is determined at least based on the signal obtained at step d) and the other signal obtained at step d').

13. The method of claim 11, further comprising: Repeat steps c) and e) for each of the multiple values ​​of the variable impedance.

14. The method of claim 13, wherein at one step of step c), the variable impedance is equivalent to an open circuit for the selected value.

15. The method of claim 14, further comprising: At each step e), when the variable impedance is equivalent to the open circuit, the attenuation value is determined at least based on the signal observed at the corresponding step d) and the signal observed at step d).

16. The method of claim 11, further comprising: A second signal, at the frequency of the local oscillator in the demodulation chain, is transmitted through the first circuit of the current source. A third signal at the intermediate frequency of the demodulation chain is transmitted through the second circuit of the current source. The second signal and the third signal are received through a mixer having an output coupled to an internal node of the current source; as well as The internal node is coupled to the first node via a resistor.

17. The method of claim 16, wherein the third signal is a square wave signal, and the mixer is a switch-mode mixer controlled by the third signal.

18. The method of claim 17, further comprising: The oscillator of the second circuit transmits a signal at a frequency greater than the intermediate frequency of the demodulation chain. as well as The third signal, based on the signal transmitted by the oscillator, is transmitted through the frequency divider of the second circuit.

19. The method of claim 17, further comprising: The first and second switches of the mixer are controlled to be in opposite phase according to the third signal. The first switch is connected between the output of the mixer and the node receiving the second signal, and the second switch is connected between the output of the mixer and the reference potential node.

20. The method of claim 16, further comprising: A fourth square wave signal at a frequency equal to four times the frequency of the local oscillator is transmitted through the fourth circuit of the first circuit. The frequency of the fourth square wave signal is divided by two by the first frequency divider of the first circuit. The frequency of the fourth square wave signal is divided by four by the second frequency divider of the first circuit; The output signals of the first frequency divider and the second frequency divider are received through the dual-input gate of the first circuit. The gate enables an XOR function between the signals received as inputs. The output of the second frequency divider is coupled to the output of the first circuit through the first resistor of the first circuit; as well as The output of the gate is coupled to the output of the first circuit through the second resistor of the first circuit.

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