Data reading method, memory controller and memory storage device

Abstract

The present invention belongs to the field of storage technologies, and provides a data reading method, a memory controller, and a memory storage device. In a storage device configured with a rewritable non-volatile memory module having multiple dies or multiple planes, the memory controller can use a multi-plane reading operation to simultaneously issue read commands to multiple physical units belonging to different dies or different planes to simultaneously read data stored in the multiple physical units, thereby achieving an acceleration of the data reading speed.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and particularly to a data reading method, a memory controller, and a memory storage device. Background Art

[0002] Digital cameras, mobile phones, and MP3 players have grown very rapidly in recent years, which has led to a rapid increase in consumers' demand for storage media. Since the rewritable non-volatile memory module has characteristics such as data non-volatility, power saving, small size, no mechanical structure, and fast read and write speeds, it is very suitable as a storage media for various portable electronic products and is provided in various portable electronic products.

[0003] Inside NAND Flash, it can be divided into die, plane, block, and page. Among them, a die is a small square on a wafer. A chip may encapsulate several dies. Due to different flash processes and technologies, the concept of die is thus generated. Common ones include Mono Die, a Die, b die, etc. A chip contains N dies, and a die can include different numbers of planes according to different models. A plane is the smallest unit in NAND that can operate according to commands such as read, write, and erase. A plane is a storage matrix that contains several Blocks. A Block is the smallest erasure unit of NAND Flash, and a Block contains several Pages. A Page is the smallest read and write unit of a NAND chip, and a Page contains several Bytes.

[0004] When a host system desires to read stored data from a memory storage device, due to the data reading principle of the memory storage device, there will be a problem of data hit rate. That is, there may be a situation where data cannot be read out during a single data reading operation. Therefore, it is necessary to perform multiple data reading operations on the data. When applied to scenarios with a large amount of data and high requirements for data reading speed, if the data reading hit rate is low, it will seriously affect the data reading speed.

[0005] Therefore, how to improve the data reading hit rate of a memory storage device is a key issue that those skilled in the art are concerned about. Summary of the Invention

[0006] The technical solutions adopted by this application to improve the data reading speed of a memory storage device are as follows:

[0007] The first aspect of the present invention provides a data reading method, which is applied to a memory storage device. The memory storage device includes a memory module. The memory module includes at least one die. The die includes a plurality of planes. The plane includes a plurality of physical units. The physical unit includes a plurality of physical programmed units. The data reading method includes: receiving at least one read instruction from a host system, where each of the read instructions respectively indicates reading data in a physical unit; executing the read instruction, loading logic into a logical-to-physical mapping table, and according to a plurality of obtained logical-to-physical mapping relationships, performing a read operation on a first logical unit to realize reading data in a first physical unit and a second physical unit. The first logical unit is mapped to the first physical unit and the second physical unit; the first physical unit belongs to a first plane among the plurality of planes, the second physical unit belongs to a second plane among the plurality of planes, and the first plane is different from the second plane; the first plane and the second plane belong to the same die among the at least one die, and the address index values of the first physical unit and the second physical unit are the same.

[0008] The second aspect of the present invention further provides a memory controller. The memory storage device includes a connection interface, a memory module, and a memory controller; the memory module includes at least one die. The die includes a plurality of planes. The plane includes a plurality of physical units. The physical unit includes a plurality of physical programmed units; the memory controller includes: a host interface for connecting to a host system; a memory interface for connecting to the memory module; a buffer memory electrically connected to a memory control circuit and used for temporarily storing instructions and data from the host system or a logical-to-physical mapping table and data from the memory module; a memory control circuit connected to the host interface and the memory interface; the memory control circuit receives at least one read instruction from the host system, where each of the read instructions respectively indicates reading data in a physical unit; the memory control circuit is used for executing the read instruction, and the memory control circuit is used for loading the logical-to-physical mapping table into the buffer memory. According to a plurality of obtained logical-to-physical mapping relationships, the memory control circuit performs a read operation on a first logical unit to realize reading data in a first physical unit and a second physical unit. The first logical unit is mapped to the first physical unit and the second physical unit; the first physical unit belongs to a first plane among the plurality of planes, the second physical unit belongs to a second plane among the plurality of planes, and the first plane is different from the second plane; the first plane and the second plane belong to the same die among the at least one die, and the address index values of the first physical unit and the first physical unit are the same.

[0009] A third aspect of the present invention further provides a memory storage device, which includes a connection interface, a memory module, and a memory controller; the connection interface is used to connect the memory storage device to a host system; the memory module includes at least one die, the die includes a plurality of planes, the plane includes a plurality of physical units, and the physical unit includes a plurality of physical programming units; the memory controller is used to receive at least one read instruction from the host system, where each of the read instructions respectively indicates reading data in the physical unit; the memory controller is used to execute the read instruction, load logic into the logical-to-physical mapping table, and according to the obtained plurality of logical-to-physical mapping relationships, the memory controller performs a read operation on a first logical unit to read the data in a first physical unit and a second physical unit, and the first logical unit is mapped to the first physical unit and the second physical unit; the first physical unit belongs to a first plane among the plurality of planes, the second physical unit belongs to a second plane among the plurality of planes, and the first plane is different from the second plane; the first plane and the second plane belong to the same die among the at least one die, and the address index value of the first physical unit is the same as the address index value of the first physical unit.

[0010] The present invention provides a data reading method, a memory controller, and a memory storage device. In a storage device configured with a rewritable non-volatile memory module having a plurality of dies or a plurality of planes, the memory controller can use a multi-plane reading operation to simultaneously issue read instructions to a plurality of physical units belonging to different dies or different planes to simultaneously read the data stored in the above-mentioned plurality of physical units, thereby achieving an acceleration of the data reading speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the protection scope of the present invention. In each drawing, similar components are numbered similarly.

[0012] Figure 1 It is a schematic diagram of a memory storage device shown in an embodiment of the present invention;

[0013] Figure 2 It is a schematic diagram of a memory controller connected to a memory module shown in an embodiment of the present invention;

[0014] Figure 3 It is a structural block diagram of a memory controller shown in an embodiment of the present invention;

[0015] Figure 4 A schematic diagram of managing a memory module shown in an embodiment of the present invention;

[0016] Figure 5 A flowchart of a data reading method shown in an embodiment of the present invention;

[0017] Figure 6 A schematic diagram of a Die including physical units and physical programming units shown in an embodiment of the present invention;

[0018] Figure 7 A schematic diagram of the first type of data stored in a Die shown in an embodiment of the present invention;

[0019] Figure 8 A schematic diagram of the second type of data stored in a Die shown in an embodiment of the present invention;

[0020] Figure 9 A schematic diagram of the third type of data stored in a Die shown in an embodiment of the present invention. Detailed implementation manners

[0021] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments.

[0022] Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0023] Hereinafter, the terms "include", "have" and their cognates that can be used in various embodiments of the present invention are only intended to represent specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0024] In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention pertain. The terms (such as those defined in a commonly used dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, unless clearly defined in various embodiments of the present invention.

[0026] Embodiment

[0027] Figure 1 is a schematic diagram of a memory storage device shown according to an embodiment of the present invention. Please refer to Figure 1 , the storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 can be any type of computer system. For example, the host system 11 can be various electronic systems such as a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, a digital camera, etc. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices. The host system 11 can be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express), a Universal Serial Bus (USB), or other types of connection interfaces. Therefore, the host system 11 can store data to the memory storage device 12 and / or read data from the memory storage device 12.

[0028] The memory storage device 12 can include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, the connection interface 121 can support connection interface standards such as SATA, PCI Express, or USB. The memory storage device 12 can communicate with the host system 11 via the connection interface 121.

[0029] The memory module 122 is used to store data. The memory module 122 may include a rewritable non-volatile memory module. The memory module 122 includes a memory cell array. The memory cells in the memory module 122 store data in the form of voltage. For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, or other memory modules with similar characteristics.

[0030] Furthermore, in this embodiment, the physical programming unit is the smallest unit for programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit is a physical programming unit page or a physical sector. If the physical programming unit is a physical programming unit page, these physical programming units usually include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, and the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In this embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other embodiments, the data bit area may also contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical unit is the smallest unit for erasure. That is, each physical unit contains the smallest number of memory cells to be erased. For example, the physical unit is a physical block.

[0031] In this embodiment, the memory module 122 has multiple planes, and each plane belongs to a die. In one embodiment, the number of planes may be greater than the number of dies. That is, two or more planes may belong to one die. Each physical unit in the memory module 122 belongs to one plane. Each plane may include multiple physical units and multiple physical programming units.

[0032] Figure 2 It is a schematic diagram showing the connection of a memory controller to a memory module according to an embodiment.

[0033] Please refer to Figure 2, the memory module 122 has a die D0, and the die D0 includes four planes P0 to P3. Each of the planes P0 to P3 has a plurality of physical units, and each physical unit has a plurality of physical programmed units.

[0034] In this embodiment, the die D0 is connected to the memory controller 123 through a chip enable pin. The memory controller 123 can send an enable signal to the chip enable pin of the die D0 to enable the die D0. After the die D0 is enabled, data can be transferred between the memory controller 123 and the die D0 through a channel (e.g., a data bus). That is, the physical units of the planes P0 to P3 belonging to a die D0 are accessed via the channel, and the data stored in the planes P0 to P3 can be read in parallel via the channel using a multi-plane read operation.

[0035] However, in an example with multiple dies, the memory controller 123 can also enable multiple dies simultaneously through an enable signal, or enable multiple dies separately through multiple enable signals. And, the data stored in different dies can be accessed via different channels. For Figure 2 example, assume that plane P0 and plane P1 belong to one die, while plane P2 and plane P3 belong to another die. The data stored in plane P0 and plane P1 can be accessed via one channel, while the data stored in plane P2 and plane P3 can be accessed via another channel.

[0036] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be used to control the memory storage device 12. For example, the memory controller 123 can control the connection interface 121 and the memory module 122 to perform data access and data management. For example, the memory controller 123 can include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations of these devices.

[0037] In one embodiment, the memory controller 123 is also referred to as a flash memory controller. In one embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 can receive an instruction sequence from the memory controller 123 and access the storage units according to this instruction sequence.

[0038] Figure 3 is a block diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 3 , the memory controller 123 includes a memory control circuit 204, a host interface 202, and a memory interface 206.

[0039] The memory control circuit 204 is used to control the overall operation of the memory controller 123. Specifically, the memory control circuit 204 has a plurality of control instructions, and when the memory storage device 12 operates, these control instructions will be executed to perform operations such as data writing, reading, and erasing. When explaining the operation of the memory control circuit 204 below, it is equivalent to explaining the operation of the memory controller 123.

[0040] In this embodiment, the control instructions of the memory control circuit 204 operate in the form of firmware. For example, the memory control circuit 204 has a microprocessor unit ( Figure 3 not shown in the figure) and a read-only memory ( Figure 3 not shown in the figure), and the control instructions are burned into this read-only memory. When the memory storage device 12 operates, these control instructions will be executed by the microprocessor unit to perform operations such as data writing, reading, and erasing.

[0041] In another embodiment, the control instructions of the memory control circuit 204 can also be stored in a specific area of the memory module 122 in the form of program code (for example, the system area dedicated to storing system data in the memory module). In addition, the memory control circuit 204 has a microprocessor unit ( Figure 3 not shown in the figure), a read-only memory ( Figure 3 not shown in the figure), and a random access memory ( Figure 3 not shown in the figure). In particular, the read-only memory has a boot code, and when the memory controller 123 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the memory module 122 into the random access memory of the memory control circuit 204. After that, the microprocessor unit will execute these control instructions to perform operations such as data writing, reading, and erasing.

[0042] In addition, in another embodiment, the control instructions of the memory control circuit 204 can also operate in a hardware form. For example, the memory control circuit 204 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are electrically connected to the microcontroller. The storage unit management circuit is used to manage the storage units or groups thereof of the memory module 122. The memory write circuit is used to issue a write instruction sequence to the memory module 122 to write data into the memory module 122. The memory read circuit is used to issue a read instruction sequence to the memory module 122 to read data from the memory module 122. The memory erase circuit is used to issue an erase instruction sequence to the memory module 122 to erase data from the memory module 122. The data processing circuit is used to process the data to be written into the memory module 122 and the data read from the memory module 122. The write instruction sequence, the read instruction sequence, and the erase instruction sequence may each include one or more program codes or instruction codes, and are used to instruct the memory module 122 to perform corresponding write, read, and erase operations. In one embodiment, the memory control circuit 204 can also issue other types of instruction sequences to the memory module 122 to instruct the execution of corresponding operations.

[0043] The host interface 202 is electrically connected to the memory control circuit 204 and is used to receive and identify the instructions and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory control circuit 204 through the host interface 202. In this embodiment, the host interface 202 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 202 can also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0044] The memory interface 206 is electrically connected to the memory control circuit 204 and is used to access the memory module 122. That is, the data to be written to the memory module 122 will be converted by the memory interface 206 into a format acceptable to the memory module 122. Specifically, if the memory control circuit 204 wants to access the memory module 122, the memory interface 206 will transmit the corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence for indicating data writing, a read instruction sequence for indicating data reading, an erase instruction sequence for indicating data erasure, and corresponding instruction sequences for indicating various memory operations (such as changing the read voltage level or performing a garbage collection operation, etc.). These instruction sequences are generated by the memory control circuit 204, for example, and are transmitted to the memory module 122 through the memory interface 206. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in the read instruction sequence, information such as the read identification code and the memory address will be included.

[0045] In this embodiment, the memory controller 123 can perform single-frame encoding on the data stored in the same physical programming unit, or perform multi-frame encoding on the data stored in multiple physical programming units. According to the encoding algorithm adopted, the memory controller 123 can encode the data to be protected to generate the corresponding error correction code and / or error check code.

[0046] In one embodiment, the memory controller 123 further includes a buffer memory 210, an error checking and correcting circuit 212, and a power management circuit 208.

[0047] The buffer memory 210 is electrically connected to the memory control circuit 204 and is used to temporarily store instructions and data from the host system 11 or the logical-to-physical mapping table and data from the memory module 122. When the host system 11 desires to read data stored in the memory module 122, the host system 11 transmits one or more read instructions. The memory control circuit 204 can temporarily store the read instructions received from the host system 11 in the buffer memory 210. For example, the memory control circuit 204 can establish a command queue to store the received read instructions. These read instructions will indicate to read data in one or more physical units (physical programmed units). In order to execute these read instructions, the logical-to-physical mapping table is loaded into the buffer memory 210. The logical-to-physical mapping table includes a plurality of logical-to-physical mapping relationships, where the plurality of logical-to-physical mapping relationships include the mapping relationships of the physical units (physical programmed units) storing the data. Specifically, the mapping relationships of the physical units (physical programmed units) storing the data include a block mapping in which one logical address maps to one physical unit and a page mapping in which one logical address maps to one physical programmed unit.

[0048] However, in other embodiments, a read instruction can also indicate to read multiple logical addresses. In other words, the host system 11 can transmit a read instruction to indicate to read multiple data in multiple physical units or physical programmed units stored in the memory module 122.

[0049] The power management circuit 208 is electrically connected to the memory control circuit 204 and is used to control the power supply of the memory storage device 12.

[0050] The error checking and correcting circuit 212 is electrically connected to the memory control circuit 204 and is used to perform error checking and correcting operations to ensure the correctness of the data.

[0051] Specifically, when the memory control circuit 204 receives a write instruction from the host system 11, the error checking and correcting circuit 212 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write instruction, and the memory control circuit 204 writes the data corresponding to the write instruction and the corresponding error correcting code and / or error detecting code into the memory module 122. After that, when the memory control circuit 204 reads data from the memory module 122, it will simultaneously read the corresponding error correcting code and / or error detecting code of the data, and the error checking and correcting circuit 212 will perform error checking and correcting operations on the read data according to the error correcting code and / or error detecting code.

[0052] Figure 4 is a schematic diagram of managing a memory module as shown in an embodiment of the present invention. Please refer to Figure 4 , the memory module 122 includes a plurality of physical units 301(0)--301(A). Each physical unit includes a plurality of memory cells and is used to store data non-volatilely. For example, a physical unit may include one or more physical blocks. Each physical block may include a plurality of physical programmed units. A physical programmed unit may include one or more memory cells. The plurality of memory cells in a physical programmed unit can be programmed simultaneously to store data. In addition, all the physical programmed units in a physical block can be erased simultaneously.

[0053] Furthermore, as Figure 4 shown, the memory control circuit 204 can configure a plurality of logical units 302(0)--302(B) to map the physical units 301(1)--301(A). For example, a logical unit may be composed of one or more logical addresses. The mapping relationship between the logical unit and the physical unit can be recorded in the logical-to-physical mapping table (L2P). Exemplarily, the mapping of the logical physical block to the physical physical block is called block mapping; the mapping of the logical physical programmed unit to the physical physical programmed unit is called physical programmed unit (page) mapping. Hereinafter, the logical-to-physical mapping table can be understood as the logical-to-physical mapping table. When receiving an access instruction from the host system 11, the memory control circuit 204 can read data from the physical unit according to the corresponding logical-to-physical mapping table.

[0054] In an embodiment, when reading data from a plurality of physical units according to the indication of a read instruction, the memory control circuit 204 executes the read instruction, loads the logical-to-physical mapping table into the buffer memory 210, and according to the obtained plurality of logical-to-physical mapping relationships, in order to improve the data read speed, the memory control circuit 204 will determine the read order of the plurality of logical addresses according to the situation of the obtained plurality of logical-to-physical mapping relationships.

[0055] In one embodiment, it is set according to the dies and planes of the memory module 122. For example, the memory control circuit 204 may preferentially execute a read operation for a logical address corresponding to one die, and then execute a read operation for a logical address corresponding to another die. Alternatively, the memory control circuit 204 may preferentially execute read operations for logical addresses corresponding to different planes, which are referred to as first logical units in this embodiment; and then execute read operations for logical addresses of a certain plane, which are referred to as second logical units and third logical units in this embodiment. That is, the read operations for data that can be read in parallel are preferentially executed, and then the read operations for data that cannot be read in parallel are executed. This approach can relatively reduce the number of read times of logical addresses and improve the data read speed.

[0056] In one embodiment, a data reading method is proposed, as Figure 5 shown. Figure 5 FIG. is a flowchart of a data reading method according to an embodiment of the present invention.

[0057] S501: Receive at least one read instruction from a host system, where each of the read instructions respectively indicates reading data in physical units;

[0058] S502: Execute the read instruction, load the logical-to-physical mapping table, and according to the obtained multiple logical-to-physical mapping relationships, execute a read operation on the first logical unit to read the data in the first physical unit and the second physical unit;

[0059] S503: After executing the read operation on the first logical unit, execute a read operation on the second logical unit to read the data in the fifth physical unit;

[0060] S504: After executing the read operation on the second logical unit, execute a read operation on the third logical unit to read the data in the first physical programmed unit in the sixth physical unit.

[0061] Specifically, when reading data in multiple physical units according to the indication of the read instruction, the memory control circuit 204 executes the read instruction, loads the logical-to-physical mapping table into the buffer memory 210, and according to the obtained multiple logical-to-physical mapping relationships, in order to improve the data read speed, the memory control circuit 204 will determine the read order of the multiple logical addresses according to the situation of the obtained multiple logical-to-physical mapping relationships.

[0062] Preferably, in step S502, the step of performing a read operation on the first logic unit to read data in the first physical unit and the second physical unit further includes: performing a read operation on the first logic unit to read data in the third physical unit and the fourth physical unit.

[0063] Specifically, the first logic unit is mapped to the first physical unit and the second physical unit; the first physical unit belongs to the first plane among the multiple planes, the second physical unit belongs to the second plane among the multiple planes, and the first plane is different from the second plane; the first plane and the second plane belong to the same die among the at least one die, and the address index values of the first physical unit and the second physical unit are the same.

[0064] Furthermore, the first logic unit is mapped to the third physical unit and the fourth physical unit. The third physical unit belongs to the third plane among the multiple planes, the fourth physical unit belongs to the fourth plane among the multiple planes, and the third plane is different from the fourth plane; the first plane, the second plane, the third plane, and the fourth plane are different from each other, and the first plane, the second plane, the third plane, and the fourth plane belong to the same die among the at least one die, and the address index values of the first to fourth physical units are the same.

[0065] Furthermore, after performing the read operation on the first logic unit, it further includes performing a read operation on the second logic unit to read data in the fifth physical unit; wherein, the second logic unit is mapped to the fifth physical unit; the address index value of the fifth physical unit is different from the address index values of the first to fourth physical units; the fifth physical unit belongs to a physical unit in any one of the multiple planes.

[0066] Furthermore, after performing the read operation on the second logic unit, it further includes performing a read operation on the third logic unit to read data in the first physical programming unit in the sixth physical unit; wherein, the third logic unit is mapped to the first physical programming unit, and the first physical programming unit is any one of the multiple physical programming units in the sixth physical unit; the address index value of the sixth physical unit is different from the address index values of the first to fifth physical units; the sixth physical unit belongs to a physical unit in any one of the multiple planes.

[0067] Further, the mapping method of the first logic unit to the first to fourth physical units is that the logical physical unit is mapped to the physical physical unit; the mapping method of the second logic unit to the fifth physical unit is that the logical physical unit is mapped to the physical physical unit; the mapping method of the third logic unit to the sixth physical unit is that the logical entity programming unit is mapped to the physical entity programming unit.

[0068] Exemplarily, assume that there is one Die in the memory storage device 12, which is Die0; each Die includes 4 planes, namely P0 to P3; each Plane includes 5 physical units (Blocks), namely B0 to B4; each physical unit includes 10 physical programming units (Pages), namely PBA0 to PBA9, as Figure 6 shown. The data expression of the large file is Data0 to DataN, and the Data0 to DataN are stored dispersedly in Die0, as Figure 7 and Figure 8 shown.

[0069] Suppose there is a file, such as a movie, whose data is Data0 - Data7, and its storage method is as Figure 9 shown. Data0 is stored in Block0 of P0, Data1 is stored in Block0 of P1, Data2 is stored in Block0 of P2, and Data3 is stored in Block0 of P3. Block0 of P0 is the first physical unit, Block0 of P1 is the second physical unit, Block0 of P2 is the third physical unit, and Block0 of P3 is the fourth physical unit. Data4 is stored in Block1 of P0, Data5 is stored in Block2 of P1, Data6 is stored in Block3 of P2, and the fifth physical unit can be all or one of these three Blocks. Similarly, the sixth physical unit is Block4 of P3.

[0070] Now the host system 11 issues an instruction to read the movie from the memory storage device 12, and the memory controller 123 receives and executes the read instruction. As Figure 9 shown, the Data0 - Data7 of the movie are stored in 8 different physical units, and there are multiple different logical-to-physical mapping relationships. Exemplarily, if it is block mapping, there are 8 logical-to-physical mapping relationships. If it is page mapping, there are 77 logical-to-physical mapping relationships. Therefore, to execute the reading of Data0 - Data7, at least 8 logical address reads are required. In this way, the data reading speed is relatively slow or the data reading hit rate is relatively low.

[0071] The data reading method in the embodiment of the present application is to execute the reading operation of the first logic unit to read Data0 - Data3; then execute the reading operation of the second logic unit to read Data4, Data5, and Data6; finally execute the reading operation of the third logic unit to read Data7. In this reading method, the reading of one logical address, that is, the first logic unit, can read the data in 4 physical units. Obviously, to achieve Data0 - Data7 in the same way, the data reading method in the embodiment of the present application only needs to read the logical address 5 times, so it can complete the data reading of the movie faster.

[0072] In another embodiment, assume that plane P0 and plane P1 belong to one die, and plane P2 and plane P3 belong to another die. Receive at least one reading instruction from the host system 11, where each of the reading instructions respectively indicates reading the data in the physical unit; the memory controller 123 and the memory control circuit 204 execute the reading instruction, load the logical-to-physical mapping table, and according to the obtained multiple logical-to-physical mapping relationships, execute the reading operation of the first logic unit to read Data0 and Data1; the memory controller 123 and the memory control circuit 204 execute the reading operation of the first logic unit to read Data2 and Data3; after the memory controller 123 and the memory control circuit 204 execute the reading operation of the first logic unit, it further includes executing the reading operation of the second logic unit to read Data4, Data5, and Data6; after the memory controller 123 and the memory control circuit 204 execute the reading operation of the second logic unit, it further includes executing the reading operation of the third logic unit to read Data7.

[0073] In another embodiment, the execution entities of the above data reading method are the memory controller 123 and the memory control circuit 204.

[0074] In summary, the present invention provides a data reading method, a memory controller, and a memory storage device. In a storage device configured with a rewritable non-volatile memory module having multiple dies or multiple planes, the memory controller can use a multi-plane reading operation to simultaneously issue reading instructions to multiple physical units belonging to different dies or different planes to simultaneously read the data stored in the above multiple physical units, thereby achieving an acceleration of the data reading speed.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data reading method, applied to a memory storage device, characterized in that, The memory storage device includes a memory module, the memory module includes at least one die, the die includes a plurality of planes, the planes include a plurality of physical units, the physical units include a plurality of physical programmed units, and the data reading method includes: Receiving at least one read instruction from a host system, wherein each of the read instructions respectively indicates reading data in a physical unit; Executing the read instruction, loading logic into a logical-to-physical mapping table, and according to a plurality of obtained logical-to-physical mapping relationships, performing a read operation on a first logical unit to realize reading data in a first physical unit and a second physical unit, where the first logical unit is mapped to the first physical unit and the second physical unit; The first physical unit belongs to a first plane among the plurality of planes, the second physical unit belongs to a second plane among the plurality of planes, and the first plane is different from the second plane; The first plane and the second plane belong to the same die among the at least one die, and the address index values of the first physical unit and the second physical unit are the same; After performing the read operation on the first logical unit, it further includes performing a read operation on a second logical unit to realize reading data in a fifth physical unit; wherein, the second logical unit is mapped to the fifth physical unit; the address index value of the fifth physical unit is different from the address index values of the first physical unit and the second physical unit; the fifth physical unit belongs to a physical unit in any one of the plurality of planes; and then preferentially performing a read operation on data that can be read in parallel, and then performing a read operation on data that cannot be read in parallel.

2. The data reading method according to claim 1, wherein The step of performing the read operation on the first logical unit to realize reading data in the first physical unit and the second physical unit further includes: Performing a read operation on the first logical unit to realize reading data in a third physical unit and a fourth physical unit, where the first logical unit is mapped to the third physical unit and the fourth physical unit; The third physical unit belongs to a third plane among the plurality of planes, the fourth physical unit belongs to a fourth plane among the plurality of planes, and the third plane is different from the fourth plane; The first plane, the second plane, the third plane, and the fourth plane are different from each other, and the first plane, the second plane, the third plane, and the fourth plane belong to the same die among the at least one die, and the address index values of the first to fourth physical units are the same.

3. The data reading method according to claim 1, wherein After performing the read operation on the second logical unit, it further includes performing a read operation on a third logical unit to realize reading data in a first physical programmed unit in a sixth physical unit; wherein, the third logical unit is mapped to the first physical programmed unit, and the first physical programmed unit is any one of the plurality of physical programmed units in the sixth physical unit; The address index value of the sixth physical unit is different from the address index values of the first to fifth physical units; The sixth physical unit belongs to the physical units in any one of the multiple planes.

4. The data reading method according to claim 3, wherein The mapping method of the first logic unit to the first to fourth physical units is that the logical physical unit is mapped to the physical physical unit; The mapping method of the second logic unit to the fifth physical unit is that the logical physical unit is mapped to the physical physical unit; The mapping method of the third logic unit to the sixth physical unit is that the logical physical programmed unit is mapped to the physical physical programmed unit.

5. A memory controller, applied to a memory storage device, characterized in that The memory storage device includes a connection interface, a memory module, and a memory controller; the memory module includes at least one die, the die includes multiple planes, the plane includes multiple physical units, and the physical unit includes multiple physical programmed units; the memory controller includes: A host interface for connecting to a host system; A memory interface for connecting to the memory module; A buffer memory, which is electrically connected to the memory control circuit and is used to temporarily store instructions and data from the host system or the logical-to-physical mapping table and data from the memory module; A memory control circuit, which is connected to the host interface and the memory interface; The memory control circuit receives at least one read instruction from the host system, and each of the read instructions respectively instructs to read data in the physical unit; The memory control circuit is used to execute the read instruction, load the logical-to-physical mapping table into the buffer memory, and according to the obtained multiple logical-to-physical mapping relationships, the memory control circuit executes a read operation on the first logic unit to read the data in the first physical unit and the second physical unit, and the first logic unit is mapped to the first physical unit and the second physical unit; The first physical unit belongs to the first plane among the multiple planes, the second physical unit belongs to the second plane among the multiple planes, and the first plane is different from the second plane; The first plane and the second plane belong to the same die among the at least one die, and the address index value of the first physical unit is the same as the address index value of the first physical unit; After the memory control circuit executes the read operation on the first logic unit, the memory control circuit executes a read operation on the second logic unit to read the data in the fifth physical unit; wherein, the second logic unit is mapped to the fifth physical unit; the address index value of the fifth physical unit is different from the address index values of the first physical unit and the second physical unit; the fifth physical unit belongs to the physical units in any one of the multiple planes; thereby enabling the memory control circuit to preferentially execute the read operation of the data that can be read in parallel, and then execute the read operation of the data that cannot be read in parallel.

6. The memory controller according to claim 5, characterized in that, The memory control circuit performs a read operation on the first logical unit to read data from the first physical unit and the second physical unit, and further includes: The memory control circuit further performs a read operation on the first logical unit to read data from the third physical unit and the fourth physical unit, and the first logical unit is mapped to the third physical unit and the fourth physical unit; The third physical unit belongs to the third plane among the multiple planes, and the fourth physical unit belongs to the fourth plane among the multiple planes, and the third plane is different from the fourth plane; The first plane, the second plane, the third plane, and the fourth plane are different from each other, and the first plane, the second plane, the third plane, and the fourth plane belong to the same die among the at least one die, and the address index values of the first to fourth physical units are the same.

7. The memory controller according to claim 6, wherein After the memory control circuit performs a read operation on the second logical unit, the memory control circuit further performs a read operation on the third logical unit to read data from the first physical programmed unit in the sixth physical unit; wherein the third logical unit is mapped to the first physical programmed unit, and the first physical programmed unit is any one of the multiple physical programmed units in the sixth physical unit; The address index value of the sixth physical unit is different from the address index values of the first to fifth physical units; The sixth physical unit belongs to the physical units in any one of the multiple planes.

8. The memory controller according to claim 7, wherein The memory control circuit maps the first logical unit to the first to fourth physical units, wherein the mapping method is mapping from a logical physical unit to a physical physical unit; The memory control circuit maps the second logical unit to the fifth physical unit, wherein the mapping method is mapping from a logical physical unit to a physical physical unit; The memory control circuit maps the third logical unit to the sixth physical unit, wherein the mapping method is mapping from a logical physical programmed unit to a physical physical programmed unit.

9. A memory storage device, characterized in that, The memory storage device includes a connection interface, a memory module, and a memory controller; The connection interface is used to connect the memory storage device to the host system; The memory module includes at least one die, the die includes multiple planes, the plane includes multiple physical units, and the physical unit includes multiple physical programmed units; The memory controller is used to receive at least one read instruction from the host system, and each of the read instructions respectively instructs to read data from the physical unit; The memory controller is used to execute the read instruction, load the logical-to-physical mapping table, and according to the obtained multiple logical-to-physical mapping relationships, the memory controller performs a read operation on the first logical unit to read data from the first physical unit and the second physical unit, and the first logical unit is mapped to the first physical unit and the second physical unit; The first physical unit belongs to a first plane among the multiple planes, the second physical unit belongs to a second plane among the multiple planes, and the first plane is different from the second plane; The first plane and the second plane belong to the same die among the at least one die, and the address index value of the first physical unit is the same as the address index value of the first physical unit; After the memory controller executes a read operation on the first logical unit, the memory controller executes a read operation on a second logical unit to read data in a fifth physical unit; wherein, the second logical unit is mapped to the fifth physical unit; the address index value of the fifth physical unit is different from the address index values of the first physical unit and the second physical unit; the fifth physical unit belongs to a physical unit in any one of the multiple planes; thereby enabling the memory controller to preferentially execute a read operation on data that can be read in parallel, and then execute a read operation on data that cannot be read in parallel.

10. The memory storage device according to claim 9, characterized in that, The memory controller executing a read operation on a first logical unit to read data in a first physical unit and a second physical unit further includes: The memory controller further executes a read operation on the first logical unit to read data in a third physical unit and a fourth physical unit, and the first logical unit is mapped to the third physical unit and the fourth physical unit; The third physical unit belongs to a third plane among the multiple planes, the fourth physical unit belongs to a fourth plane among the multiple planes, and the third plane is different from the fourth plane; The first plane, the second plane, the third plane, and the fourth plane are different from each other, and the first plane, the second plane, the third plane, and the fourth plane belong to the same die among the at least one die, and the address index values of the first to fourth physical units are the same.

11. The memory storage device according to claim 10, wherein After the memory controller executes a read operation on the second logical unit, the memory controller further executes a read operation on a third logical unit to read data in a first physical programming unit in a sixth physical unit; wherein, the third logical unit is mapped to the first physical programming unit, and the first physical programming unit is any one of the multiple physical programming units in the sixth physical unit; The address index value of the sixth physical unit is different from the address index values of the first to fifth physical units; The sixth physical unit belongs to a physical unit in any one of the multiple planes.

12. The memory storage device according to claim 11, wherein The memory controller maps the first logical unit to the first to fourth physical units, wherein the mapping method is that a logical physical unit is mapped to a physical physical unit; The memory controller maps the second logical unit to the fifth physical unit, wherein the mapping method is that a logical physical unit is mapped to a physical physical unit; The memory controller maps the third logic unit to the sixth physical unit, wherein the mapping method is that the logical physical programming unit is mapped to the physical physical programming unit.

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