Cache access command processing systems, methods, apparatuses, devices, and storage media
By managing cache queues and using pipelined processing, the scheduling of cache access commands is optimized based on the cache access address and command type, thus solving the problem of low processing efficiency of cache access commands and achieving efficient processing of commands at the same address.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN JAGUAR MICROSYSTEMS CO LTD
- Filing Date
- 2022-03-22
- Publication Date
- 2026-07-10
AI Technical Summary
In existing technologies, cached access command processing is inefficient, especially when a same address access command fails, requiring the execution of all subsequent access commands to be suspended.
The cache queue management module inputs commands with the same cache access address into the same queue and processes these commands in the cache pipeline. The scheduling order of the next command is determined based on the command type and response data, avoiding the suspension of all commands when a cache miss occurs.
It improves the processing efficiency of cached access commands, ensures the order of commands at the same address, and avoids suspending the execution of subsequent commands when a cache miss occurs.
Smart Images
Figure CN115048142B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a cache access command processing system, method, apparatus, computer device, storage medium, and computer program product. Background Technology
[0002] With the development of computer technology, a method has emerged that uses non-blocking caches to handle access commands to the cache. In a non-blocking cache, if an access command to the cache is missed, that is, if the cache does not store the data corresponding to the access command, the MSHR (Miss States Handing Register) can be used to record the missed cache access command in the avoidance state save register to ensure the reception of subsequent access commands.
[0003] However, in the above-mentioned method of handling access commands, if there are multiple accesses to the cache and accesses to the same address, if an access command misses and another access command to the same address is received, it is often necessary to postpone the execution of all subsequent access commands in order to maintain the order of commands to the same address. Therefore, the above-mentioned method of handling cached access commands has low processing efficiency. Summary of the Invention
[0004] Therefore, it is necessary to provide a cached access command processing system, method, apparatus, computer device, computer-readable storage medium, and computer program product that can improve the efficiency of access command processing in order to address the above-mentioned technical problems.
[0005] In a first aspect, this application provides a cache access command processing system, including: a cache queue management module and a cache pipeline; wherein,
[0006] The cache queue management module is used to obtain the cache access command to be processed and the cache access address corresponding to the cache access command; input the cache access commands with the same cache access address into the same queue; and within one clock cycle, schedule a current cache access command from multiple non-idle queues into the cache pipeline.
[0007] The cache pipeline is used to process the current cache access command entering the cache pipeline and return the response data corresponding to the current cache access command to the cache queue management module.
[0008] The cache queue management module is configured to, when the current cache access queue corresponding to the current cache access command contains multiple cache access commands and the response data is received, obtain the cache access command to be scheduled that is processed after the current cache access command among the cache access commands contained in the current cache access queue; and determine the next cache access command to be scheduled into the cache pipeline based on the command type of the cache access command to be scheduled.
[0009] In one embodiment, the cache queue management module is further configured to, when the command type is a read command, not send the cache access command to be scheduled to the cache pipeline, and use the response data corresponding to the current cache access command as the response data corresponding to the cache access command to be scheduled.
[0010] In one embodiment, the cache queue management module is further configured to send the cache access command to be scheduled to the cache pipeline when the command type is a write command; the cache pipeline is further configured to obtain the response data corresponding to the cache access command to be scheduled and return the response data corresponding to the cache access command to the cache queue management module.
[0011] In one embodiment, the cache queue management module is further configured to, in the absence of receiving the response data, schedule another cache access command into the cache pipeline from a non-idle queue other than the current cache access queue corresponding to the current cache access command.
[0012] In one embodiment, the system further includes an MSHR module and a write buffer; wherein the cache pipeline is further configured to send the current cache access command to the MSHR module if the current cache access command is a miss command; the MSHR module is configured to query the write buffer based on the current cache access address corresponding to the current cache access command; if the write buffer stores data corresponding to the current cache access address, the write buffer retrieves the data corresponding to the current cache access address and returns the data to the cache pipeline.
[0013] In one embodiment, the MSHR module is further configured to, if the write buffer does not store data corresponding to the current cache access address, retrieve the data corresponding to the current cache access address from memory and return the data to the cache pipeline.
[0014] Secondly, this application also provides a method for processing cache access commands, the method comprising:
[0015] Obtain the cache access command to be processed, and the cache access address corresponding to the cache access command;
[0016] Enter cache access commands with the same cache access address into the same queue;
[0017] Within one clock cycle, a current cache access command is scheduled from multiple non-idle queues and entered into the cache pipeline. The current cache access command entering the cache pipeline is processed by the cache pipeline, and the response data corresponding to the current cache access command is returned.
[0018] If the current cache access queue corresponding to the current cache access command contains multiple cache access commands, and the response data is received, then obtain the cache access command to be scheduled that is processed after the current cache access command among the cache access commands contained in the current cache access queue.
[0019] Based on the command type of the cache access command to be scheduled, determine the next cache access command to be scheduled into the cache pipeline.
[0020] In one embodiment, determining the next cache access command to be scheduled into the cache pipeline based on the command type of the cache access command to be scheduled includes: if the command type is a read command, not sending the cache access command to be scheduled to the cache pipeline, and using the response data corresponding to the current cache access command as the response data corresponding to the cache access command to be scheduled.
[0021] In one embodiment, determining the next cache access command to be scheduled into the cache pipeline based on the command type of the cache access command to be scheduled includes: if the command type is a write command, sending the cache access command to be scheduled to the cache pipeline, obtaining the response data corresponding to the cache access command to be scheduled through the cache pipeline, and returning the response data corresponding to the cache access command to be scheduled.
[0022] In one embodiment, the method further includes: if the response data is not received, scheduling another cache access command into the cache pipeline from a non-idle queue other than the current cache access queue corresponding to the current cache access command.
[0023] In one embodiment, the method further includes: if the current cache access command is a miss command, then sending the current cache access command to the MSHR module through the cache pipeline; querying the write buffer through the MSHR module based on the current cache access address corresponding to the current cache access command; if the write buffer stores data corresponding to the current cache access address, then retrieving the data corresponding to the current cache access address from the write buffer and returning the data to the cache pipeline.
[0024] In one embodiment, after querying the write buffer, the method further includes: if the write buffer does not store data corresponding to the current cache access address, then retrieving the data corresponding to the current cache access address from memory and returning the data to the cache pipeline.
[0025] Thirdly, this application also provides a cache access command processing apparatus, the apparatus comprising:
[0026] The access command acquisition module is used to acquire the cache access command to be processed and the cache access address corresponding to the cache access command;
[0027] The command queue input module is used to input cache access commands with the same cache access address into the same queue;
[0028] The current command processing module is used to schedule a current cache access command from multiple non-idle queues into the cache pipeline within one clock cycle, process the current cache access command entering the cache pipeline through the cache pipeline, and return the response data corresponding to the current cache access command.
[0029] The scheduling command determination module is used to, when the current cache access queue corresponding to the current cache access command contains multiple cache access commands and the response data is received, obtain the cache access command to be scheduled that has a processing order after the current cache access command among the cache access commands contained in the current cache access queue.
[0030] The scheduling command processing module is used to determine the next cache access command to be scheduled into the cache pipeline based on the command type of the cache access command to be scheduled.
[0031] Fourthly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:
[0032] Obtain the cache access command to be processed, and the cache access address corresponding to the cache access command;
[0033] Enter cache access commands with the same cache access address into the same queue;
[0034] Within one clock cycle, a current cache access command is scheduled from multiple non-idle queues and entered into the cache pipeline. The current cache access command entering the cache pipeline is processed by the cache pipeline, and the response data corresponding to the current cache access command is returned.
[0035] If the current cache access queue corresponding to the current cache access command contains multiple cache access commands, and the response data is received, then obtain the cache access command to be scheduled that is processed after the current cache access command among the cache access commands contained in the current cache access queue.
[0036] Based on the command type of the cache access command to be scheduled, determine the next cache access command to be scheduled into the cache pipeline.
[0037] Fifthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:
[0038] Obtain the cache access command to be processed, and the cache access address corresponding to the cache access command;
[0039] Enter cache access commands with the same cache access address into the same queue;
[0040] Within one clock cycle, a current cache access command is scheduled from multiple non-idle queues and entered into the cache pipeline. The current cache access command entering the cache pipeline is processed by the cache pipeline, and the response data corresponding to the current cache access command is returned.
[0041] If the current cache access queue corresponding to the current cache access command contains multiple cache access commands, and the response data is received, then obtain the cache access command to be scheduled that is processed after the current cache access command among the cache access commands contained in the current cache access queue.
[0042] Based on the command type of the cache access command to be scheduled, determine the next cache access command to be scheduled into the cache pipeline.
[0043] Sixthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, performs the following steps:
[0044] Obtain the cache access command to be processed, and the cache access address corresponding to the cache access command;
[0045] Enter cache access commands with the same cache access address into the same queue;
[0046] Within one clock cycle, a current cache access command is scheduled from multiple non-idle queues and entered into the cache pipeline. The current cache access command entering the cache pipeline is processed by the cache pipeline, and the response data corresponding to the current cache access command is returned.
[0047] If the current cache access queue corresponding to the current cache access command contains multiple cache access commands, and the response data is received, then obtain the cache access command to be scheduled that is processed after the current cache access command among the cache access commands contained in the current cache access queue.
[0048] Based on the command type of the cache access command to be scheduled, determine the next cache access command to be scheduled into the cache pipeline.
[0049] The aforementioned cache access command processing system, method, apparatus, computer device, storage medium, and computer program product include: a cache queue management module and a cache pipeline; wherein, the cache queue management module is used to obtain cache access commands to be processed and the cache access addresses corresponding to the cache access commands; input cache access commands with the same cache access address into the same queue, and within one clock cycle, schedule one current cache access command from multiple non-idle queues into the cache pipeline; the cache pipeline is used to process the current cache access command entering the cache pipeline and return the response data corresponding to the current cache access command to the cache queue management module; the cache queue management module is used to, when the current cache access queue corresponding to the current cache access command contains multiple cache access commands and response data is received, obtain the cache access command to be scheduled from the cache access commands contained in the current cache access queue that has a processing order after the current cache access command; and determine the next cache access command to be scheduled into the cache pipeline based on the command type of the cache access command to be scheduled. This application utilizes a cache queue management module within a cache access command processing system to input cache access commands with the same cache access address into the same queue. When the cache pipeline processes cache access commands entering the pipeline, if the cache queue management module receives response data corresponding to a cache access command, it can determine the access commands in the queue whose processing order follows that cache access command. Based on the command type of that command, it determines the next access command to be scheduled into the cache pipeline. This achieves order preservation of commands with the same address through the cache queue management module. This method does not require suspending the execution of all subsequent access commands when an access command misses, thereby improving the processing efficiency of access commands. Attached Figure Description
[0050] Figure 1 This is a schematic diagram of the structure of a cache access command processing system in one embodiment;
[0051] Figure 2 This is a schematic diagram of the cache access command processing system in another embodiment;
[0052] Figure 3 This is a flowchart illustrating a cache access command processing method in one embodiment;
[0053] Figure 4 This is a schematic diagram of the process of handling missed commands through a cache pipeline in one embodiment;
[0054] Figure 5 A structural diagram of the cache in an application instance;
[0055] Figure 6A diagram illustrating the management of a cached request command queue in an application instance;
[0056] Figure 7a This is a timing diagram of cache processing for an application instance, illustrating the acceleration method.
[0057] Figure 7b This is a timing diagram of cache processing in a non-accelerated processing method in an application instance.
[0058] Figure 8a This is a schematic diagram illustrating the processing timing of queue scheduling in an application example.
[0059] Figure 8b This is a timing diagram illustrating the process of suspending commands at the same address in an application example.
[0060] Figure 9 This is a schematic diagram illustrating the interaction between the write buffer and the avoidance state save register in an application example.
[0061] Figure 10 This is a structural block diagram of a cache access command processing device in one embodiment;
[0062] Figure 11 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0064] In one embodiment, such as Figure 1 As shown, a cache access command processing system is provided, which may include: a cache queue management module 101 and a cache pipeline 102; wherein,
[0065] The cache queue management module 101 can be a module that manages cache access commands in the cache through queues. This module can manage queues in the form of linked lists, and each linked list can correspond to a cache access queue. A cache access command refers to a command used to access cached data stored in the cache. This command can cache the address of the cached data to be accessed, i.e., the cache access address. Specifically, when the cache queue management module 101 receives a cache access command that needs to be processed, it can determine the cache access address corresponding to each cache access command and input cache access commands with the same cache access address into the same cache access queue.
[0066] For example, the cache access commands that need to be processed may include command 0, command 1, command 2, and command 3. Command 0 and command 2 are access commands for cache access address 0, command 1 is an access command for cache access address 1, and command 3 is an access command for cache access address 2. The terminal can then divide the above cache access commands into three queues: queue 0 can cache command 0 and command 2, queue 1 can cache command 1, and queue 2 can cache command 3.
[0067] After obtaining the above multiple cache access queues, one of the access commands can be scheduled from the multiple non-idle queues, i.e. the queues with cached commands, within one clock cycle, and used as the current cache access command to enter the cache pipeline 102.
[0068] The cache pipeline 102 can be used to process the cache access commands entering it, obtain the corresponding response data, and return it to the cache queue management module 101. After the cache queue management module 101 schedules the current cache access command into the cache pipeline 102, the cache pipeline 102 can process the current cache access command entering it, obtain the corresponding response data of the current cache access command, and return it to the cache queue management module 101.
[0069] Finally, after receiving the response data returned by the cache pipeline 102 for the current cache access command, if the cache access queue corresponding to the current cache access command contains multiple cache access commands, the cache queue management module 101 can obtain the cache access command whose processing order is after the current cache access command from the multiple cache access commands in the current cache access queue, and use it as the cache access command to be scheduled. Furthermore, it can determine the next cache access command to be scheduled into the cache pipeline 102 based on the command type corresponding to the cache access command to be scheduled.
[0070] For example, the current cache access command can be command 0, and its corresponding queue caches command 0 and command 2. The processing order of command 2 is after command 0. If the cache queue management module 101 inputs command 0 into the cache pipeline 102 and receives the response data for command 0 returned by the cache pipeline 102, it can stop scheduling the commands in other queues and schedule command 2 as the cache access command to be scheduled. That is, by obtaining the command type corresponding to command 2, it can determine whether command 2 needs to be input into the cache pipeline 102.
[0071] The aforementioned cache access command processing system includes: a cache queue management module 101 and a cache pipeline 102; wherein, the cache queue management module 101 is used to obtain the cache access command to be processed and the cache access address corresponding to the cache access command; input cache access commands with the same cache access address into the same queue, and within one clock cycle, schedule one current cache access command from multiple non-idle queues into the cache pipeline 102; the cache pipeline 102 is used to process the current cache access command entering the cache pipeline and return the response data corresponding to the current cache access command to the cache queue management module; the cache queue management module 101 is further used to, when the current cache access queue corresponding to the current cache access command contains multiple cache access commands and response data is received, obtain the cache access command to be scheduled from the cache access commands contained in the current cache access queue that has a processing order after the current cache access command; and determine the next cache access command to be scheduled into the cache pipeline 102 according to the command type of the cache access command to be scheduled. This application utilizes a cache queue management module 101 within the cache access command processing system to input cache access commands with the same cache access address into the same queue. When the cache pipeline 102 processes cache access commands entering the cache pipeline, if the cache queue management module 101 receives response data corresponding to a certain cache access command, it can determine the access commands in the queue whose processing order follows that cache access command. Based on the command type of that command, it determines the next access command to be scheduled into the cache pipeline. Thus, the cache queue management module 101 achieves order preservation of commands with the same address. This method does not require suspending the execution of all subsequent access commands when an access command miss occurs, thereby improving the processing efficiency of access commands.
[0072] In one embodiment, the cache queue management module 101 is further configured to not send the cache access command to be scheduled to the cache pipeline 102 when the command type is a read command, and to use the response data corresponding to the current cache access command as the response data corresponding to the cache access command to be scheduled.
[0073] If the cache access command to be scheduled obtained by the cache queue management module 101 is a read command, since the read command does not change the data stored in the cache, the response data corresponding to the read command can be the same as the response data of the previous command. Therefore, the cache queue management module 101 can use the response data of the previous command of the cache access command to be scheduled, i.e., the current cache access command, as the response data of the cache access command to be scheduled. In this case, the cache queue management module 101 does not need to send the cache access command to be scheduled to the cache pipeline 102, and the cache pipeline 102 will process and obtain the above response data.
[0074] For example, if the current cache access command is command 0 and the cache access command to be scheduled is command 2, after the cache queue management module 101 obtains the response data of command 0, if command 2 is a read command, the cache queue management module 101 can directly use the response data corresponding to command 0 as the response data of command 2, so as not to schedule command 2 into the cache pipeline 102.
[0075] In this embodiment, if the cache access command to be scheduled is a read command, the response data corresponding to the current cache access command can be directly used as the response data of the cache access command to be scheduled. This eliminates the need to send the cache access command to be scheduled into the cache pipeline 102 for processing, thereby further improving the efficiency of cache access command processing.
[0076] In one embodiment, the cache queue management module 101 is further configured to send the cache access command to be scheduled to the cache pipeline 102 when the command type is a write command; the cache pipeline 102 is further configured to obtain the response data corresponding to the cache access command to be scheduled and return the response data corresponding to the cache access command to be scheduled to the cache queue management module 101.
[0077] If the cache access command to be scheduled is a write command, its corresponding response data may be different from the response data of the previous cache access command, i.e., the current cache access command. In order to ensure the accuracy of the response data corresponding to the write command, the cache queue management module 101 can input the cache access command to be scheduled into the cache pipeline 102, and the cache pipeline 102 will process the above write command, obtain the corresponding response data, and return it to the cache queue management module 101.
[0078] In this embodiment, if the cache access command to be scheduled is a write command, the cache queue management module 101 can send the cache access command to be scheduled into the cache pipeline 102, and the cache pipeline 102 will return the corresponding response data to ensure the accuracy of the response data corresponding to the command.
[0079] In one embodiment, the cache queue management module 101 is further configured to, in the absence of receiving response data, schedule another cache access command into the cache pipeline 102 from other non-idle queues besides the current cache access queue corresponding to the current cache access command.
[0080] Other non-idle queues refer to any of the multiple non-idle queues managed by the cache queue management module 101, excluding the current cache access queue. For example, if the current cache access queue is queue 0, then other non-idle queues could be queue 1 or queue 2. If the cache queue management module 101 does not receive the response data corresponding to the current cache access command, it can further schedule one of the other non-idle queues (i.e., other cache access commands) into the cache pipeline 102. This avoids the need to postpone all subsequent access commands from entering the cache pipeline 102 when the current cache access command misses, thereby further improving the processing efficiency of cache access commands.
[0081] In this embodiment, if the cache queue management module 101 does not receive response data, it can schedule another cache access command from a non-idle queue other than the current cache access queue to enter the cache pipeline 102. Since the other cache access command has a different cache access address than the current cache access queue, it can ensure that there are no commands with the same address in the cache pipeline. Therefore, when the current cache access command misses, it is not necessary to postpone all subsequent access commands from entering the cache pipeline 102, thereby further improving the processing efficiency of cache access commands.
[0082] In one embodiment, such as Figure 2 As shown, the cache access command processing system, in addition to the cache queue management module 201 and the cache pipeline 202, may also include the MSHR module 203 and the write buffer 204, wherein...
[0083] The cache pipeline 202 is further used to send the current cache access command to the MSHR module 203 if the current cache access command is a miss command; the MSHR module 203 is used to query the write buffer 204 based on the current cache access address corresponding to the current cache access command; if the write buffer 204 stores data that matches the current cache access address, the write buffer 204 retrieves the data that matches the current cache access address and returns the data to the cache pipeline 202.
[0084] In this embodiment, the cache access command processing system includes a cache queue management module 201 and a cache pipeline 202, as well as an MSHR module 203 and a write buffer 204. The cache pipeline 202 can communicate with the MSHR module 203, and the MSHR module 203 can communicate with the write buffer 204.
[0085] If, when processing the current cache access command, the cache pipeline 202 detects that the cache does not contain data corresponding to the access command, the current cache access command can be treated as a miss command. In this case, the cache pipeline 202 can further send the current cache access command to the MSHR module 203 to return the corresponding data to the cache pipeline 202.
[0086] After receiving the current cache access command, the MSHR module 203 can query the write buffer 204 based on the access address corresponding to the current cache access command, i.e., the current cache access address, to detect whether the write buffer 204 stores data that matches the current cache access address. For example, the current cache access address can be sent to a register in the write buffer 204 that stores address information. This register can store the address information corresponding to each piece of data stored in the write buffer 204. By judging whether the register stores address information that matches the current cache access address, it can be determined whether the write buffer 204 stores data that matches the current cache access address. If the data exists, the MSHR module 203 can obtain the data from the write buffer 204 and return it to the cache pipeline 202.
[0087] In this embodiment, when a cache access command misses in the cache pipeline 202, the MSHR module 203 can check whether data matching the current cache access address is stored in the write buffer 204 based on the cache access address of the cache access command. If so, the data can be directly obtained from the write buffer 204 and returned to the cache pipeline 202. Compared to the MSHR module 203 needing to read data directly from memory, reading data through the write buffer 204 improves the efficiency of data retrieval, thereby further improving the processing efficiency of cache access commands.
[0088] In addition, the MSHR module 203 is also used to retrieve the data corresponding to the current cache access address from memory and return the data to the cache pipeline 202 if the write buffer 204 does not store the data corresponding to the current cache access address.
[0089] If the write buffer 204 does not contain data that matches the current cache access address, in order to process the missed cache access command, in this embodiment, the MSHR module 203 can further obtain memory data that matches the cache access address from memory and return the data to the cache pipeline 202 to process the cache access command.
[0090] If the write buffer 204 does not contain data corresponding to the current cache access address, the MSHR module 203 in this embodiment can further obtain data corresponding to the current cache access address from memory and return it to the cache pipeline 202, thereby ensuring the feasibility of processing cache access commands that have missed.
[0091] In one embodiment, such as Figure 3 As shown, a cache access command processing method is provided, which can be applied to the cache and includes the following steps:
[0092] Step S301: Obtain the cache access command to be processed and the cache access address corresponding to the cache access command;
[0093] Step S302: Input cache access commands with the same cache access address into the same queue.
[0094] In this context, a cache access command refers to a command used to access cached data stored in the cache. This command may contain the address of the cached data to be accessed, i.e., the cache access address. In this embodiment, the cache may contain a cache queue management module that manages cache access commands through a queue. After the cache queue management module receives the cache access command that needs to be processed, it can further determine the cache access address corresponding to each cache access command and input cache access commands with the same cache access address into the same cache access queue.
[0095] Step S303: Within one clock cycle, schedule a current cache access command from multiple non-idle queues into the cache pipeline, process the current cache access command entering the cache pipeline through the cache pipeline, and return the response data corresponding to the current cache access command.
[0096] The cache pipeline can be used to process cached access commands entering it. After obtaining multiple cached access queues in step S302, within one clock cycle, one access command can be scheduled from the multiple non-idle queues (i.e., queues containing cached commands) as the current cached access command and enter the cache pipeline. The cache pipeline can then process the current cached access command, obtain the corresponding response data for the current cached access command, and return it to the cache queue management module.
[0097] Step S304: If the current cache access queue corresponding to the current cache access command contains multiple cache access commands and response data is received, obtain the cache access command to be scheduled that is processed after the current cache access command among the cache access commands contained in the current cache access queue.
[0098] Step S305: Determine the next cache access command to be scheduled into the cache pipeline based on the command type of the cache access command to be scheduled.
[0099] Finally, after receiving the response data from the cache pipeline for the current cache access command, if the cache access queue corresponding to the current cache access command contains multiple cache access commands, then the next cache access command in the current cache access queue that is processed after the current cache access command can be obtained as the cache access command to be scheduled. Furthermore, the next cache access command to be scheduled into the cache pipeline can be determined based on the command type corresponding to the cache access command to be scheduled.
[0100] In the above cache access command processing method, the following steps are taken: First, obtain the cache access command to be processed and its corresponding cache access address. Second, input cache access commands with the same cache access address into the same queue. Third, within one clock cycle, schedule a current cache access command from multiple non-idle queues into the cache pipeline. Process the current cache access command in the cache pipeline and return the corresponding response data. Fourth, if the current cache access queue corresponding to the current cache access command contains multiple cache access commands and response data has been received, obtain the cache access command to be scheduled that is processed after the current cache access command in the current cache access queue. Fifth, determine the next cache access command to be scheduled into the cache pipeline based on the command type of the cache access command to be scheduled. This application achieves order preservation of commands with the same cached access address by inputting them into the same queue. When the cache pipeline processes the cached access commands entering the cache pipeline, if a response data corresponding to a certain cached access command is received, the access commands in the queue whose processing order follows that cached access command can be determined. Based on the command type of that command, the next access command to be scheduled into the cache pipeline is determined, thereby achieving order preservation of commands with the same address. This method does not require suspending the execution of all subsequent access commands when an access command miss occurs, thus improving the processing efficiency of access commands.
[0101] In one embodiment, step S305 may further include: when the command type is a read command, not sending the cache access command to be scheduled to the cache pipeline, and using the response data corresponding to the current cache access command as the response data corresponding to the cache access command to be scheduled.
[0102] If the cache access command to be scheduled is a read command, since the read command does not change the data stored in the cache, the response data corresponding to the read command can be the same as the response data of the previous command. Therefore, the response data of the previous command, i.e. the current cache access command, can be used as the response data of the cache access command to be scheduled. There is no need to send the cache access command to be scheduled to the cache pipeline for processing to obtain the above response data.
[0103] In this embodiment, if the cache access command to be scheduled is a read command, the response data corresponding to the current cache access command can be directly used as the response data of the cache access command to be scheduled. This eliminates the need to send the cache access command to be scheduled into the cache pipeline for processing, thereby further improving the efficiency of cache access command processing.
[0104] In one embodiment, step S305 may further include: when the command type is a write command, sending the cache access command to be scheduled to the cache pipeline, obtaining the response data corresponding to the cache access command to be scheduled through the cache pipeline, and returning the response data corresponding to the cache access command to be scheduled.
[0105] If the cache access command to be scheduled is a write command, its corresponding response data may differ from the response data of the previous cache access command, i.e., the current cache access command. In order to ensure the accuracy of the response data corresponding to the write command, the cache access command to be scheduled can be input into the cache pipeline, which will then process the write command and return the corresponding response data.
[0106] In this embodiment, if the cache access command to be scheduled is a write command, the cache access command to be scheduled can be sent to the cache pipeline, and the cache pipeline will return the corresponding response data to ensure the accuracy of the response data corresponding to the command.
[0107] In one embodiment, the cache access command processing method may further include: if no response data is received, scheduling another cache access command into the cache pipeline from a non-idle queue other than the current cache access queue corresponding to the current cache access command.
[0108] Other non-idle queues refer to any one of the multiple non-idle queues other than the current cache access queue. If the response data corresponding to the current cache access command returned by the cache pipeline is not received, a cache access command from one of the remaining non-idle queues (i.e., other cache access commands) can be scheduled into the cache pipeline. This avoids having to postpone all subsequent access commands from entering the cache pipeline when the current cache access command misses, thereby further improving the processing efficiency of cache access commands.
[0109] In this embodiment, if no response data is received, another cache access command can be scheduled into the cache pipeline from other non-idle queues besides the current cache access queue. Since the other cache access command has a different cache access address than the current cache access queue, it can be guaranteed that there are no commands with the same address in the cache pipeline. Therefore, when the current cache access command misses, it is not necessary to postpone all subsequent access commands from entering the cache pipeline, thereby further improving the processing efficiency of cache access commands.
[0110] In one embodiment, such as Figure 4 As shown, the cache access command processing method may further include:
[0111] Step S401: If the current cache access command is a missed command, the current cache access command is sent to the MSHR module through the cache pipeline.
[0112] The MSHR module can be a module in the cache used to handle cached access commands that have failed. If the cache pipeline detects that the cache does not contain data corresponding to the current cached access command while processing it, the current cached access command can be treated as a failed command. In this case, the cache pipeline can further send the current cached access command to the MSHR module, which will then return the corresponding data to the cache pipeline.
[0113] Step S402: The MSHR module queries the write buffer based on the current cache access address corresponding to the current cache access command;
[0114] Step S403: If the write buffer contains data that corresponds to the current cache access address, then retrieve the data that corresponds to the current cache access address from the write buffer and return the data to the cache pipeline.
[0115] The write buffer is a buffer area in the cache used to store write-through data and write-back data. After the MSHR module receives the current cache access command, it can query the write buffer based on the access address corresponding to the current cache access command, i.e., the current cache access address, to check whether the write buffer stores data that matches the current cache access address. For example, the current cache access address can be sent to a register in the write buffer that stores address information. This register can store the address information corresponding to each piece of data stored in the write buffer. By judging whether the register stores address information that matches the current cache access address, it can be determined whether the write buffer stores data that matches the current cache access address. If the data exists, the MSHR module can obtain the data from the write buffer and return it to the cache pipeline.
[0116] In this embodiment, when a cache access command misses in the cache pipeline, the MSHR module can check whether data matching the current cache access address is stored in the write buffer based on the cache access address of the command. If so, the data can be directly retrieved from the write buffer and returned to the cache pipeline. Compared to the MSHR module directly reading data from memory, reading data through the write buffer improves data retrieval efficiency, thereby further improving the processing efficiency of cache access commands.
[0117] Additionally, after step S402, the method may further include: if the write buffer does not contain data corresponding to the current cache access address, then retrieve the data corresponding to the current cache access address from memory and return the data to the cache pipeline.
[0118] If the write buffer does not contain data matching the current cache access address, in order to process the missed cache access command, in this embodiment, the MSHR module can further obtain memory data matching the cache access address from memory and return the data to the cache pipeline to process the cache access command.
[0119] If the write buffer does not contain data corresponding to the current cache access address, the MSHR module in this embodiment can further obtain data corresponding to the current cache access address from memory and return it to the cache pipeline, thereby ensuring the feasibility of processing cache access commands that have missed.
[0120] In one application example, a method for preserving the order of same-address access commands in a cache is also provided. The structure diagram of this cache is as follows: Figure 5As shown, by managing the queue of input cached request commands and performing a lookup of the write buffer similar to Content-Addressable Memory (CAM), the problem of maintaining the order of commands at the same address is solved without sacrificing cache access performance. The specific implementation process is as follows:
[0121] The diagram illustrating the cached request command queue management is as follows: Figure 6 As shown in the diagram. Assume the supported number of cache misses is 64. Access commands with the same address are placed in the same queue, while access commands with different addresses are placed in different queues. When all 64 input access commands are at different addresses, 64 queues are required. To conserve resources, the 64 queues share a command buffer of depth 64 and are managed using linked lists, with each queue corresponding to one linked list. Each loop schedules one command from the non-free links of the 64 linked lists, dequeuing it and sending it to the cache pipeline for processing. No commands from the same linked list are scheduled until the previous command entering the pipeline has been processed. This ensures that there are no commands with the same address in the pipeline, thus avoiding the timing issues introduced by searching the MSHR (Maximum Storage Register) for commands with the same address in the pipeline.
[0122] Meanwhile, to improve the efficiency of cache access, commands within the same linked list can be processed more quickly, such as... Figure 7a As shown. Linked list 0 contains 5 access commands at the same address. Commands 0-2 are read commands, command 3 is a write command, and command 4 is a read command. Using an accelerated processing method, after command 0 reads data from the pipeline, subsequent read commands in the linked list (commands 1-2) are no longer sent to the pipeline; they directly use the data read back by the first command. Write command 3 needs to be sent to the pipeline for further processing. Command 4 directly uses the write data from command 3 as its read data and is no longer sent to the pipeline for processing. This is done using... Figure 7a The acceleration method shown is, compared to not using acceleration, i.e. Figure 7b The processing method shown saves latency from 3 read accesses.
[0123] When the 64 cache misses are distributed across different queues, the overall scheduling result of this scheme is as follows: Figure 8a As shown. When the number of commands for non-same addresses can cover the latency of missed read accesses, this method is performance-comparable to handling 64 access commands for non-same addresses. This is in contrast to the method of directly suspending the handling of commands for the same address. Figure 8b Compared to the method shown, the access efficiency of this application instance can be greatly improved.
[0124] Introducing a write buffer can improve write performance in write-through operations and also enhance the performance of evicting dirty lines during write-back operations. However, with a write buffer, when a memory access miss occurs, if a write-back strategy is used and the replacement line is dirty, after evicting the dirty line to the write buffer, subsequent read miss commands may have the same address as data in the write buffer. In this case, the avoidance status saver sends read requests via the advanced microcontroller bus, and the write buffer sends write requests via the advanced microcontroller bus. The processing of both on the bus is completely parallel, and the bus cannot guarantee the order in which they arrive at downstream memory. This scenario is a same-address ordering problem that the entry queue scheduling method cannot solve. Figure 9 As shown, to address the order preservation issue in this scenario, a content-addressable memory (CAM)-like storage mechanism is introduced into the write buffer to store all write-complete commands (assuming the cache outputs 16 bus write-complete commands, then 16 write commands need to be recorded). When a read miss command is scheduled from the avoidance state save register, the write buffer is first checked. If data with the same address exists in the write buffer, the data is directly read and returned to the cache request interface, without sending a read request to downstream memory. If data with the same address does not exist in the write buffer, a read request needs to be initiated to downstream memory via the bus. This approach not only solves the same-address order preservation problem but also reduces the frequency of access to downstream memory, improving access efficiency.
[0125] In the above application examples, by adding a queue scheduling mechanism for cache entry points and introducing a lookup mechanism similar to Content Addressable Memory (CAM) in the write buffer, the order preservation problem of missed commands at the same address in non-blocking caches can be efficiently solved without affecting cache access performance. At the same time, timing problems caused by introducing overly complex logic into the cache pipeline are avoided.
[0126] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0127] Based on the same inventive concept, this application also provides a cache access command processing apparatus for implementing the cache access command processing method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more cache access command processing apparatus embodiments provided below can be found in the limitations of the cache access command processing method described above, and will not be repeated here.
[0128] In one embodiment, such as Figure 10 As shown, a cache access command processing device is provided, including: an access command acquisition module 1001, a command queue input module 1002, a current command processing module 1003, a scheduling command determination module 1004, and a scheduling command processing module 1005, wherein:
[0129] The access command acquisition module 1001 is used to acquire the cache access command to be processed and the cache access address corresponding to the cache access command;
[0130] The command queue input module 1002 is used to input cache access commands with the same cache access address into the same queue;
[0131] The current command processing module 1003 is used to schedule a current cache access command from multiple non-idle queues into the cache pipeline within one clock cycle, process the current cache access command entering the cache pipeline through the cache pipeline, and return the response data corresponding to the current cache access command.
[0132] The scheduling command determination module 1004 is used to obtain the cache access command to be scheduled that is processed after the current cache access command when the current cache access queue corresponding to the current cache access command contains multiple cache access commands and response data is received.
[0133] The scheduling command processing module 1005 is used to determine the next cache access command to be scheduled into the cache pipeline based on the command type of the cache access command to be scheduled.
[0134] In one embodiment, the scheduling command processing module 1005 is further configured to, when the command type is a read command, not send the cache access command to be scheduled to the cache pipeline, and use the response data corresponding to the current cache access command as the response data corresponding to the cache access command to be scheduled.
[0135] In one embodiment, the scheduling command processing module 1005 is further configured to send the cache access command to be scheduled to the cache pipeline when the command type is a write command, obtain the response data corresponding to the cache access command to be scheduled through the cache pipeline, and return the response data corresponding to the cache access command to be scheduled.
[0136] In one embodiment, the current command processing module 1003 is further configured to, in the absence of receiving response data, schedule another cache access command into the cache pipeline from a non-idle queue other than the current cache access queue corresponding to the current cache access command.
[0137] In one embodiment, the cache access command processing apparatus further includes: a miss command processing module, configured to, if the current cache access command is a miss command, send the current cache access command to the MSHR module through the cache pipeline; query the write buffer through the MSHR module based on the current cache access address corresponding to the current cache access command; if the write buffer stores data corresponding to the current cache access address, retrieve the data corresponding to the current cache access address from the write buffer and return the data to the cache pipeline.
[0138] In one embodiment, the miss command processing module is further configured to, if the write buffer does not store data corresponding to the current cache access address, retrieve the data corresponding to the current cache access address from memory and return the data to the cache pipeline.
[0139] Each module in the aforementioned cache access command processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device in software form, so that the processor can invoke and execute the operations corresponding to each module.
[0140] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 11 As shown, the computer device includes a processor, memory, and a communication interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a cache access command processing method.
[0141] Those skilled in the art will understand that Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0142] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.
[0143] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.
[0144] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.
[0145] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.
[0146] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0147] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0148] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A cache access command processing system, characterized in that, include: The cache queue management module, and the cache pipeline; among them, The cache queue management module is used to obtain the cache access command to be processed and the cache access address corresponding to the cache access command; input the cache access commands with the same cache access address into the same queue; and within one clock cycle, schedule a current cache access command from multiple non-idle queues into the cache pipeline. The cache pipeline is used to process the current cache access command entering the cache pipeline and return the response data corresponding to the current cache access command to the cache queue management module. The cache queue management module is used to, when the current cache access queue corresponding to the current cache access command contains multiple cache access commands and the response data is received, obtain the cache access command to be scheduled that is processed after the current cache access command among the cache access commands contained in the current cache access queue; and determine the next cache access command to be scheduled into the cache pipeline based on the command type of the cache access command to be scheduled. The cache queue management module is further configured to, when the command type is a read command, not send the cache access command to be scheduled to the cache pipeline, and use the response data corresponding to the current cache access command as the response data corresponding to the cache access command to be scheduled; and when the command type is a write command, send the cache access command to be scheduled to the cache pipeline.
2. The system according to claim 1, characterized in that, The cache pipeline is further configured to, when the command type is a write command, obtain the response data corresponding to the cache access command to be scheduled, and return the response data corresponding to the cache access command to be scheduled to the cache queue management module.
3. The system according to claim 1 or 2, characterized in that, The cache queue management module is also used to schedule another cache access command into the cache pipeline from other non-idle queues besides the current cache access queue corresponding to the current cache access command, if the response data is not received.
4. The system according to claim 1, characterized in that, The system also includes: an MSHR module and a write buffer; wherein... The cache pipeline is further configured to send the current cache access command to the MSHR module if the current cache access command is a miss command. The MSHR module is used to query the write buffer based on the current cache access address corresponding to the current cache access command; if the write buffer stores data that matches the current cache access address, the data that matches the current cache access address is retrieved from the write buffer and returned to the cache pipeline.
5. The system according to claim 4, characterized in that, The MSHR module is further configured to, if the write buffer does not store data corresponding to the current cache access address, retrieve the data corresponding to the current cache access address from memory and return the data to the cache pipeline.
6. A method for processing cache access commands, characterized in that, The method includes: Obtain the cache access command to be processed, and the cache access address corresponding to the cache access command; Enter cache access commands with the same cache access address into the same queue; Within one clock cycle, a current cache access command is scheduled from multiple non-idle queues and entered into the cache pipeline. The current cache access command entering the cache pipeline is processed by the cache pipeline, and the response data corresponding to the current cache access command is returned. If the current cache access queue corresponding to the current cache access command contains multiple cache access commands, and the response data is received, then obtain the cache access command to be scheduled that is processed after the current cache access command among the cache access commands contained in the current cache access queue. Based on the command type of the cache access command to be scheduled, determine the next cache access command to be scheduled into the cache pipeline; including: if the command type is a read command, not sending the cache access command to be scheduled to the cache pipeline, and using the response data corresponding to the current cache access command as the response data corresponding to the cache access command to be scheduled; if the command type is a write command, sending the cache access command to be scheduled to the cache pipeline.
7. The method according to claim 6, characterized in that, When the command type is a write command, after sending the scheduled cache access command to the cache pipeline, the process further includes: The response data corresponding to the scheduled cache access command is obtained through the cache pipeline, and the response data corresponding to the scheduled cache access command is returned.
8. The method according to claim 6 or 7, characterized in that, The method further includes: If the response data is not received, another cache access command is scheduled into the cache pipeline from a non-idle queue other than the current cache access queue corresponding to the current cache access command.
9. The method according to claim 6, characterized in that, The method further includes: If the current cache access command is a miss command, then the current cache access command is sent to the MSHR module through the cache pipeline; The MSHR module queries the write buffer based on the current cache access address corresponding to the current cache access command. If the write buffer contains data that corresponds to the current cache access address, then the data corresponding to the current cache access address is retrieved from the write buffer and returned to the cache pipeline.
10. The method according to claim 9, characterized in that, Following the query write buffer, the following is also included: If the write buffer does not contain data corresponding to the current cache access address, then the data corresponding to the current cache access address is retrieved from memory and returned to the cache pipeline.
11. A cache access command processing apparatus, characterized in that, The device includes: The access command acquisition module is used to acquire the cache access command to be processed and the cache access address corresponding to the cache access command; The command queue input module is used to input cache access commands with the same cache access address into the same queue; The current command processing module is used to schedule a current cache access command from multiple non-idle queues into the cache pipeline within one clock cycle, process the current cache access command entering the cache pipeline through the cache pipeline, and return the response data corresponding to the current cache access command. The scheduling command determination module is used to, when the current cache access queue corresponding to the current cache access command contains multiple cache access commands and the response data is received, obtain the cache access command to be scheduled that has a processing order after the current cache access command among the cache access commands contained in the current cache access queue. The scheduling command processing module is used to determine the next cache access command to be scheduled into the cache pipeline based on the command type of the cache access command to be scheduled; further, it is used to not send the cache access command to be scheduled to the cache pipeline when the command type is a read command, and to use the response data corresponding to the current cache access command as the response data corresponding to the cache access command to be scheduled; and to send the cache access command to be scheduled to the cache pipeline when the command type is a write command.
12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 6 to 10.
13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 6 to 10.
14. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 6 to 10.