Failure localization method applied to FPGA

Abstract

The present invention discloses a failure location method applied to FPGA. The method determines the code block range for failure analysis based on the underlying physical netlist and original code of the chip under test; performs secondary wiring operation on the underlying circuit corresponding to the code block range, and leads the intermediate node data of multiple fabric circuits of the underlying circuit to the outside of the chip; analyzes the underlying physical netlist according to the intermediate node data, generates multiple test sets in units of code blocks, and each test set includes multiple test patterns; performs actual testing on the chip under test according to the multiple test sets, and collects failure information; locates the physical location of the chip failure according to the failure information. The technical solution of the present invention achieves the reduction of the failure range and the precise location of the failure by retaining the original physical netlist and reproducing the failure.

Description

Technical Field

[0001] The present invention relates to the technical field of chip failure location, and in particular to a failure location method applied to FPGA. Background Art

[0002] Chips may fail at every stage from production to application. Once the complex digital circuits running on the logic chip fail, the chip resources used are relatively large (the number of basic resources involved ranges from thousands to tens of thousands), resulting in the pattern required for positioning to continue to increase with the complexity of user code and the increase in chip integration. The manpower, material and financial resources consumed during this period and the time spent on the entire positioning process will also increase accordingly.

[0003] There are usually two existing technical solutions: one is to split the failure pattern, continuously refine and disassemble the complex design into small simple functional modules to try to reproduce the failure phenomenon, and then continue to split the functional modules that reproduce the failure phenomenon, and repeat the above process until the root cause of the failure is found. The other is to use the software's online debugging tool to extract the signal instantiated by the user code to the outside of the chip and observe its data flow for analysis.

[0004] The location of logic chips is difficult because the chips themselves lack sufficient DFT circuits. Whether it is splitting the failure project or using online debugging tools, an inevitable problem will be encountered, that is, regenerating the physical netlist. Even if it is just a slight change in the code, or even just changing the compilation environment, during software synthesis, this small change will cause the software algorithm to decide to use other resources and other structures to implement the previous functions. Therefore, in the actual failure location process, the following problems will occur: Figure 2 The situation shown is that the failure cannot be reproduced, and thus the failure location work cannot be performed. Summary of the invention

[0005] The present invention provides a failure location method applied to FPGA, which reduces the failure range and accurately locates the failure position by retaining the original physical netlist and reproducing the failure.

[0006] An embodiment of the present invention provides a failure location method applied to FPGA, comprising the following steps:

[0007] Determine the scope of the code block used for failure analysis based on the underlying physical netlist and original code of the chip under test;

[0008] Performing secondary wiring operation on the bottom layer circuit corresponding to the code block range, and leading the intermediate node data of multiple fabric circuits of the bottom layer circuit out of the chip;

[0009] Analyze the underlying physical netlist according to the intermediate node data to generate multiple test sets in units of code blocks, each test set including multiple test patterns;

[0010] Performing actual tests on the chip under test according to the multiple test sets, and collecting failure information;

[0011] The physical location of the chip failure is located according to the failure information.

[0012] Furthermore, the failed fabric circuit is located according to the failure information corresponding to the test pattern, and then the physical position of the corresponding chip failure is located according to the failed fabric circuit.

[0013] Further, performing a secondary wiring operation on the underlying circuit corresponding to the code block range includes the following steps:

[0014] Get the idle output IO resources and idle fabric circuits of the chip under test;

[0015] For a first code block in the code block range, analyzing resources used by the first code block in the underlying physical netlist one by one to obtain one or more resource output ports of the first code block;

[0016] Each time, a resource output port of the first code block is connected to the idle fabric circuit, and then connected to the idle output IO resource through the idle fabric circuit.

[0017] Further, the underlying physical netlist is analyzed according to the intermediate node data to generate multiple test sets in units of code blocks, specifically:

[0018] The automated program analyzes the underlying physical netlist according to the intermediate node data to obtain the connection relationship of the fabric circuit;

[0019] The expected input value and expected output value of each fabric circuit are obtained through circuit simulation, and multiple test sets based on code blocks are generated.

[0020] Furthermore, each test set includes 1 to 999 test patterns.

[0021] Furthermore, the process of performing actual testing on failed chips according to the multiple test sets is an automated testing process.

[0022] The embodiments of the present invention have the following beneficial effects:

[0023] The present invention provides a failure location method applied to FPGA. Under the premise of keeping the original physical netlist synthesized by the user unchanged, the method uses other resources in the chip to bypass the intermediate nodes of the original circuit. The bypass transmits the signals of the intermediate nodes to the outside of the chip. By analyzing these signals, the failure range can be narrowed again in the later stage of failure analysis. Since the physical netlist of the user is kept, there is no need to worry about the failure situation not being able to be reproduced, and the intercepted signals of the intermediate nodes will also truthfully reflect the internal data of the circuit. Therefore, when the failure phenomenon occurs, it can be quickly located which code block has caused the data flow error. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a flow chart of a failure location method in the prior art;

[0025] Figure 2 It is a flowchart of a failure location method applied to FPGA provided by an embodiment of the present invention;

[0026] Figure 3 It is a schematic diagram of the structure of the overall circuit of a failure location method applied to FPGA provided by an embodiment of the present invention;

[0027] Figure 4 It is a structural schematic diagram of a single code block of a failure localization method applied to FPGA provided by an embodiment of the present invention;

[0028] Figure 5 It is a secondary wiring diagram of a failure location method applied to FPGA provided by an embodiment of the present invention;

[0029] Figure 6 It is a schematic diagram of the structure of a test set of a failure localization method applied to FPGA provided by an embodiment of the present invention;

[0030] Figure 7 It is a schematic diagram of constructing a test set for a single code block in a failure localization method applied to FPGA provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] like Figure 1 As shown, a failure location method applied to FPGA provided by an embodiment of the present invention includes the following steps:

[0033] Step S101: Determine the code block range for failure analysis based on the underlying physical netlist and original code of the chip under test. Specifically, the underlying physical netlist and original code of the chip under test are input into the failure analysis program, and the code block range for failure analysis is defined by the user.

[0034] like Figure 3 As shown in the figure, the overall circuit is composed of a series of block modules (i.e., code blocks). Each block module exchanges and processes data, and finally realizes the functions expected by the user code. Therefore, for early analysis, whether it is splitting the code or using online debugging tools, the minimum functional subset can only stay at the level of these block modules. However, from the perspective of the underlying chip design, Figure 4 As shown, the essence of each block module lies in the organic combination of countless LUT resources, DFF resources and routing resources, and the organic combination of LUT resources, DFF resources and routing resources is fabric circuit / fabric resource. Based on this principle, the accuracy of failure location can be improved. In the past, only the failure of a block module could be located. However, no matter how simple the function of this block module is, it will at least contain multiple fabric circuits, and the real cause of failure may be that one or more of these fabric circuits are physically damaged, and there is a mapping relationship between these fabric circuits and the physical circuits on the actual chip. Therefore, by re-analyzing and re-locating these resources, it is possible to directly lock to an exact position in the chip; then other personnel can conduct further analysis on the located failure position.

[0035] Step S102: performing a secondary wiring operation on the bottom layer circuit corresponding to the code block range, and leading the intermediate node data of multiple fabric circuits of the bottom layer circuit out of the chip.

[0036] Performing secondary wiring operation on the underlying circuit corresponding to the code block range includes the following steps:

[0037] Get the idle output IO resources and idle fabric circuits of the chip under test;

[0038] For a first code block in the code block range, analyzing resources used by the first code block in the underlying physical netlist one by one to obtain one or more resource output ports of the first code block;

[0039] Each time, a resource output port of the first code block is connected to the idle fabric circuit, and then connected to the idle output IO resource through the idle fabric circuit.

[0040] like Figure 5 As shown, since there are some idle wiring resources in the chip that can be called, the bottom-level circuit synthesized by the user's code (i.e., the code block range for failure analysis) can be rewired, and the intermediate node data of multiple fabric circuits in the bottom-level circuit can be led out of the chip for analysis (i.e., off-chip analysis) through secondary wiring to create one or more bypasses without destroying the original circuit settings. The bypass is another data output path led from the module used in the original physical netlist through idle fabric circuits and idle io resources, and the intermediate node data is output to the outside of the chip for analysis through idle io resources.

[0041] Step S103: Analyze the underlying physical netlist according to the intermediate node data to generate multiple test sets in units of code blocks, each test set including multiple test patterns. Specifically, an automated program analyzes the underlying physical netlist according to the intermediate node data to obtain the connection relationship of the fabric circuit;

[0042] The expected input value and expected output value of each fabric circuit are obtained through circuit simulation, and multiple test sets based on code blocks are generated.

[0043] like Figure 6 As shown, the expected input value and expected output value of each fabric circuit are obtained through circuit simulation, and multiple test sets are generated in units of code blocks. Each test set includes 1 to 999 test patterns.

[0044] Step S104: Perform actual testing on the tested chips according to the multiple test sets and collect failure information. The process of performing actual testing on failed chips according to the multiple test sets is automated testing.

[0045] Step S105: locate the physical location of the chip failure according to the failure information. Specifically, locate the failed fabric circuit according to the failure information corresponding to the test pattern, and then locate the corresponding physical location of the chip failure according to the failed fabric circuit.

[0046] If the underlying circuit synthesized by the user's code is relatively complex, it can be handled by an automated program. The connection relationship of the fabric circuit is determined by analyzing the underlying physical netlist, and the expected input value and expected output value of each fabric circuit are obtained through circuit simulation, and multiple test sets are generated. Then, the failed chip is automatically tested in an assembly line manner according to the multiple test sets. Since the expected input value and expected output value have been obtained through simulation in advance, once the simulated value and the measured value are different, the program will automatically retain the fail information of the corresponding pattern, and the user can directly locate the failed fabric circuit through the fail information, and at the same time locate the physical location of the chip failure.

[0047] like Figure 7 As shown, if the user has located a certain block module or a failure of a certain code block by splitting the project in the early stage, the scope of the automation program can be adjusted to analyze only the circuit synthesized by the specific block module or specific code, and generate a test pattern set only for the specific block module. This can avoid the situation where the entire project needs to be analyzed even though the scope of the problem point is known, greatly reducing repeated and meaningless analysis processes and speeding up analysis efficiency.

[0048] The terms involved in the embodiments of the present invention are explained as follows:

[0049] Logic chip: refers to a chip used to implement user digital logic, whose function is usually determined by user programming.

[0050] Failure localization: When a logic chip cannot perform its function, it is considered to have failed. The process of narrowing the scope of the failure is called failure localization.

[0051] Physical netlist: A file generated by a software algorithm after processing user code. It can be narrowly understood as a circuit constructed to implement the code function.

[0052] FPGA: (Field Programmable Gate Array) field programmable gate array.

[0053] Pattern: chip test vector.

[0054] DFT: (Design For Test) refers to the insertion of various hardware logics used to improve the testability of the chip (including controllability and observability) during the original chip design stage. Through this part of the logic, test vectors are generated to achieve the purpose of testing large-scale chips.

[0055] LUT: (Look Up Table) refers to the smallest unit used to implement basic logic operations in a logic chip.

[0056] DFF: (D type flip-flop) refers to a trigger of a clock signal.

[0057] Routing: The chip's wiring resources are used to transmit signals.

[0058] Fabric: The underlying infrastructure of a logic chip.

[0059] The advantage of this patent is that, under the premise of keeping the original physical netlist synthesized by the user unchanged, other resources in the chip are used to bypass the intermediate nodes of the original circuit. This bypass will transmit the signals of the intermediate nodes to the outside of the chip. By analyzing these signals, the failure range can be narrowed again in the later stage of failure analysis. Since the user's physical netlist is retained, there is no need to worry about the failure situation not being able to be reproduced, and the intercepted signals of the intermediate nodes will also truthfully reflect the internal data of the circuit. Therefore, when a failure occurs, it can be seen which data flow is caused by the error.

[0060] Exemplarily, the computer program may be divided into one or more modules, which are stored in the memory and executed by the processor to implement the present invention. The one or more modules may be a series of computer program instruction segments capable of implementing specific functions, which are used to describe the execution process of the computer program in the terminal device.

[0061] The terminal device may be a computing device such as a desktop computer, a notebook, a PDA, a cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0062] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the terminal device, and uses various interfaces and lines to connect various parts of the entire terminal device.

[0063] The memory can be used to store the computer program and / or module, and the processor realizes various functions of the terminal device by running or executing the computer program and / or module stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0064] Wherein, if the module / unit integrated in the terminal device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium (i.e., the above-mentioned readable storage medium). Based on such an understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium, etc.

[0065] It should be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the accompanying drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art may understand and implement it without paying any creative effort.

[0066] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

[0067] Those skilled in the art can understand that all or part of the processes in the above embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes in the above embodiments. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

Claims

1. A failure location method applied to FPGA, characterized in that: The following steps are involved: Determine the scope of the code block used for failure analysis based on the underlying physical netlist and original code of the chip under test; Perform secondary wiring operation on the bottom layer circuit corresponding to the code block range, and lead the intermediate node data of multiple fabric circuits of the bottom layer circuit to the outside of the chip; wherein, obtain the idle output IO resources and idle fabric circuits of the chip under test; for the first code block in the code block range, analyze the resources used by the first code block in the bottom layer physical netlist one by one, and obtain one or more resource output ports of the first code block; connect one resource output port of the first code block to the idle fabric circuit each time, and connect to the idle output IO resource through the idle fabric circuit; Analyze the underlying physical netlist according to the intermediate node data to generate multiple test sets in units of code blocks, each test set including multiple test patterns; Performing actual tests on the chip under test according to the multiple test sets, and collecting failure information; The physical location of the chip failure is located according to the failure information.

2. The failure location method applied to FPGA according to claim 1, characterized in that: The failed fabric circuit is located according to the failure information corresponding to the test pattern, and then the physical position of the corresponding chip failure is located according to the failed fabric circuit.

3. The failure location method applied to FPGA according to claim 1, characterized in that: The underlying physical netlist is analyzed according to the intermediate node data to generate multiple test sets in units of code blocks, specifically: The automated program analyzes the underlying physical netlist according to the intermediate node data to obtain the connection relationship of the fabric circuit; The expected input value and expected output value of each fabric circuit are obtained through circuit simulation, and multiple test sets based on code blocks are generated.

4. The failure location method applied to FPGA according to claim 3, characterized in that: Each test set contains 1 to 999 test patterns.

5. The failure location method applied to FPGA according to any one of claims 1 to 4, characterized in that: The process of performing actual testing on failed chips according to the multiple test sets is an automated testing process.

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