A method for automatic extraction and analysis of schematic power supply topology

Abstract

The present invention discloses a method for automatically extracting and analyzing a schematic power supply topology structure. The extraction method includes: obtaining the characteristic information of the schematic diagram to be analyzed, and based on the characteristic information of the schematic diagram, obtaining the core devices in the schematic diagram and the analysis sequence of the core devices, where the core devices are power-consuming devices; analyzing each core device one by one based on the analysis sequence of the core devices to obtain all the first power networks between the core devices and the power supply input endpoints and the first connection sequence of all the first power networks; forming the power supply topology structure of the schematic diagram based on all the power networks and the connection sequence of all the power networks obtained after analyzing the core devices. The present invention effectively solves the problems of low efficiency and missed inspection in manual inspection of schematic power supply design caused by the increasing complexity of circuit hardware design.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and particularly to a method for automatically extracting and analyzing a schematic power supply topology structure. Background Art

[0002] With the increasing complexity of circuit hardware design, the schematic power supply design becomes more and more complex. A clear power supply structure tree check and power supply design check are becoming increasingly important in the schematic design stage.

[0003] Currently, the schematic power supply design often relies on manual inspection, but the manual review efficiency is low, it is not comprehensive enough in related inspections that require calculations, and an effective inspection report cannot be formed. Summary of the Invention

[0004] In view of the problems existing in the above-mentioned prior art, the present invention provides a method for automatically extracting and analyzing a schematic power supply topology structure, which realizes automatically and efficiently generating a power supply topology structure and improves the inspection efficiency of the schematic power supply topology structure.

[0005] In a first aspect, a method for automatically extracting a schematic power supply topology structure is provided, including:

[0006] Obtaining the characteristic information of the schematic to be analyzed, and based on the characteristic information of the schematic, obtaining the core devices in the schematic and the analysis order of the core devices, where the core devices are powered devices;

[0007] Analyzing each core device one by one based on the core device analysis order. Analyzing the core device includes: taking the core device as the end node, and iteratively searching upward according to the connection relationship of the power supply-related pins of different devices and the connection relationship between the power supply-related pins of the device and the power supply network until the power supply input endpoint is obtained, and obtaining all the first power supply networks between the core device and the power supply input endpoint and the first connection order of all the first power supply networks. The power supply-related pins include pins representing power input or power output, and the first connection order of all the first power supply networks represents the input-output direction between the power supply networks;

[0008] Forming the power supply topology structure of the schematic based on all the power supply networks and the connection order of all the power supply networks obtained after analyzing the core devices.

[0009] In some embodiments, analyzing the core device includes:

[0010] a) Obtaining the first power supply network or the first device connected to the power supply-related pins of the core device;

[0011] b) Obtaining the second device connected through the power supply-related pins among all the devices connected to the first power supply network;

[0012] c) Obtain all the first power networks or the first devices connected to the power-related pins of the first device and the second device;

[0013] d) Repeat steps b) and c) until the power supply input terminal is obtained;

[0014] e) Obtain the first power network between the core device and the power supply input terminal and determine the first connection sequence between the power networks.

[0015] In some embodiments, after obtaining all the first power networks between the core device and the power supply input terminal and the first connection sequence of all the first power networks, it further includes:

[0016] Based on all the obtained first power networks, iteratively search downward from the first power network until the terminal device. The downward iterative search process includes: obtaining the second power network or the third device connected to the first power network through non-power-related pins, and iteratively searching according to the pin connection relationship until the terminal device, obtaining all the second power networks between the first power network and the terminal device and determining the first connection sequence or the second connection sequence. The non-power-related pins include enable control pins, and the second connection sequence includes the power-on sequence under the action of the enable control pins.

[0017] In some embodiments, the obtaining of the core device and the core device analysis sequence in the schematic diagram based on the characteristic information of the schematic diagram includes:

[0018] Based on the characteristic information of the schematic diagram, obtain the core device according to the device type, device name, device value, and the number of device pins, and sort them in descending order according to the number of pins of the core device.

[0019] In a second aspect, a method for automatically analyzing the power topology structure of a schematic diagram is provided, including:

[0020] Based on the power topology structure of the schematic diagram, start the analysis from the power supply input terminal, and respectively analyze the rationality of the design circuit of the power supply input terminal, the electrical parameters of the power supply terminal and the power receiving terminal, the design circuit of the power network associated capacitor, and the configuration of the power network associated capacitor.

[0021] In some embodiments, the analysis of the rationality of the design circuit of the power supply input terminal includes:

[0022] Check and analyze the protection circuit of the power supply input terminal according to the first preset constraint rules. The first constraint rules include the electrical parameter specifications of the circuit protection device, the number of filter capacitors, the type and specifications of the filter capacitors.

[0023] In some embodiments, the analysis of the rationality of the electrical parameters of the power supply end and the power receiving end includes:

[0024] Determine whether the power supply output and input voltage and current match;

[0025] According to the voltage and current of each power supply network, calculate the recommended value of the layout design line width parameter between power supply networks according to the temperature rise limit and rules;

[0026] According to the device information library, calculate the power consumption of all devices in each power supply network, and analyze the recommended value of the layout design line width parameter in the power supply network.

[0027] In some embodiments, the analysis of the rationality of the power supply network associated capacitor design circuit includes:

[0028] Analyze whether the capacitor configuration at the input and output ends of the devices in the power supply network conforms to the preset constraint rules according to the device type and characteristics. The preset constraint rules for the capacitor configuration include constraints on the capacitance value, quantity, and type of the capacitor;

[0029] The analysis of the rationality of the power supply network associated capacitor configuration includes:

[0030] According to the enabling order between the power supply network and / or power attribute devices and the connected capacitor devices, calculate and analyze the capacitor charge and discharge process parameters, and determine whether the capacitor charge and discharge process parameters conform to the preset constraint rules. The capacitor charge and discharge process parameters include the charging time, power-on delay, and power-on transient current of the capacitor when powered on.

[0031] In some embodiments, the device information library dynamically adds and updates device information based on the newly added schematic diagram to be analyzed.

[0032] In some embodiments, the above-mentioned automatic analysis method for the schematic power supply topology structure further includes:

[0033] Based on the summary and collation of the circuit schematic analysis results, obtain a power supply schematic design analysis report and suggestions, and at the same time automatically add prompts and marks in the power supply schematic diagram.

[0034] A method for automatically extracting and analyzing the schematic power supply topology structure of the present invention has the following beneficial effects:

[0035] The present invention starts from the analysis of the core device, based on the power supply related pins as search conditions, and iteratively searches each power supply network or device until no new power supply network or device can be obtained, that is, the search reaches the power supply input endpoint. Then, the power supply network between the core device and the power supply input endpoint and the connection sequence between the power supply networks can be obtained, thereby forming a power supply network topology structure diagram. By connecting the devices, power supply networks, and devices in the power supply network in the schematic diagram in series according to the voltage direction through the connection relationship of the power supply related pins of the devices, a power supply network topology structure diagram is generated. The power supply network topology structure diagram generation method has a small calculation amount, high efficiency, and good accuracy, effectively solving the problems of low efficiency and missed detection in the power supply design inspection of the schematic diagram caused by the increasing complexity of the circuit hardware design. Description of the Drawings

[0036] Figure 1 is a flowchart of the method for automatically extracting the power supply topology structure of the schematic diagram in the embodiment of the present application;

[0037] Figure 2 is a circuit schematic diagram of the power supply related pins of the core device connecting to the power supply network;

[0038] Figure 3 is a circuit schematic diagram of the power supply network connecting multiple devices;

[0039] Figure 4 is a schematic diagram for describing the device information of device Chip1;

[0040] Figure 5 is a schematic diagram of the network interconnection information of NET_V1 network. Detailed Implementation Manner

[0041] Aiming at the problems of the increasing complexity of circuit schematic design and the low efficiency of manual inspection of the standardization of power supply design in the circuit schematic diagram in the prior art, the embodiment of the present application provides a method for automatically extracting the power supply topology structure of the schematic diagram. The extraction method includes:

[0042] Step 1, obtain the characteristic information of the schematic diagram to be analyzed. Based on the characteristic information of the schematic diagram, obtain the core device and the core device analysis sequence in the schematic diagram, and the core device is the powered device;

[0043] Step 2: Analyze each core device one by one based on the core device analysis order. Analyzing the core device includes: taking the core device as the end node, and iteratively searching upward according to the connection relationships of the power-related pins of different devices and the connection relationships between the power-related pins of the device and the power network until the power supply input endpoint is obtained, so as to acquire all the first power networks between the core device and the power supply input endpoint and the first connection order of all the first power networks. The power-related pins include the pins representing power input or power output, and the first connection order of all the first power networks represents the input-output directions between the power networks.

[0044] Step 3: Based on all the power networks and the connection order of all the power networks obtained after analyzing the core devices, form the power topology structure of the schematic diagram.

[0045] Specifically, when opening the schematic diagram to be analyzed in the schematic diagram design software, the netlist file and the device BOM information list of the schematic diagram can be obtained. Among them, taking Cadence as an example, the netlist file exported by Orcad contains 3 files:

[0046] pstchip.dat: It is the schematic diagram device information, including device name, value, pin name, pin number, and corresponding package.

[0047] pstnet.dat: It is the connection information between devices, including network name, connected device number, device corresponding pin name, and pin number.

[0048] pstxprt.dat: It is the device package information, including device number and corresponding package name.

[0049] Among them, for the device BOM information list, it includes the information of all devices in the schematic diagram, including device number, model, value, coordinates in the schematic diagram, number of pins, etc.

[0050] The characteristic information of the above schematic diagram includes: the number of pages and structure of the schematic diagram, the netlist exported from the schematic diagram, the list of all device attributes, and the schematic diagram version record, etc.

[0051] In one implementation, first open the EDA software and the schematic diagram to be analyzed through a scripting language, and automatically export the schematic diagram netlist file, component attribute information, and schematic diagram file structure information. The netlist file contains the characteristics of the devices in the schematic diagram, device package information, and network interconnections between devices. The component characteristics include device number, device name, pin number, and pin name, as Figure 4 shown. The schematic diagram network interconnection information includes all signal network names and the numbers, corresponding pin numbers, and pin names of all devices connected within a network, as Figure 5As shown

[0052] Starting from the core device as the analysis starting point, based on the power supply related pins as the search conditions, iteratively searching each power supply network or device until no new power supply network or device can be obtained, that is, the search reaches the power supply input endpoint, and then the power supply network between the core device and the power supply input endpoint and the connection sequence between the power supply networks can be obtained, thereby forming a power supply network topology structure diagram. In this application, the automatic formation of the power supply network topology structure diagram is realized, avoiding the low efficiency and missed inspection of manual inspection, and improving the inspection efficiency of the rationality of the schematic power supply design.

[0053] Among them, the power supply related pins represent the pins for power supply input or power supply output. Generally, the names of the power supply related pins have corresponding naming rules. For example, for chip devices with control attributes, the names of their power supply related pins include VDD, VCC, VREF, etc. For chip devices with power supply attributes, the names of their power supply related pins include power supply input VIN, output VOUT, etc.;

[0054] In the embodiment of this application, the devices, power supply networks, and devices in the power supply networks in the schematic diagram are strung together according to the voltage direction through the connection relationship of the power supply related pins of the devices, and then a power supply network topology structure diagram is generated. The method for generating the power supply network topology structure diagram has a small calculation amount, high efficiency, and good accuracy, effectively solving the problems of low inspection efficiency and missed inspection in the schematic power supply design brought about by the increasing complexity of the circuit hardware design.

[0055] The analysis of the core device in step 2 above includes the following steps:

[0056] a) Obtain the first power supply network or the first device connected to the power supply related pins of the core device;

[0057] b) Obtain the second device connected through the power supply related pins among all the devices connected to the first power supply network;

[0058] c) Obtain all the first power supply networks or the first devices connected to the power supply related pins of the first device and the second device;

[0059] d) Repeat steps b) and c) until the power supply input end is obtained;

[0060] e) Obtain the first power supply network between the core device and the power supply input end and determine the first connection sequence between the power supply networks.

[0061] In one case, in step a), it may be to analyze the power network connected to the power input pin and the power output pin of the core device. Considering that the core device is a power receiving end device and generally does not have a power output pin, in the embodiments of the present application, when iteratively searching upward with the core device as the analysis origin, the power input pin of the core device can be used to further search upward.

[0062] It can be understood that in steps b)-d), it may be: for the first power network, further analyze the devices and connection pins connected in the first power network through step b) to obtain the devices connected through the power-related pins, which are recorded as the second devices; further, through step c), obtain all the first power networks or the first devices connected to the power-related pins of the second devices for the second devices, and then enter step d): repeat steps b) and c) until the power supply input end is obtained;

[0063] In steps b)-d), it may be: for the first device, obtain all the first power networks or the first devices connected to the power-related pins of the first device through step c), and then enter step d): repeat steps b) and c) until the power supply input end is obtained;

[0064] Take Figure 2 and Figure 3 The circuit schematic diagram shown as an example to specifically illustrate the above steps a)-e):

[0065] Suppose Figure 2 Chip1 in is used as the core device. Chip1 is respectively connected to the networks NET_V1, NET_V11, and NET_Va through the VDD_1, VDD_11, and VDD_a pins. Taking the NET_V11 network as an example to illustrate the subsequent steps, by obtaining the network interconnection information of NET_V11, it can be obtained that the devices connected to the NET_V11 network are the magnetic bead FB and the device Chip1. Furthermore, through the pin connection relationship of the magnetic bead FB, it can be obtained that the magnetic bead FB is connected to NET_V1. By obtaining the network interconnection information of NET_V1, such as Figure 5From the network interconnection information of NET_V1 shown, it can be obtained that network NET_V1 is connected to many different devices and their corresponding pin numbers and names. By filtering out the OUT_1 pin of device U1 according to the pin name, since device U1 is a device with a power supply attribute, device U1 is determined as the output device of NET_V1. Then, according to all the pin connection relationships of device U1, it can be obtained that it has a pin IN_1 at pin number 1. Then, continue to iteratively search upward according to all the networks or devices connected to the IN_1 pin until the power supply input terminal interface J1 and the voltage NET_V0 connected to J1 are searched. Thus, the iterative search of Chip1, NET_V11 network, NET_V1,..., interface J1 is completed and their connection order is determined. It can be understood that the attribute types of all devices in the circuit schematic diagram can be obtained from the data information exported by the schematic design software. For example, Chip1 is a control attribute device, and U1 and U2 are power supply attribute devices, where U1 and U2 are voltage conversion devices. For U1, the input voltage is greater than the output voltage, and for U2, the input voltage is less than the output voltage. Through the above steps a)-e), the voltage directions of most power supplies can be obtained.

[0066] It can be understood that during the process of steps a)-d), the first power network between the core device and the power supply input terminal, as well as the power supply attribute devices and other attribute devices between the core device and the power supply input terminal, can be obtained. At the same time, the connection order between the first power networks, the pin connection relationships of the power supply attribute devices, and the pin connection relationships of the other attribute devices are determined. Thus, when analyzing the schematic power topology structure based on the extracted schematic power topology structure, it can be analyzed whether the design of the power network meets the constraint conditions, and at the same time, it can be analyzed whether the input and output terminal configurations of the power supply attribute devices in the schematic diagram and the circuit designs of the other attribute devices meet the constraint conditions.

[0067] Further, in the above step 2, after obtaining all the first power networks between the core device and the power supply input terminal point and the first connection order of all the first power networks, it further includes:

[0068] Based on all the obtained first power networks, iteratively search downward from the first power network until the terminal device. The downward iterative search process includes: obtaining the second power network or the third device connected by the first power network through non-power-related pins, and iteratively searching according to the pin connection relationships until the terminal device, obtaining all the second power networks between the first power network and the terminal device and determining the first connection order or the second connection order. The non-power-related pins include enable control pins, and the second connection order includes the power-on order under the action of the enable control pins.

[0069] It can be understood that the first power network is obtained by starting from the core device and iteratively searching upward through the connection relationships of the power-related pins of the device. Further, for each first power network, the power networks or devices that were not searched during the upward iterative search are obtained by iteratively searching downward through the non-power-related pin connection relationships. This downward iterative search process further improves the schematic power topology, and can obtain the power networks or devices that were not searched during the upward iterative search, as well as the devices or power networks with enable control relationships, thereby obtaining the conversion and enable control relationships between the power networks.

[0070] Taking Figure 2 and 3 the circuit schematic shown as an example for illustration, for the NET_V1 network obtained based on the core device Chip1, based on the network interconnection information of this NET_V1 network (as shown in Figure 5 ), it can be obtained that the network NET_V1 is also connected to Ra_EN. Furthermore, through the pin connection relationship of Ra_EN, it can be obtained that NET_V1 is connected to the enable EN pin of U2. After judging the power-on sequence, the power networks or devices obtained from the downward iterative search process are used to supplement and improve the power network topology obtained previously based on the upward iterative search.

[0071] Specifically, in the above step 1, based on the characteristic information of the schematic diagram, the core device and the core device analysis order in the schematic diagram are obtained, including:

[0072] Based on the characteristic information of the schematic diagram, the core device is obtained according to the device type, device name, device value, and the number of device pins, and sorted from largest to smallest according to the number of pins of the core device.

[0073] Specifically, taking an embodiment as an example for illustration, it can be a device of the main control chip type, that is, a control attribute device, as the core device, such as chips of types FPGA, ARM, DSP, etc. At the same time, based on the characteristic information of the schematic diagram, the core device is screened through the device name and device value. Processor chips produced by different manufacturers have corresponding naming rules. For example, a control device with a name starting with "STM******" is an ARM chip, and a chip with a name starting with "EP4C******" is a Cyclone IV series chip of Altera Corporation (Altera has been acquired by Intel).

[0074] In addition, considering that the pins of main control chips such as FPGA and ARM are significantly more than those of other devices, the number of device pins is used as a basis for core device analysis. The core device can be obtained through comprehensive analysis of the device type, device name, device value, and the number of device pins.

[0075] Of course, the core device is not limited to the above control devices. The core device is a key or main device in the schematic diagram, such as an amplifier circuit, a logic or timer chip in a digital circuit control circuit, etc. Specifically, the core device can be obtained through corresponding analysis according to the actual schematic diagram.

[0076] Take Figure 3 the schematic diagram as an example for illustration. According to the attribute information of the devices, it can be known that U1 and U2 are power supply attribute devices, and Chip is a control attribute device. Sort according to the number of pins of the components in the feature information to obtain the order of Chip1 - U2 - U1. Combining the device attributes and the sorting results, it is determined that Chip1 is the core electrical appliance device.

[0077] Based on the circuit schematic power topology structure extracted by the above - mentioned schematic diagram power topology structure automatic extraction method, check the standardization and rationality of the power supply design in the schematic diagram. A schematic diagram power topology structure automatic analysis method provided by an embodiment of the present application includes:

[0078] Based on the power topology structure of the schematic diagram and a preset device information library, start the analysis from the power supply input endpoint, and respectively analyze the rationality of the design circuit of the power supply input endpoint, the electrical parameters of the power supply terminal and the power - receiving terminal, the design circuit of the power network associated capacitor, and the configuration of the power network associated capacitor.

[0079] Among them, the preset device information library includes:

[0080] (1) The characteristic power input and output pin numbers, names, voltage ranges, maximum currents, and power consumptions of each component and the power - related pins.

[0081] (2) The capacitors recommended for use in the power input and output pins of the components, such as filtering and bypass capacitors, the number and types of capacitors;

[0082] (3) For components without recommended values, according to the voltage and current, user - defined setting rules are set.

[0083] This device information library needs to be established in advance and is an important part in the analysis process. This device information library dynamically adds and updates device information based on the newly added schematic diagram to be analyzed, realizing the continuous expansion of the data in the device information library.

[0084] Specifically, the above - mentioned analysis of the rationality of the design circuit of the power supply input endpoint includes:

[0085] Check and analyze the protection circuit of the power supply input endpoint according to the first preset constraint rule. The first constraint rule includes the electrical parameter specifications of the circuit protection device, the number of filtering capacitors, the type and specifications of the filtering capacitors.

[0086] Among them, the circuit protection device can be an ESD, overcurrent protection, overvoltage protection and other electronic devices. The electrical parameter specifications of the circuit protection device in the first constraint rule can be the working voltage specification of the ESD device, the voltage and current specification of the fuse, etc.

[0087] It can be understood that the circuit schematic diagram to be analyzed includes at least one power supply input endpoint, and may include multiple power supply input endpoints. For the protection circuit of each power supply input endpoint, check and analyze whether the working voltage specification of the ESD device, the voltage and current specification of the fuse, the number of filter capacitors, the type and specification of the filter capacitors meet the preset constraint rules.

[0088] The above analysis of the rationality of the electrical parameters of the power supply end and the power receiving end includes:

[0089] Judge whether the power supply output and input voltage and current match;

[0090] According to the voltage and current of each power supply network, calculate the recommended value of the layout design line width parameter between the power supply networks according to the temperature rise limit and rules;

[0091] According to the device information library, calculate the power consumption of all devices in each power supply network, and analyze the recommended value of the layout design line width parameter in the power supply network.

[0092] Among them, judging whether the power supply output and input voltage and current match includes comparing the power supply voltage parameter and the device pin connected to the power supply in the circuit schematic diagram with the pin voltage information in the device information library to judge whether the device pin voltage parameter meets the preset constraint rules. The power supply voltage parameter in the circuit schematic diagram is determined according to the marked voltage in the power supply name in the circuit schematic diagram. The marked voltage of the power supply name in the circuit schematic diagram is, for example, VCC_5V, VDD_1V8, etc.;

[0093] The above analysis of the rationality of the power supply network associated capacitor design circuit includes:

[0094] Analyze whether the input and output terminal capacitor configuration of the devices in the power supply network meets the preset constraint rules according to the device type and characteristics. The preset constraint rules of the capacitor configuration include the constraints on the capacitance value, quantity and type of the capacitor;

[0095] The above analysis of the rationality of the power supply network associated capacitor configuration includes:

[0096] According to the enabling sequence between the power supply network and / or the power supply attribute devices and the connected capacitor devices, calculate and analyze the capacitor charge and discharge process parameters and judge whether the capacitor charge and discharge process parameters meet the preset constraint rules. The capacitor charge and discharge process parameters include the charging time, power-on delay, and power-on transient current of the capacitor when powered on.

[0097] Specifically, for the devices in the power supply network, according to the recommended values of the input and output of the components in the device information library, it is determined whether the capacitance value, quantity, and type of the capacitors at the input and output ends of each component meet the preset constraint rules. For different power supply networks, according to the enabling control relationship and power-on sequence of the devices therein, the charging time, power-on delay, change in power-on transient current, and transient current at the input end of the capacitor device during power-on are calculated and analyzed, and the places with excessive power-on transient current are recorded and marked.

[0098] Taking Figure 2 and 3 the circuit schematic diagram as an example, the automatic analysis method for the schematic power supply topology structure is schematically described. The analysis process includes:

[0099] According to the power supply network structure, it can be known that J1 is the input end of the circuit power supply. From the power supply structure, it can be known that NET_V0 is the power supply input end of NET_V1 and NET_V2. According to the power consumption of Chip1 and the power supply input requirements, as well as the power device efficiency information and input-output relationship between U1 and U2, the total current required for the input of NET_V0 is calculated, and a safety margin is reserved during the calculation. Read the device characteristic information of D1, FU1, and C0, and determine whether the voltage and current meet the working requirements of the NET_V0 power supply.

[0100] According to the power supply circuit structure information, starting from NET_V0 and retrieving backward to NET_V0_0, NET_V0_0 is connected to the devices C00, C00n, C1, C1n, and U1. Calculate and determine whether the capacitance quantity, type, and capacitance value of the network NET_V0_0 meet the requirements according to the input capacitance requirements of U1 in the device information. According to the voltage of NET_V0_0 and the maximum current calculated above, calculate the transient current change rate and power-on charging time during power-on according to the capacitor charging formula, and give the power-on delay parameter.

[0101] According to the above analysis method, the input and output of all power supply network-related devices in the power supply structure are calculated and analyzed to determine whether the filtering and bypass capacitors are within a reasonable range, and for the power supply networks with large currents, calculate and determine the appropriate PCB line width as a reference for PCB wiring.

[0102] Based on the above power supply design analysis results, an analysis report can be automatically generated in the embodiments of the present application. Specifically, it includes: summarizing and organizing based on the analysis results of the circuit schematic diagram to obtain the power supply schematic diagram design analysis report and suggestions, and at the same time automatically adding prompts and marks in the power supply schematic diagram. Taking Orcad as an example, it supports Tcl / TK scripts and can place marks through scripts.

[0103] Specifically, based on the analysis results of the schematic power supply topology structure, the analysis results of the power supply structure and the calculation analysis results of the power supply network are summarized. For important items in the calculation analysis, such as the lack of power supply protection, capacitance quantity and value problems, and trace width, etc., marks and problem reminder information are added near the corresponding network labels and devices in the schematic EDA software through a script program; at the same time, the circuit structure diagram and the circuit analysis report are output, and the above calculation results and PCB power supply wiring reference information are given in the report.

[0104] The present invention is not limited to the above specific embodiments. Those of ordinary skill in the art starting from the above concepts and making various transformations without creative labor fall within the protection scope of the present invention.

Claims

1. An automatic extraction method for the power supply topology structure of a schematic diagram, characterized in that, it includes: Obtain the characteristic information of the schematic diagram to be analyzed. Based on the characteristic information of the schematic diagram, obtain the core devices in the schematic diagram and the analysis order of the core devices. The core devices are power-receiving devices; Analyze each core device one by one based on the core device analysis order. Analyzing the core device includes: taking the core device as the end node, and iteratively searching upward according to the connection relationship of the power supply-related pins of different devices and the connection relationship between the power supply-related pins of the device and the power supply network until the power supply input endpoint is obtained, and obtaining all the first power supply networks between the core device and the power supply input endpoint and the first connection order of all the first power supply networks. The power supply-related pins include pins representing power input or power output, and the first connection order of all the first power supply networks represents the input-output direction between the power supply networks; Form the power supply topology structure of the schematic diagram based on all the power supply networks and the connection order of all the power supply networks obtained after analyzing the core devices; After obtaining all the first power supply networks between the core device and the power supply input endpoint and the first connection order of all the first power supply networks, it further includes: based on all the obtained first power supply networks, iteratively search downward from the first power supply network until the end device. The downward iterative search process includes: obtaining the second power supply network or the third device connected by the first power supply network through non-power supply-related pins, and iteratively searching according to the pin connection relationship until the end device, obtaining all the second power supply networks between the first power supply network and the end device and determining the first connection order or the second connection order. The non-power supply-related pins include enable control pins, and the second connection order includes the power-on order under the action of the enable control pins.

2. The automatic extraction method for the power supply topology structure of a schematic diagram according to claim 1, characterized in that, the analysis of the core device includes: a) Obtain the first power supply network or the first device connected to the power supply-related pins of the core device; b) Obtain the second device connected through the power supply-related pins among all the devices connected to the first power supply network; c) Obtain all the first power supply networks or the first devices connected to the power supply-related pins of the first device and the second device; d) Repeat steps b) and c) until the power supply input end is obtained; e) Obtain the first power supply network between the core device and the power supply input end and determine the first connection order between the power supply networks.

3. The automatic extraction method for the power supply topology structure of a schematic diagram according to claim 1, characterized in that, obtaining the core devices in the schematic diagram and the analysis order of the core devices based on the characteristic information of the schematic diagram includes: Based on the characteristic information of the schematic diagram, obtain the core devices according to the device type, device name, device value, and the number of device pins, and sort them in descending order according to the number of pins of the core devices.

4. The automatic analysis method for the power supply topology structure of a schematic diagram according to any one of claims 1-3, characterized in that, it includes: Based on the power supply topology of the schematic diagram, starting from the input endpoint of the power supply, analyze the designed circuit of the input endpoint of the power supply, the electrical parameters of the power supply terminal and the power receiving terminal, the designed circuit of the associated capacitor of the power network, and the rationality of the configuration of the associated capacitor of the power network.

5. A method for automatically analyzing the power supply topology of a schematic diagram according to claim 4, characterized in that, The analysis of the rationality of the designed circuit of the input endpoint of the power supply includes: Checking and analyzing the protection circuit of the input endpoint of the power supply according to the first preset constraint rule, and the first preset constraint rule includes the electrical parameter specifications of the circuit protection device, the number of filter capacitors, the type and specifications of the filter capacitors.

6. A method for automatically analyzing the power supply topology of a schematic diagram according to claim 4, characterized in that, The analysis of the rationality of the electrical parameters of the power supply terminal and the power receiving terminal includes: Judging whether the output and input voltage and current of the power supply match; According to the voltage and current of each power network, calculate the recommended value of the layout design line width parameter between power networks according to the temperature rise limit and rules; According to the device information library, calculate the power consumption of all devices in each power network and analyze the recommended value of the layout design line width parameter in the power network.

7. A method for automatically analyzing the power supply topology of a schematic diagram according to claim 4, characterized in that, The analysis of the rationality of the designed circuit of the associated capacitor of the power network includes: Analyzing whether the input and output terminal capacitor configuration of the devices in the power network conforms to the preset constraint rule according to the device type and characteristics, and the preset constraint rule of the capacitor configuration includes the constraints on the capacitance value, quantity and type of the capacitor; The analysis of the rationality of the configuration of the associated capacitor of the power network includes: According to the enabling sequence between the power network and / or the power attribute devices and the connected capacitor devices, calculate and analyze the capacitor charge and discharge process parameters and judge whether the capacitor charge and discharge process parameters conform to the preset constraint rule, and the capacitor charge and discharge process parameters include the charging time, power-on delay and power-on transient current of the capacitor when powered on.

8. A method for automatically analyzing the power supply topology of a schematic diagram according to claim 6, characterized in that, The device information library dynamically adds and updates device information based on the newly added schematic diagram to be analyzed.

9. A method for automatically analyzing the power supply topology of a schematic diagram according to claim 4, characterized in that, It also includes: Summarize and organize the analysis results based on the circuit schematic diagram to obtain a power supply schematic diagram design analysis report and suggestions, and at the same time automatically add prompts and marks in the power supply schematic diagram.

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