Flexible DLL (delay-locked loop) calibration

Abstract

A memory device performs DLL (delay-locked loop) calibration according to a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions of the memory device. The memory device includes input / output (I / O) interface circuitry and a delay-locked loop (DLL) circuit coupled to control I / O timing of the I / O interface. A control circuit of the memory device selectively enables and disables DLL calibration according to the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to stop or refrain from DLL calibration operations.

Description

Technical Field

[0001] This application is a divisional application of application number 201680069525.8, entitled "Flexible DLL (Delay-Locked Loop) Calibration". The description generally relates to input / output (I / O) circuits, and more specifically to flexible DLL (Delay-Locked Loop) calibration for I / O circuits.

[0002] Copyright Notice / License

[0003] This patent document may contain copyrighted material. The copyright holder does not object to any person reproducing this patent document or patent disclosure when it appears in the Patent and Trademark Office's patent files or records, but otherwise reserves all copyright rights whatsoever. This copyright notice applies to all data as described below and in the accompanying drawings, and also to any software described below: Copyright © 2015, Intel Corporation. All rights reserved. Background Technology

[0004] Synchronous memories perform access operations based on a clock signal that serves as a timing reference to achieve data transfer and reception with a known relationship to the reference. I / O (input / output) interfaces used for synchronous interconnects typically employ DLLs (delay-locked loops) to maintain a known relationship with the reference timing. The DLL circuitry adjusts the timing of internal signals to align with the timing reference. Synchronous operation can improve signaling between connected devices. However, when the DLL is active, DLL operation traditionally involves continuous tracking of the reference timing signal, which consumes significant power. DLL tracking can be referred to as DLL calibration, where phase control is calibrated to an external reference timing. The power consumption of continuous DLL calibration can consume a significant portion of the total power budget in systems designed to operate in low-power modes.

[0005] It will be understood that signal transfer speeds can be lower or higher depending on the application of the memory device. Lower power applications typically use lower signal transfer speeds. DLL timing compensation adjustments affect the timing characteristics of the data "eye," which identifies the threshold for signal transfers made by the memory device. Continuous DLL tracking maintains a narrow margin on the data eye. Lower speed signal transfers can tolerate higher variations in the data eye margin and may not require DLL calibration in some implementations. Higher speed signal transfers may require continuous DLL calibration to ensure the data eye margin required for higher speed operation. Traditionally, manufacturers and system designers either make DLL calibration continuous while the DLL is active or exclude it altogether. Attached Figure Description

[0006] The following description includes a discussion of the accompanying drawings, which illustrate examples of implementations of the invention. The drawings should be understood as examples, not as limitations. As used herein, references to one or more “embodiments” are to be understood as describing specific features, structures, and / or characteristics included in at least one implementation of the invention. Therefore, phrases such as “in one embodiment” or “in an alternative embodiment” appearing herein describe various embodiments and implementations of the invention and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0007] Figure 1 This is a block diagram of one embodiment of a system in which memory device I / O phase control can be selectively calibrated.

[0008] Figure 2 This is a block diagram of one embodiment of a system in which the memory device includes a configurable DLL calibration mode.

[0009] Figure 3 This is a block diagram of one embodiment of a system in which a DLL calibration mode for memory devices can be applied.

[0010] Figure 4 This is a block diagram of one embodiment of a mode register used to selectively enable DLL calibration mode.

[0011] Figure 5 This is a flowchart of one embodiment of the process for applying selective DLL calibration.

[0012] Figure 6 This is a block diagram of one embodiment of a computing system that can implement DLL calibration mode.

[0013] Figure 7 This is a block diagram of one embodiment of a mobile device that can implement DLL calibration mode.

[0014] Certain details and implementations follow, including descriptions of some or all of the figures that may depict the embodiments described below, as well as discussions of other potential embodiments or implementations of the inventive concepts presented herein. Detailed Implementation

[0015] As described herein, the memory device performs DLL (Delay-Locked Loop) calibration according to a DLL calibration mode configured for the memory device. Different DLL calibration modes provide flexibility in enabling and disabling DLL calibration to achieve a balance between power consumption and timing margin for I / O (input / output) signal transmission. The DLL calibration mode can include a mode for always-on operation as in conventional systems, and can also allow for periods when DLL calibration is disabled.

[0016] The host controller can configure the calibration mode based on the operating conditions of the memory device. The memory device includes input / output (I / O) interface circuitry and a delay-locked loop (DLL) circuitry coupled to control the I / O timing of the I / O interface. The memory device's control circuitry selectively enables and disables DLL calibration according to the DLL calibration mode. When selectively enabled, DLL calibration can operate at time intervals identified by the DLL calibration mode, and when selectively disabled, DLL calibration operation is stopped. Therefore, the system can provide flexible DLL calibration for different operating conditions.

[0017] References to memory devices can be applied to different memory types. In one embodiment, a reference to a memory device can refer to a non-volatile memory device whose state is determined even if power to the device is interrupted. In one embodiment, the non-volatile memory device is a block-addressable memory device, such as NAND or NOR technology. Therefore, the memory device can also include non-volatile devices such as three-dimensional crosspoint (3D Xpoint or 3DXP) memory devices, other byte-addressable non-volatile memory devices, or memory devices using chalcogenide phase change materials. In one embodiment, the memory device can be or include multi-threshold NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) incorporating memristor technology, or spin-transfer torque (STT)-MRAM, or a combination of any of the above, or other memory. Therefore, references to memory devices can refer to non-volatile memory devices that support random access and / or are configured for synchronous I / O.

[0018] In one embodiment, "memory device" refers to volatile memory technology. Volatile memory is memory whose state (and therefore the data stored thereon) is indeterminate if power to the device is interrupted. Dynamically volatile memory requires refreshing the data stored in the device to maintain its state. An example of dynamically volatile memory includes DRAM (Dynamic Random Access Memory), or some variants such as Synchronous DRAM (SDRAM). The memory subsystem described herein is compatible with many memory technologies and their derivatives or extensions based on such specifications, such as DDR4 (DDR version 4, the initial specification published by JEDEC in September 2012), DDR4E (DDR version 4, an extension, currently under discussion by JEDEC), LPDDR3 (Low Power DDR version 3, JESD209-3B, JEDEC in August 2013), LPDDR4 (Low Power Double Data Rate (LPDDR) version 4, JESD209-4, originally published by JEDEC in August 2014), and / or others.

[0019] The description of “DRAM” in this document can be applied to any memory device that allows random access, whether volatile or non-volatile. Memory device or DRAM can refer to the die itself and / or the packaged memory product.

[0020] As a non-limiting example of the flexible DLL calibration described in this paper, consider a memory device built on 3DXP technology. 3DXP technology is under development and is expected to find use in computing platforms with varying requirements regarding bandwidth and storage capacity. Some implementations will require faster access to 3DXP memory, while others may require lower pin counts. 3DXP technology enables the development of non-volatile memory devices that support random access. Some implementations can provide access speeds comparable to traditional DRAM speeds, rather than those of traditional non-volatile technologies such as NAND flash memory.

[0021] In one embodiment, a 3DXP device can be synchronous and operate based on a clock signal that serves as a timing reference for data exchange (transmitting and / or receiving data). In synchronous operation, data can be transmitted and received using a known relationship with the reference signal. Because 3DXP technology supports different implementations, it can be deployed in systems requiring high-frequency access or in systems requiring only low-frequency access. Similar to conventional memory technologies, in high-frequency operation, 3DXP memory devices will need to maintain the clock-data signal relationship when process, voltage, and temperature (PVT) variations are present. Typical PVT variations result in reduced timing margins.

[0022] In one embodiment, a 3DXP device includes a DLL (Dynamic Link Controller) for maintaining consistent timing relationships between clock signals and output data signals over time, even in higher-speed operation, where process, voltage, and temperature variations cause these relationships to change over time. While a DLL improves the frequency of operation by maintaining a constant relationship between clock and data signal transmissions, it periodically calibrates the clock and data paths each time, consuming significant power. In one embodiment, certain implementations of the 3DXP device will have lower access speeds and can tolerate greater variations in data transfer timing, and therefore do not require DLL calibration.

[0023] As stated above, 3DXP technology is a non-limiting example, and other memory device technologies have also undergone trade-offs in maintaining a consistent relationship between timing references and data using DLLs versus the significant power consumed by calibrating the DLLs. Similarly, other memory technologies exist that may have different implementations where timing margins are not a concern and other implementations where variations in timing margins based on operating conditions can lead to signal transmission errors. Utilizing either 3DXP technology or other memory technologies, it is possible to have continuously used, lower-power system implementations where relaxed timing margins do not require DLL calibration.

[0024] Different DLL calibration modes allow for setting different calibration cycles based on system needs. As described below, there are four main calibration modes, which are to be understood as non-limiting. Other calibration modes are possible, and the flexibility to apply different modes is to be understood similarly to the different calibration mode configurations. Calibration modes provide system flexibility to trade off power performance based on DLL operation. Different calibration modes allow modifications to the memory device interface to change how often DLL calibration is performed. This flexibility allows system designers to choose between high-frequency, high-power operation and low-frequency, low-power operation, rather than choosing continuous DLL calibration that consumes a lot of power in low-frequency, low-power applications. Furthermore, it enables occasional DLL calibration in low-frequency, low-power applications, rather than simply disabling DLL operation entirely as is the case with traditional implementations.

[0025] Figure 1This is a block diagram of one embodiment of a system in which memory device I / O phase control can be selectively calibrated. System 100 includes elements of a memory subsystem in a computing device. Processor 110 represents a processing unit of a host computing platform that executes an operating system (OS) and applications, which may be collectively referred to as the "host" for memory. The OS and applications perform operations that result in memory access. Processor 110 may include one or more individual processors. Each individual processor may include a single and / or multi-core processing unit. The processing unit may be a main processor (such as a CPU (Central Processing Unit)) and / or a peripheral processor (such as a GPU (Graphics Processing Unit)). System 100 may be implemented as a System-on-a-Chip (SoC) or using separate components.

[0026] Memory controller 120 represents one or more host controller or memory controller circuitry or devices for system 100. Memory controller 120 represents control logic that generates memory access commands and / or otherwise enables memory access in system 100 in response to the execution of operations by processor 110. Memory controller 120 accesses one or more memory devices 140. In one embodiment, memory device 140 represents a three-dimensional stacked memory device. In one embodiment, memory device 140 represents a 3D cross-point memory device or other non-volatile memory device. In one embodiment, according to any of the above, memory device 140 may be DRAM. In one embodiment, memory devices 140 are organized and managed as different channels, each channel being coupled to a bus and signal lines that are coupled in parallel to multiple memory devices. When using channels, each channel can be independently operable. Therefore, each channel is accessed and controlled independently, and timing, data transfer, command and address exchange, and other operations are separate for each channel. In one embodiment, settings for each channel are controlled by separate mode registers or other register settings. In one embodiment, each memory controller 120 manages a separate memory channel, but the system 100 can be configured to have multiple channels managed by a single controller, or multiple controllers on a single channel. In one embodiment, the memory controller 120 is part of the host processor 110, such as logic implemented on the same die as the processor or logic implemented in the same package space as the processor.

[0027] The memory controller 120 includes I / O interface logic 122 for coupling to a system bus. The I / O interface logic 122 (and the I / O 142 of the memory device 140) may include pins, connectors, signal lines, and / or other hardware for connecting the devices. The I / O interface logic 122 may include a hardware interface. As illustrated, the I / O interface logic 122 includes at least a driver / transceiver for the signal lines. Typically, wires within an integrated circuit interface with pads or connectors to interface to signal lines or traces between devices. The I / O interface logic 122 may include drivers, receivers, transceivers, terminations, and / or other circuitry for sending and / or receiving signals on the signal lines between devices. The system bus may be implemented as a plurality of signal lines coupling the memory controller 120 to the memory device 140. In one embodiment, the system bus includes at least a clock (CLK) 132, a command / address (CMD) 134, a data (DQ) 136, and other signal lines 138. The signal lines for CMD 134 can be referred to as the "C / A bus" (or ADD / CMD bus, or some other name indicating the transmission of command and address information), and the signal lines for DQ 136 are referred to as the "data bus." In one embodiment, independent channels have different clock signals, C / A buses, data buses, and other signal lines. Therefore, in the sense that independent interface paths can be considered as independent system buses, system 100 can be considered to have multiple "system buses." It will be understood that, in addition to the lines explicitly shown, system buses may also include strobe signal transmission lines, guard lines, auxiliary lines, and other signal lines.

[0028] In one embodiment, the system bus includes a data bus (DQ 136) configured to operate at bandwidth. Based on the design and / or implementation of system 100, DQ 136 may have more or less bandwidth per memory device 140. For example, DQ 136 may support memory devices with x32, x16, x8, or other interfaces. The convention "xN" (where N is a binary integer) refers to the interface size of memory device 140, representing the number of signal lines DQ 136 exchanging data with memory controller 120. The interface size of the memory devices is a control factor regarding how many memory devices can be used simultaneously per channel in system 100 or how many memory devices can be coupled in parallel to the same signal lines.

[0029] Memory device 140 represents memory resources for system 100. In one embodiment, each memory device 140 is a separate memory die. In one embodiment, each memory device 140 may include multiple (e.g., two) channels per die. Each memory device 140 includes I / O interface logic 142 having a bandwidth (e.g., x16 or x8 or some other interface bandwidth) determined by the device implementation and enabling the memory device to interface with memory controller 120. I / O interface logic 142 may include a hardware interface and may be based on the memory controller's I / O 122, but at the end of the memory device. In one embodiment, multiple memory devices 140 are connected in parallel to the same data bus. For example, system 100 may be configured with multiple memory devices 140 coupled in parallel, wherein each memory device responds to commands and accesses memory resources 160 within each. For a write operation, a single memory device 140 may write a portion of the entire data word, and for a read operation, a single memory device 140 may retrieve a portion of the entire data word.

[0030] In one embodiment, the memory device 140 is disposed directly on the motherboard or host system platform of the computing device (e.g., a PCB (printed circuit board) on which the processor 110 is disposed). In one embodiment, the memory device 140 may be organized in a memory module 130. In one embodiment, the memory module 130 represents a dual in-line memory module (DIMM). In one embodiment, the memory module 130 represents another organization of multiple memory devices for sharing at least a portion of access or control circuitry, which may be circuitry, separate devices, or separate boards separate from the host system platform. The memory module 130 may include multiple memory devices 140, and the memory module may include support for multiple separate channels to the included memory devices, which are disposed on the multiple separate channels.

[0031] Each of the memory devices 140 includes a memory resource 160. The memory resource 160 represents various arrays of memory locations or storage locations for data. In one embodiment, the memory resource 160 is managed as a data row accessed via cache lines (rows) and bit lines (individual bits within a row). In one embodiment, the memory resource 160 may be organized as separate channels, ranks, and banks of memory. A channel is an independent control path to a storage location within the memory device 140. A column refers to a common location across multiple memory devices (e.g., the same row address within different devices). A bank refers to an array of memory locations within the memory device 140. In one embodiment, the banks of memory are divided into sub-banks, with at least a portion of shared circuitry directed to the sub-banks. In one embodiment, other organization of memory resource storage locations may be used. Regardless of how it is organized, the memory resource 160 can be accessed via address information (as generally illustrated, "address").

[0032] In one embodiment, memory device 140 includes one or more registers 144. Register 144 represents a storage device or storage location that provides configuration or settings for the operation of the memory device. In one embodiment, register 144 may provide a storage location for memory device 140 to store data for access by memory controller 120 as part of control or management operations. In one embodiment, register 144 includes a mode register. In one embodiment, register 144 includes a multipurpose register. Configuration of locations within register 144 may configure memory device 140 to operate in different “modes,” where commands and / or address information or signal lines may trigger different operations within memory device 140 depending on the mode. Settings within register 144 may indicate configurations for I / O settings (e.g., timing, termination, or ODT (on-die termination), drive configuration, and / or other I / O settings).

[0033] In one embodiment, memory device 140 includes an ODT 146, which serves as part of the interface hardware associated with I / O 142. The ODT 146 can be configured as mentioned above and provides settings for the impedance to be applied to the interface on designated signal lines. The ODT settings can be changed based on whether the memory device is the selected target or a non-target device for an access operation. The ODT 146 settings can affect the timing and reflections of signal transmissions on terminated lines. Careful control of the ODT 146 can enable higher-speed operation by improving the matching of the applied impedance and load.

[0034] Memory device 140 includes a controller 150, which represents control logic within the memory device for controlling internal operations within the memory device. For example, controller 150 decodes commands sent by memory controller 120 and generates internal operations to execute or satisfy those commands. Controller 150 may be referred to as an internal controller. Controller 150 can determine which mode to select based on register 144, and configure access to and / or execution of operations for memory resource 160 based on the selected mode. Controller 150 generates control signals to control the routing of bits within memory device 140 to provide an appropriate interface or I / O 142 for the selected mode and to direct commands to the appropriate memory location or address.

[0035] Referring again to memory controller 120, memory controller 120 includes command (CMD) logic 124, which represents logic or circuitry used to generate commands to be sent to memory device 140. Typically, signaling in a memory subsystem includes address information within or accompanying the command, used to indicate or select one or more memory locations where the memory device should execute the command. In one embodiment, controller 150 of memory device 140 includes command logic 152 for receiving and decoding command and address information received from memory controller 120 via I / O 142. Based on the received command and address information, controller 150 can control the timing of the operation of the logic and circuitry within memory device 140 used to execute the command. Controller 150 is responsible for conforming to standards or specifications that include timing margins for I / O signal transmissions.

[0036] In one embodiment, memory device 140 includes phase control 174 for controlling the phase or other timing characteristics of I / O 142. Thus, for example, phase control 174 enables memory device 140 to adjust the phase to synchronize DQ 136 with clock 132. In one embodiment, at least a portion of the logic or circuitry of phase control 174 is part of controller 150. In one embodiment, phase control 174 includes a DLL. The DLL can operate to maintain timing margins for I / O 142 and can be synchronized according to one or more calibration modes.

[0037] In one embodiment, the memory controller 120 includes calibration control 172, which represents circuitry / logic within the memory controller for providing calibration settings to the memory device 140 for timing synchronization. In one embodiment, calibration control 172 enables the memory controller 120 to set a DLL calibration mode configuration for the memory device 140. The calibration mode configuration set by calibration control 172 can affect how the phase control 174 of the memory device 140 operates. In one embodiment, calibration control 172 programs one or more multipurpose registers 144 or other registers to store the configuration for the calibration mode. Such multipurpose registers enable configurability for DLL calibration timing within the memory 140. In one embodiment, calibration control 172 determines the operating conditions of the memory device 140 (such as the configuration of system 100), environmental conditions (e.g., voltage, noise, temperature), and / or other conditions. In one embodiment, calibration control 172 enables the memory controller 120 to perform one or more test operations on the memory device 140 to determine process variations or other conditions that may set I / O data eye margins or other signal transmission characteristics.

[0038] Phase control 174 may perform DLL calibration more or less frequently, depending on the DLL calibration mode set by calibration control 172. In one embodiment, memory device 140 includes a sensor (not shown) that provides environmental condition information to memory controller 120, which can be used by calibration control 172 to set the calibration mode.

[0039] Figure 2 This is a block diagram of one embodiment of a system in which the memory device includes a configurable DLL calibration mode. System 200 represents components of a memory subsystem. System 200 provides according to Figure 1 This is an example of a memory subsystem in an embodiment of system 100. System 200 can be included in any type of computing device or electronic circuitry that uses memory controlled by a DLL with I / O timing. Host 210 represents control circuitry for system 200. Host 210 may include a processor and a memory controller or storage controller. The processor of host 210 may include any type of processing logic or components that perform operations based on data stored in or to be stored in memory 230. Host 210 may include a host processor, central processing unit (CPU), microcontroller or microprocessor, graphics processor, peripheral processor, application-specific processor, or other processor. Host 210 may be or include single-core or multi-core circuitry. The host executes an operating system (OS), which controls the execution flow of the computing device or part of the computing device in which system 200 is incorporated.

[0040] Host 210 includes (either as part of the same circuitry as the processor or as part of a separate circuitry) a controller that implements access to memory 230. In one embodiment, system 200 is a system in which the processor and memory devices are integrated onto the same substrate or PCB. Host 210 includes I / O 220, which represents interface hardware used to couple to memory 230. For the purposes illustrated in system 200, I / O 220 includes a command interface 222, a clock or timing reference 224, and data 226. Memory 230 includes I / O 240 with corresponding interface hardware commands 242, clock 244, and data 246. It will be understood that other interfaces may be included. In one embodiment, command interface 222 includes a command / address bus. In one embodiment, data 226 includes a data bus separate from the command / address bus of command interface 222. In one embodiment, command interface 222, clock 224, and data 226 may be considered as part of the same bus. For example, in some non-volatile memory technologies (such as NAND memory), such signal lines may be considered as combined in a single bus. The host 210 is communicatively coupled to the memory 230 via an interface from I / O 220 to I / O 240. The host 210 accesses the memory 230 via the interface.

[0041] Memory 230 includes an array 232 representing storage locations of stored data within memory 230. Array 232 may include any number of storage locations, and memory 230 includes (not explicitly shown) interface hardware for accessing various addressable storage locations within array 232. Command 242 receives a command from host 210, and an internal controller of memory 230 (not explicitly shown) decodes the command to result in access to one or more appropriate storage locations in array 232. In one embodiment, array 232 is an array of non-volatile memory cells, and memory 230 is a three-dimensional stacked memory device with random access capability.

[0042] In one embodiment, I / O 242 includes I / O hardware 248, which may include drivers, termination, receivers, routing hardware, and / or other components that connect the array 232 interface to the data interface 246 based on command 242 and clock 244. For write operations, data is received via data 246 to be written to the array 232. For read operations, data is sent via data 246 to the host 210. In one embodiment, I / O hardware 248 includes one or more buffers for implementing burst access.

[0043] In one embodiment, I / O 240 includes DLL 256, which represents a phase control mechanism that can control the timing of the operation of I / O hardware 248. DLL 256 then operates based on one or more settings in register 252. In one embodiment, calibration control 254 controls how frequently the operation of DLL 256 is calibrated (e.g., any range from no calibration to continuous calibration) is performed based on a DLL calibration mode configured in register 252. By utilizing register 252 to enable multiple configuration modes, calibration control 254 can provide greater flexibility to perform DLL calibration at any time interval required for proper operation of memory 230 or at any time interval required for proper synchronization of data 246 via DLL 256.

[0044] In one embodiment, host 210 configures register 252 for DLL calibration to selectively enable and disable DLL calibration. In one embodiment, DLL 256 controls I / O eye 260, which may represent a signal transmission “eye” at data interface 246. I / O eye 260 will be understood as a non-limiting example and represents signal transmission between voltage rails (VDD and VSS). Voltage rails refer to high and low voltage references, where VDD is the high voltage reference used for signal transmission and VSS is the low voltage signal transmission reference. In one embodiment, memory 230 includes a VTT reference, which may be between VDD and VSS and may be used for termination and / or other signal transmission characteristics. VTT is not necessarily present in all examples of memory 230. Signal 262 represents a “data eye,” which is an approximation of many different I / O signals or a composite signal of many different signals sent and / or received over time. The approximation of composite signal 262 provides openings within the signal, where valid signal 264 indicates an approximation of the voltage level and timing that should guarantee that the I / O signal will be properly interpreted.

[0045] Typically, the valid region 264 is set via standards or protocols and / or through training. The space between signal 262 and valid region 264 is margin 266. Margin 266 indicates how much variation can occur in signal 262 while still adhering to the timing / voltage requirements of a valid signal. Sometimes expressions such as “margin” and “margin adjustment” can refer to determining what settings should be used to make signal 262 achieve a valid eye 264, and / or refer to configuring I / O to achieve such valid signal transmission. DLL 256 can control the timing of signals exchanged via data 246 (e.g., transmitted and / or received) to ensure a valid I / O eye 260. In one embodiment, calibration control 254 refers to the control logic between register 252 and DLL 256 and / or other I / O hardware 248 used to control the calibration of DLL 256.

[0046] In one embodiment, if memory 230 is deployed in a "non-volatile memory" application, calibration control 254 may perform DLL calibration infrequently or not at all. In memory applications, signal transmission speeds may be slower, and the margin 266 may be large enough that regular DLL calibration is not required. In one embodiment, if memory 230 is deployed as main memory replacement, calibration control 254 may perform DLL calibration or DLL tracing more frequently or continuously. In "main memory" applications, signal transmission speeds are faster, and the margin 266 may be much smaller, requiring more frequent DLL calibration operations.

[0047] In one embodiment, calibration is based on one or more operating conditions, such as the environmental conditions of the computing device of system 200, or the power supply to system 200. Changing conditions may affect voltage rails, thereby introducing voltage variations into the rails and / or introducing noise into the power supply lines of either rail. In one embodiment, calibration control 254 can selectively enable and disable calibration based on a DLL calibration mode setting in register 252. It will be understood that disabling DLL calibration may result in a delay of approximately a few microseconds whenever calibration is disabled and then re-enabled. In one embodiment, host 210 can determine when noise is present regarding the power supply to a particular memory 230 and / or other variations in system 200, and set the DLL calibration mode based on the condition of the memory. In one embodiment, the host sets the calibration mode based on the system configuration, such as whether memory 230 is configured for high-speed or low-speed access.

[0048] Figure 3 This is a block diagram of one embodiment of a system in which a DLL calibration mode for a memory device can be applied. System 300 represents the elements of a memory system and provides an example of a system according to an embodiment of system 100 and / or an embodiment of system 200. System 300 includes a host 310 and a memory 330. The host 310 is communicatively coupled to the memory 330 via an interface 320. Interface 320 may include point-to-point connections, multipoint bus connections, routed signal lines, I / O hardware (similar to those described above), and / or other mechanisms for enabling one device to communicate with another. I / O 332 represents the I / O interface of the memory 330. Although not explicitly shown, it will be understood that the host 310 also includes an I / O interface, and interface 320 represents the interconnection of those two I / O interfaces. I / O 332 may include the I / O hardware as previously described. I / O 332 does not necessarily show all connections that will exist between the host 310 and the memory 330.

[0049] In one embodiment, host 310 includes scheduler 312, which represents control logic for determining what commands to send to which memory devices and when to send them. In response to execution by a host processor (not specifically shown), the scheduler can generate commands to be sent to memory 330 to access data not stored in a local cache or local buffer. The data may include commands and / or values. Scheduler 312 provides command 322 (which may include address information) to memory 330 via interface 320. In one embodiment, internal controller 334 receives and decodes the command data. Such command data may include a Mode Register Setting (MRS) command for setting a mode register or a multipurpose register of a mode register. Such command data may include access commands. Such command data may include calibration commands, but a separate calibration path is illustrated for purposes illustrated in system 300. Controller 334 directs operations in memory 330 based on commands received from host 310.

[0050] In one embodiment, the memory 330 is synchronized and synchronized with a clock signal 324 received via interface 320. The host 310 includes one or more oscillators 314, representing hardware that generates periodic signals used to control the timing of operations within the host 310. In one embodiment, the host 310 provides the clock signal 324 based on the oscillator 314. It will be understood that the clock signal 324 is not necessarily a direct output of the oscillator 314, but may be filtered, conditioned, or otherwise modified before being sent to the memory 330.

[0051] In one embodiment, memory 330 includes an internal oscillator 346, which can be used in certain operations asynchronous with host 310, such as certain low-power operations. Not every implementation of memory 330 will include an internal oscillator 346. Oscillators 346 do not necessarily operate at the same nominal frequency as oscillator 314, but they may. Oscillator 346 enables memory 330 to generate an internal clock signal for operations that do not use external clock 324. In one embodiment where memory 330 includes oscillator 346, memory 330 may include a selection mechanism (such as multiplexer 340) for selecting between internal and external clock signals. Whether from an internal oscillator or synchronized with an external clock signal, memory 330 includes an internal clock 348 for defining the timing of operations within memory 330.

[0052] In one embodiment, memory 330 includes a DLL 344 for controlling the timing or phase of data I / O 328 based on a clock signal 324 and a feedback loop as understood in the art. Conventionally, when DLL 344 is active, it continuously tracks the phase of data I / O 328 relative to clock 324 and adjusts the output based on the clock signal. Continuous tracking refers to DLL calibration, which can consume significant power. For illustrative purposes, DLL calibration (CAL) 342 is illustrated adjacent to DLL 344. DLL calibration 342 represents the logic that can control the calibration operation of DLL 344. In one embodiment, DLL calibration 342 can be considered part of controller 334. Controller 334 is not necessarily a single logic circuit but may include distributed control logic within memory 330.

[0053] Memory 330 includes memory resource 360, which represents a storage cell or memory location storing data in memory 330. The memory resource can be implemented according to embodiments of memory technology as described above. Memory 330 includes access hardware 362 for interface-connecting with memory resource 360 ​​and controlling access to data stored in memory resource 360. For write operations, access hardware 362 can select one or more address locations and set one or more address locations using the data to be written. For read operations, access hardware 362 can select one or more address locations and read data stored in one or more address locations.

[0054] Access hardware 362 interfaces memory resource 360 ​​with the data bus of data I / O 328 for interface 320. Access hardware 362 can implement interconnection between one or more buffers 318 of host 310 and memory resource 360. In one embodiment, access hardware 362 includes one or more buffers. Buffer 318 may represent a temporary queue of data to be written to memory resource 360 ​​for write transactions, or a temporary queue used to store data received from memory resource 360 ​​in read transactions. Host 310 can fill or empty buffer 318 according to commands provided by scheduler 312.

[0055] In one embodiment, memory 330 includes an ODT (on-die termination) 354. In another embodiment, system 300 includes an off-chip termination for memory 330, which can provide I / O impedance via a connection to I / O 332 (not shown). Whether it is external impedance or ODT 354, memory 330 can provide specific I / O impedance for data exchanged through data interface 328. Although dashed boxes are shown for illustration, in one embodiment, the termination can be considered as a “part” of I / O 332. The termination impedance is applied as part of the interface to provide a certain impedance when viewed from the perspective of host 310 for I / O 332.

[0056] In one embodiment, controller 334 and / or DLL calibration 342 perform calibration according to DLL calibration mode settings stored in register 336. In one embodiment, several distinct DLL calibration modes may exist. Modes may include a mode in which DLL calibration 342 operates continuously when memory 330 is active and is turned off when memory 330 is in a low-power state. Modes may include a mode in which DLL calibration 342 operates continuously regardless of whether memory 330 is active or in a low-power state, comparable to conventional DLL calibration operations. Modes may include host-initiated calibration modes in which host 310 provides an explicit DLL calibration command to memory 330. Such a mode can be represented by calibration logic 316, which provides calibration command 326 to memory 330. In one embodiment, calibration logic 316 represents logic used to determine and set a selected DLL calibration mode (such as determining the operating state of memory 330 and setting the DLL calibration mode based on that operating state). Therefore, calibration command 326 may represent a command used to set the calibration mode.

[0057] It will be understood that selectively enabling or disabling DLL calibration operations can occur at runtime within system 300. Therefore, DLL calibration 342 is dynamically configurable and can be changed (even at runtime), rather than a system that includes a unified setting for DLL operation. In one embodiment, a DLL configuration mode is set at each initialization or power-on of system 300. In one embodiment, host 310 periodically determines whether to update the DLL calibration mode. In one embodiment, host 310 determines to update the DLL calibration mode in response to detecting certain conditions, such as receiving an interrupt, receiving an operational status indication from memory 330, or other detections. The selected calibration mode determines the time interval for operations performed by DLL calibration 342. Therefore, DLL calibration 342 will operate at time intervals identified by the calibration mode.

[0058] In one embodiment, the DLL calibration mode may include a DLL calibration mode in which DLL calibration occurs together with ZQCal operation. ZQCal refers to impedance calibration. In one embodiment, memory 330 includes ZQCal 352. In one embodiment, memory 330 includes only ZQCal 352, and in one embodiment it also includes ODT 354. In one embodiment, ZQCal 352 includes one or more configuration settings in register 336. For example, one or more mode registers may store configuration settings that control a schedule for when ZQCal operations are performed.

[0059] ZQCal operation can refer to the operations performed by a ZQCal engine that performs various I / O operations and measures timing and signal transmission characteristics to determine the settings that achieve the desired I / O characteristics. ZQCal 352 can represent a ZQCal engine. Similarly, DLL calibration 342 can be considered a DLL calibration engine that performs various I / O operations in different settings to determine what settings achieve the desired I / O margin and / or other timing constraints and / or I / O eye characteristics. In one embodiment, DLL calibration 342 performs DLL calibration whenever ZQCal 352 performs impedance calibration.

[0060] Figure 4 This is a block diagram of one embodiment of a mode register used to selectively enable DLL calibration modes. Mode register (MRx) 410 represents an example of a mode register in a DRAM or other memory device that supports different DLL calibration modes. In one embodiment, multiple separate mode registers may be illustrated as mode register 410. As illustrated, addresses AY[1:0] represent the bits that set a specific DLL calibration mode. The example shown in mode register 410 is consistent with other examples provided herein and illustrates a non-limiting example. More or fewer DLL calibration modes may be used, and different bit patterns may be used to represent different DLL calibration modes.

[0061] In one embodiment, when AY[1:0]='00', the DLL calibration operation is connected to the ZQCal operation. Therefore, when the ZQCal operation occurs (which can be in response to a command from the host), the memory device also performs DLL calibration. In one embodiment, DLL calibration runs concurrently with ZQCal by default. In one embodiment, when AY[1:0]='01', DLL calibration continues DLL tracking during active and idle modes, and DLL is turned off during low-power mode. In one embodiment, when AY[1:0]='11', DLL calibration continues DLL tracking during active, idle, and low-power modes. Having DLL calibration track during low-power mode increases power consumption but results in less latency when exiting low-power mode. In one embodiment, when AY[1:0]='10', the DLL calibration operation is controlled by explicit commands from the host. Host-initiated DL calibration indices start or stop DLL calibration via command or by setting the mode register bit AZ, where '0' stops calibration and '1' starts calibration.

[0062] Address AZ represents the bit that triggers the DLL calibration operation in host-initiated DLL calibration mode. In one embodiment, address AZ may be located in a different mode register than the mode register that stores one or more bits setting the DLL calibration mode. In one embodiment, control bit AZ='0' stops DLL calibration, and control bit AZ='1' starts DLL calibration. In one embodiment, when the DLL calibration mode is not set to host-initiated calibration mode, the memory device ignores AZ, and its value has no effect on operation.

[0063] It will be understood that a host-initiated calibration mode may require the host to perform calibration based on the environment or board characteristics of the system in which the memory is deployed. Given that ZQCal typically only responds to temperature fluctuations and can therefore be executed every few hundred milliseconds, the DLL may be affected by a wider range of conditions than temperature. DLL operation may be affected by noise, which may require the host to monitor power supply noise in addition to system temperature and perform DLL calibration when changes in the noise exceed a threshold.

[0064] In one embodiment of 3DXP technology implementation, the 3DXP memory device may include a mode register, such as mode register 410, for providing DLL calibration modes. Different DLL calibration modes allow the 3DXP memory to achieve power / frequency flexibility through mode registers that can be set according to system operation. It will be understood that disabling DLL calibration can provide power-saving benefits. For example, DLL calibration can be set to be disabled when the 3DXP memory is in low-power mode because there is no bus activity according to appropriate interface signaling. It will be understood that this will result in a minimum power level, but will increase latency, while the DLL calibrates before communication with the host / controller can be re-established.

[0065] Figure 5 This is a flowchart of one embodiment of a process for applying selective DLL calibration. More specifically, process 500 may allow selective application of DLL calibration modes. In one embodiment, the host identifies a system configuration for an associated memory device, 502. The memory device can be any embodiment of the memory device described herein. In one embodiment, a user or system designer enters information indicating the system configuration. In one embodiment, the BIOS (Basic Input / Output System) discovers the system configuration by polling the device. The system configuration may identify whether the memory device is configured for high-speed access or only for low-speed access.

[0066] In one embodiment, based on system configuration, the host determines a DLL calibration mode for an operating mode, 504. In one embodiment, a specific DLL calibration mode is associated with a system configuration, operating mode, or operating condition. Such an association can be predetermined by the system designer. In one embodiment, the host identifies a specific operating mode of the memory device, 506. Determining a specific operating mode can, for example, determine when the memory device enters a low-power state or when it leaves a low-power state. Such determination can include identifying the environmental conditions of the system.

[0067] In one embodiment, the host sets the DLL calibration mode of the memory device based on the identified operating mode, 508. In one embodiment, as an example, the DLL calibration mode may include four different modes. In one embodiment, the host sets the memory to a calibration mode in which impedance calibration is performed to control DLL calibration, 510. When ZQCal performs control DLL calibration, it will be understood as referring to the frequency of operation, where the DLL calibration operation is configured to occur at the same frequency as the ZQCal operation.

[0068] In one embodiment, the host sets the memory to a mode in which DLL tracking occurs only during active mode, 512. In one embodiment, such a mode may include active mode and idle mode. In one embodiment, the host sets the memory to a mode in which DLL tracking occurs during active mode and low-power mode, 514. In one embodiment, the host sets the memory to a mode in which DLL calibration occurs in response to a command initiated by the host, 516. Such a command may be separate from the command that triggers the execution of ZQCal.

[0069] In one embodiment, in the case of host-initiated DLL calibration, the host can determine whether to perform DLL calibration, 518. The host can make this determination based on the operating state or condition of the memory device and / or the host system in which the memory device is located. In one embodiment, the host can make this determination based on one or more schedules, some of which may correspond to certain operating modes of the memory device. Even if the host determines not to perform DLL calibration, 520 no branch, the host can continue to monitor / wait until DLL calibration should be performed.

[0070] In one embodiment, when the host determines that the memory device should perform DLL calibration, 520 is a branch where the host sets the mode register to activate DLL calibration, 522. It will be understood that in a memory subsystem with multiple memory devices, the host can use the same DLL calibration schedule on all memory devices, or it can cause different memory devices to apply DLL calibration at different times. In one embodiment, regardless of the DLL calibration mode set for the memory device, the host can continue to monitor the system and determine whether to change the calibration mode, 524. It will be understood that with different calibration modes, there may be situations where one calibration mode is more advantageous than another. In a host-initiated calibration mode, determining to change the calibration mode can refer to selectively enabling or disabling DLL calibration.

[0071] If the host determines to change the calibration mode (526 is a branch), the host can identify the specific operating mode of the memory device (506) and set the DLL calibration mode accordingly (508). In one embodiment, if the host determines not to change the calibration mode (526 is a no branch), the system continues operation using DLL tracking based on the selected / set calibration mode (528). The memory device will continue such DLL calibration operations while the host continues to monitor and determine whether the DLL calibration mode should be changed. The memory device determines the calibration mode setting and performs DLL calibration according to the DLL calibration mode. The memory device can continue to perform DLL calibration at time intervals indicated by the DLL calibration mode.

[0072] Figure 6 This is a block diagram of one embodiment of a computing system in which DLL calibration mode can be implemented. System 600 represents a computing device according to any embodiment described herein and can be a laptop computer, desktop computer, server, game or entertainment control system, scanner, copier, printer, routing or switching equipment, or other electronic equipment. System 600 includes a processor 620, which provides processing, operation management, and instruction execution for system 600. Processor 620 can include any type of microprocessor, central processing unit (CPU), processing core, or other processing hardware used to provide processing for system 600. Processor 620 controls the overall operation of system 600 and can be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or combinations of such devices.

[0073] Memory subsystem 630 represents the main memory of system 600 and provides temporary storage for code to be executed by processor 620 or data values ​​to be used in execution routines. Memory subsystem 630 may include one or more memory devices, such as read-only memory (ROM), flash memory, one or more types of random access memory (RAM), or other memory devices, or combinations of such devices. Among other things, memory subsystem 630 also stores and hosts operating system (OS) 636 to provide a software platform for the execution of instructions in system 600. Additionally, other instructions 638 from memory subsystem 630 are stored and executed to provide logic and processing for system 600. The OS 636 and instructions 638 are executed by processor 620. Memory subsystem 630 includes memory device 632, in which data, instructions, programs, or other entries are stored. In one embodiment, memory subsystem includes memory controller 634, which is a memory controller used to generate commands and issue commands to memory device 632. It will be understood that memory controller 634 may be a physical part of processor 620.

[0074] Processor 620 and memory subsystem 630 are coupled to bus / bus system 610. Bus 610 is an abstraction representing any one or more individual physical buses, communication lines / interfaces, and / or point-to-point connections connected via appropriate bridges, adapters, and / or controllers. Therefore, bus 610 may include one or more of, for example, a system bus, Peripheral Component Interconnect (PCI) bus, HyperTransport or Industry Standard Architecture (ISA) bus, Small Computer System Interface (SCSI) bus, Universal Serial Bus (USB), or Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (commonly referred to as "FireWire"). Each bus of bus 610 may also correspond to an interface in network interface 650.

[0075] System 600 also includes one or more input / output (I / O) interfaces 640, a network interface 650, one or more internal mass storage devices 660, and a peripheral interface 670 coupled to bus 610. I / O interface 640 may include one or more interface components through which users interact with system 600 (e.g., video, audio, and / or alphanumeric interface connections). Network interface 650 provides system 600 with the ability to communicate with remote devices (e.g., servers, other computing devices) over one or more networks. Network interface 650 may include an Ethernet adapter, wireless interconnect component, USB (Universal Serial Bus), or other wired or wireless standard-based interfaces or proprietary interfaces.

[0076] Storage device 660 may be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more disks, solid-state drives, or optical-based disks, or a combination thereof. Storage device 660 retains code or instructions and data 662 in a persistent state (i.e., values ​​are preserved despite a power interruption to system 600). Storage device 660 can generally be considered "memory," although memory 630 is execution or operational memory used to provide instructions to processor 620. Given that storage device 660 is non-volatile, memory 630 may include volatile memory (i.e., the value or state of data is indeterminate if power to system 600 is interrupted).

[0077] Peripheral interface 670 may include any hardware interface not specifically mentioned above. Peripheral devices generally refer to devices that are dependently connected to system 600. A dependent connection is one in which system 600 provides a software and / or hardware platform, on which operations are performed and on which the user interacts.

[0078] In one embodiment, system 600 includes DLL calibration control 680. Although shown as a separate component of system 600, it will be understood that DLL calibration control 680 may be part of one or more other systems. For example, one or more memory devices 632 may include DLL calibration control 680 according to embodiments described herein. As another example, storage device 660 may include DLL calibration control 680 according to embodiments described herein. In one embodiment, system 600 includes non-volatile memory 632, such as a 3D stacked memory device or a 3DXP memory device, and may not include storage device 660 separate from such memory 632. DLL calibration control 680 includes configuration settings that identify DLL calibration modes or operates according to configuration settings that identify DLL calibration modes. DLL calibration control 680 supports multiple different DLL calibration modes, which are dynamically configurable to provide different time intervals for DLL tracking operations or DLL calibration operations. In one embodiment, memory 632 is DRAM. In one embodiment, processor 620 represents one or more processors that execute data stored in one or more DRAM memories 632. In one embodiment, network interface 650 exchanges data with another device in another network location, and the data is data stored in memory 632.

[0079] Figure 7 This is a block diagram of one embodiment of a mobile device that can implement DLL calibration mode. Device 700 represents a mobile computing device, such as a computing tablet, mobile phone or smartphone, wirelessly enabled e-reader, wearable computing device or other mobile device. It will be understood that some of the components are generally shown, and not all components of such a device are shown in device 700.

[0080] Device 700 includes a processor 710, which performs the main processing operations of device 700. Processor 710 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing unit. The processing operations performed by processor 710 include the execution of an operating platform or operating system on which application and / or device functions are performed. Processing operations include operations relating to I / O (input / output) concerning human users or other devices, operations relating to power management, and / or operations relating to connecting device 700 to another device. Processing operations may also include operations relating to audio I / O and / or display I / O.

[0081] In one embodiment, device 700 includes an audio subsystem 720, which represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. Audio functionality may include speaker and / or headphone outputs, and microphone inputs. Devices for such functionality may be integrated into or connected to device 700. In one embodiment, a user interacts with device 700 by providing audio commands received and processed by processor 710.

[0082] Display subsystem 730 represents hardware (e.g., display device) and software (e.g., driver) components that provide visual and / or tactile displays to a user for interaction with a computing device. Display subsystem 730 includes display interface 732, which includes a specific screen or hardware device for providing a display to a user. In one embodiment, display interface 732 includes logic decoupled from processor 710 for performing at least some display-related processing. In one embodiment, display subsystem 730 includes a touchscreen device that provides both input and output to a user. In one embodiment, display subsystem 730 includes a high-definition (HD) display that provides output to a user. High-definition can refer to a display with a pixel density of approximately 100 PPI (pixels per inch) or greater, and can include formats such as Full HD (e.g., 1080p), Retina display, 4K (Ultra-High Definition or UHD), or others.

[0083] I / O controller 740 represents hardware devices and software components related to user interaction. I / O controller 740 can operate to manage hardware that is part of audio subsystem 720 and / or display subsystem 730. Additionally, I / O controller 740 illustrates connection points for additional devices connected to device 700 through which the user may interact with the system. For example, devices that can be attached to device 700 may include microphone devices, speakers or stereo systems, video systems or other display devices, keyboards or keypad devices, or other I / O devices for use with specific applications, such as card readers or other devices.

[0084] As mentioned above, the I / O controller 740 can interact with the audio subsystem 720 and / or the display subsystem 730. For example, input via a microphone or other audio device can provide input or commands to one or more applications or functions of the device 700. Additionally, audio output can be provided instead of or in addition to display output. In another example, if the display subsystem includes a touchscreen, the display device also acts as an input device, which can be managed at least partially by the I / O controller 740. Additional buttons or switches may also be present on the device 700 to provide I / O functions managed by the I / O controller 740.

[0085] In one embodiment, the I / O controller 740 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning systems (GPS), or other hardware that may be included in device 700. Inputs may be part of direct user interaction and provide environmental inputs to the system to affect its operation (such as filtering for noise, adjusting the display for brightness detection, applying camera flash, or other features). In one embodiment, device 700 includes power management 750, which manages battery power usage, battery charging, and features related to power-saving operation.

[0086] The memory subsystem 760 includes one or more memory devices 762 for storing information in the device 700. The memory subsystem 760 may include non-volatile (the state does not change if power to the memory device is interrupted) and / or volatile (the state is indeterminate if power to the memory device is interrupted) memory devices. The memory 760 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of the system 700. In one embodiment, the memory subsystem 760 includes a memory controller 764 (which may also be considered part of the control of the system 700 and potentially part of the processor 710). The memory controller 764 includes a scheduler for generating commands and issuing them to the memory devices 762.

[0087] Connectivity 770 includes hardware devices (such as wireless and / or wired connectors and communication hardware) and software components (such as drivers and protocol stacks) that enable device 700 to communicate with external devices. External devices can be standalone devices, such as other computing devices, wireless access points or base stations, and peripheral devices (such as headphones, printers, or other devices).

[0088] Connectivity 770 can include several different types of connectivity. In general, device 700 is illustrated with cellular connectivity 772 and wireless connectivity 774. Cellular connectivity 772 generally refers to cellular network connectivity provided by a wireless carrier, such as cellular network connectivity provided via GSM (Global System for Mobile Communications) or its variants or derivatives, CDMA (Code Multiple Access) or its variants or derivatives, TDM (Time Division Multiplexing) or its variants or derivatives, LTE (Long Term Evolution – also known as “4G”), or other cellular service standards. Wireless connectivity 774 refers to non-cellular wireless connectivity and may include personal area networks (such as Bluetooth), local area networks (such as WiFi), and / or wide area networks (such as WiMax), or other wireless communications. Wireless communication refers to the transmission of data via a non-solid medium using modulated electromagnetic radiation. Wired communication occurs via a solid communication medium.

[0089] Peripheral connection 780 includes hardware interfaces and connectors, as well as software components (such as drivers and protocol stacks) used to make the peripheral connection. It will be understood that device 700 can be both a peripheral device to other computing devices (“to” 782) and have peripheral devices connected to it (“from” 784). Device 700 typically has a “dock” connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, modifying, synchronizing) content on device 700. Additionally, the dock connector may allow device 700 to connect to certain peripheral devices that allow device 700 to control content output, such as to an audiovisual system or other system.

[0090] In addition to proprietary docking connectors or other proprietary connection hardware, device 700 can also make peripheral connections 780 via common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of many different hardware interfaces), display ports including Mini DisplayPort (MDP), High Definition Multimedia Interface (HDMI), FireWire, or other types.

[0091] In one embodiment, system 700 includes DLL calibration control 790. Although shown as part of memory subsystem 760, it will be understood that DLL calibration control 790 can be part of any system that uses DLLs for I / O timing control. In one embodiment, one or more memory devices 762 may include DLL calibration control 790 according to embodiments described herein. In one embodiment, memory device 762 may include a non-volatile memory device, such as a 3D stacked memory device or a 3DXP memory device. DLL calibration control 790 includes configuration settings that identify DLL calibration modes or operates according to configuration settings that identify DLL calibration modes. DLL calibration control 790 supports multiple different DLL calibration modes, which are dynamically configurable to provide different time intervals for DLL tracking operations or DLL calibration operations. In one embodiment, memory 762 includes DRAM. In one embodiment, processor 710 represents one or more processors that execute data stored in one or more DRAM memories 762. In one embodiment, system 700 includes a network interface (such as in connectivity 770) for exchanging data with another device in another network location, and the data is data stored in memory 762.

[0092] In one aspect, a memory device for storing data includes: input / output (I / O) interface circuitry for exchanging data with an associated host controller; delay phase-locked loop (DLL) circuitry coupled to control the I / O timing of the I / O interface; and control circuitry for selectively enabling and disabling DLL calibration for the DLL circuitry according to a DLL calibration mode configured for the memory device, wherein when selectively enabled, DLL calibration operates at time intervals identified by the DLL calibration mode, and when selectively disabled, DLL calibration prevents tracking phase updates.

[0093] In one embodiment, the memory device includes a three-dimensional (3D) stacked memory device. In one embodiment, the memory device includes a 3D crosspoint (3DXP) memory device. In one embodiment, control circuitry selectively enables and disables DLL calibration during runtime. In one embodiment, the DLL calibration mode includes a host-initiated calibration mode, wherein an associated host controller sends commands to selectively enable or disable DLL calibration. In one embodiment, the associated host controller selects the DLL calibration mode based at least in part on the noise characterization of the memory device. In one embodiment, the DLL calibration mode includes a mode in which DLL calibration operates continuously when the memory device is in an active operating state and is disabled when the memory device is in a low-power operating state. In one embodiment, the DLL calibration mode includes a mode in which DLL calibration operates continuously when the memory device is in an idle operating state and is disabled when the memory device is in a low-power operating state. In one embodiment, the associated host controller selects the DLL calibration mode based on the operating state of the memory device. In one embodiment, the associated host controller selects the DLL calibration mode based on the low-power state of the memory device. In one embodiment, the DLL configuration mode includes a mode in which DLL calibration occurs together with ZQCal operation. In one embodiment, a mode register is further included to store configuration settings for the DLL calibration mode.

[0094] In one aspect, a system having a memory subsystem includes: a host controller; and a three-dimensional stacked memory device having random access capability and non-volatile memory cells, the memory device including input / output (I / O) interface circuitry for exchanging data with the associated host controller; delay phase-locked loop (DLL) circuitry coupled to control the I / O timing of the I / O interface; and control circuitry for selectively enabling and disabling DLL calibration for the DLL circuitry according to a DLL calibration mode configured for the memory device, wherein when selectively enabled, DLL calibration operates at time intervals identified by the DLL calibration mode, and when selectively disabled, DLL calibration prevents tracking phase updates. In one aspect, the system according to any embodiment of the memory device is as described above.

[0095] In one aspect, a method for controlling I / O (input / output) synchronization in a memory device includes: determining whether to selectively enable or disable DLL calibration for a DLL circuitry coupled to control I / O timing of an I / O interface of the memory device, based on a DLL (delay-locked loop) calibration mode setting of the memory device, wherein an associated host controller sets the DLL calibration mode; and performing DLL calibration for the DLL circuitry according to the DLL calibration mode, wherein when DLL calibration is selectively enabled, DLL calibration is performed at time intervals identified by the DLL calibration mode, and when DLL calibration is selectively disabled, DLL calibration is not performed.

[0096] In one embodiment, the memory device includes a three-dimensional (3D) stacked memory device. In one embodiment, the memory device includes a 3D cross-point (3DXP) memory device. In one embodiment, performing DLL calibration includes selectively enabling and disabling DLL calibration at runtime. In one embodiment, performing DLL calibration further includes performing DLL calibration in a host-initiated calibration mode, wherein the associated host controller sends commands to selectively enable or disable DLL circuitry. In one embodiment, performing DLL calibration is based at least in part on a noise characterization of the memory device. In one embodiment, performing DLL calibration further includes performing DLL calibration in an active-on mode where DLL calibration is continuous when the memory device is in an active operating state and when the memory device is in a low-power operating state. In one embodiment, performing DLL calibration further includes performing DLL calibration in an active-on mode where DLL calibration is continuous when the memory device is in an active operating state and when the memory device is in a low-power operating state. In one embodiment, performing DLL calibration further includes performing DLL calibration in an active-on mode where DLL calibration is continuous when the memory device is in an idle operating state and when the memory device is in a low-power operating state. In one embodiment, the DLL calibration mode is further selected based on the operating state of the memory device. In one embodiment, selecting the DLL calibration mode includes a DLL calibration mode based on the low-power state of the memory device. In one embodiment, performing DLL calibration further includes performing DLL calibration in a mode in which DLL calibration occurs together with ZQCal operation. In one embodiment, it further includes storing configuration settings for the DLL calibration mode in a mode register.

[0097] In one aspect, an article of manufacture includes a computer-readable storage medium having content stored thereon for inducing execution of operations to perform a method according to any embodiment of the methods set forth above. In another aspect, an apparatus for memory management includes components for performing operations to perform a method according to any embodiment of the methods set forth above. Flowcharts illustrated herein provide examples of sequences of various process actions. Flowcharts may indicate operations to be performed by software or firmware routines, as well as physical operations. In one embodiment, a flowchart may illustrate the states of a finite state machine (FSM), which may be implemented in hardware and / or software. Although shown in a particular sequence or order, the order of actions may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and processes may be performed in different orders, and some actions may be performed in parallel. Additionally, one or more actions may be omitted in various embodiments; therefore, not all actions are required in every embodiment. Other process flows are possible.

[0098] With respect to the various operations or functions described herein, they can be described or defined as software code, instructions, configuration, and / or data. Content can be directly executable (in "object" or "executable" form), source code, or differential code ("incremental" or "patch" code). The software content of the embodiments described herein can be provided via an article of art on which the content is stored or via a method of operating a communication interface to transmit data via the communication interface. Machine-readable storage media can enable a machine to perform the described functions or operations and includes any mechanism that stores information in a form accessible to a machine (e.g., a computing device, electronic system, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces to any medium, such as hardwired, wireless, optical, etc., to transmit to another device, such as a memory bus interface, processor bus interface, Internet connection, disk controller, etc. The communication interface can be configured to prepare the communication interface to provide data signals describing the software content by providing configuration parameters and / or sending signals. The communication interface can be accessed via one or more commands or signals sent to it.

[0099] The various components described herein can be parts used to perform the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. Components can be implemented as software modules, hardware modules, special-purpose hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuits, etc.

[0100] In addition to those described herein, various modifications may be made without departing from the scope of the embodiments and implementations disclosed herein. Therefore, the descriptions and examples herein should be interpreted in an illustrative and non-limiting sense. The scope of the invention should be measured solely with reference to the following claims.

Claims

1. A memory device for storing data, comprising: A delay phase-locked loop (DLL) circuit, which is coupled to control the timing of the input / output I / O interface; as well as A control circuit is provided for selectively enabling calibration of the DLL circuit, and when enabled, the control circuit is configured to select from a plurality of calibration modes, including a first calibration mode for enabling continuous DLL circuit tracking, and a second calibration mode for enabling tracking of the DLL circuit only in response to a command. The first calibration mode is used to trigger continuous DLL tracking when the memory device is in an active operating state and an idle state, and to disable DLL circuit tracking when the memory device is in a low-power operating state.

2. The memory device of claim 1, wherein the memory device comprises a three-dimensional 3D stacked memory device.

3. The memory device of claim 2, wherein the memory device comprises a 3D cross-point 3DXP memory device.

4. The memory device of claim 1, wherein the control circuitry is configured to selectively and dynamically enable DLL calibration during the operation of the memory device.

5. The memory device of claim 1, wherein the second calibration mode includes triggering DLL circuit tracing only in response to the associated host controller.

6. The memory device of claim 1, wherein the first calibration mode is used to trigger continuous DLL circuit tracking when the memory device is in an active operating state, an idle state, and a fast standby state, and to disable DLL circuit tracking when the memory device is in a slow standby state.

7. The memory device of claim 1, wherein the second calibration mode is used to trigger impedance calibration ZQCal operation to run DLL calibration.

8. The memory device of claim 1, further comprising a mode register for storing configuration settings to indicate the calibration mode.

9. The memory device of claim 1, wherein when the I / O interface is used to operate in a high-frequency mode in a non-low-power application, the control circuitry is used to select the first calibration mode.

10. The memory device of claim 1, wherein when the I / O interface is used to operate in a low-frequency mode in a low-power application, the control circuitry is used to select the second calibration mode.

11. A method for calibrating input / output I / O circuitry of a memory device, comprising: The register settings determine whether delay-locked loop (DLL) calibration is selectively enabled to control DLL circuit tracking of the I / O circuit; When DLL calibration is enabled, multiple calibration modes are selected, including selecting from a first calibration mode to enable continuous DLL circuit tracing and selecting from a second calibration mode to enable DLL circuit tracing only in response to a command. as well as Perform DLL circuit tracing according to the selected calibration mode. Performing DLL circuit tracing according to the first calibration mode includes performing continuous DLL circuit tracing when the memory device is in an active operating state and in an idle state, and disabling DLL circuit tracing when the memory device is in a standby state.

12. The method of claim 11, wherein the memory device comprises a three-dimensional 3D stacked memory device.

13. The method of claim 12, wherein the memory device comprises a 3D cross-point 3DXP memory device.

14. The method of claim 11, wherein performing DLL circuit tracing includes selectively and dynamically enabling DLL calibration during the runtime of the memory device.

15. The method of claim 11, wherein performing DLL circuit tracing in the second calibration mode comprises performing DLL circuit tracing only in response to commands from the associated host controller.

16. The method of claim 11, wherein performing DLL circuit tracing according to the first calibration mode includes performing continuous DLL circuit tracing when the memory device is in an active operating state, an idle state, and a fast standby state, and disabling DLL circuit tracing when the memory device is in a slow standby state.

17. The method of claim 11, wherein performing DLL circuit tracing in the second calibration mode includes performing DLL circuit tracing in conjunction with an impedance calibration ZQCal operation command.

18. The method of claim 11, further comprising storing configuration settings for DLL calibration mode in a mode register.

19. A computer-readable medium having instructions stored thereon, which, when executed, cause the method according to any one of claims 11-18 to be performed.

20. An apparatus for controlling the calibration of input / output I / O circuitry of a memory device, comprising: A component used to determine from register settings whether delay-locked loop (DLL) calibration is selectively enabled to control DLL circuit tracking of the I / O circuit; A component for selecting from multiple calibration modes when DLL calibration is enabled, including selecting from a first calibration mode to enable continuous DLL circuit tracing and selecting from a second calibration mode to enable tracing of the DLL circuit only in response to a command; as well as A component used to perform DLL circuit tracing according to the selected calibration mode. The components for performing DLL circuit tracing according to the first calibration mode include components for performing continuous DLL circuit tracing when the memory device is in an active operating state and in an idle state, and for disabling DLL circuit tracing when the memory device is in a standby state.

21. The apparatus of claim 20, wherein the memory device comprises a three-dimensional 3D stacked memory device.

22. The apparatus of claim 21, wherein the memory device comprises a 3D cross-point 3DXP memory device.

23. The apparatus of claim 20, wherein the component for performing DLL circuit tracing includes a component for selectively and dynamically enabling DLL calibration at runtime of the memory device.

24. The apparatus of claim 20, wherein the component for performing DLL circuit tracing in accordance with the second calibration mode includes a component for performing DLL circuit tracing only in response to a command from the associated host controller.

25. The apparatus of claim 20, wherein the component for performing DLL circuit tracing according to the first calibration mode includes a component for performing continuous DLL circuit tracing when the memory device is in an active operating state, an idle state, and a fast standby state, and for disabling DLL circuit tracing when the memory device is in a slow standby state.

26. The apparatus of claim 20, wherein the component for performing DLL circuit tracing in accordance with the second calibration mode includes a component for performing DLL circuit tracing in conjunction with an impedance calibration ZQCal operation command.

27. The apparatus of claim 20, further comprising a component for storing configuration settings for DLL calibration mode in a mode register.

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