Single-ended sensitive amplification circuit based on variable capacitance

Abstract

The application discloses a single-ended sensitive amplification circuit based on a variable capacitor, which comprises a switching circuit, a cross-coupled auxiliary amplification circuit and a variable capacitor. The switching circuit comprises a first NMOS tube and a second NMOS tube. The cross-coupled auxiliary amplification circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube and a third NMOS tube. The variable capacitor is realized by using an NMOS tube with an intrinsic doping layer, which is referred to as a fourth NMOS tube. A gate of the fourth NMOS tube is one end of the variable capacitor, which is recorded as a capacitor node SAN. A source of the fourth NMOS tube is connected with a drain of the fourth NMOS tube, and a connection end thereof is the other end of the variable capacitor. The other end of the variable capacitor is used for connecting an enable signal SA. The single-ended sensitive amplification circuit based on the variable capacitor has the advantages that single-ended output can be realized, the storage density of SRAM can be effectively improved, special process support is not needed, the circuit can be realized by using a general CMOS process, and the process cost is relatively low.

Description

Technical Field

[0001] This invention relates to a single-ended sensitive amplifier circuit, and more particularly to a single-ended sensitive amplifier circuit based on a variable capacitor. Background Technology

[0002] Sensitive amplifier circuits are crucial in Static Random Access Memory (SRAM), primarily amplifying the data on the bit lines. For differential output memory arrays, the high sensitivity of the differential sensitive amplifier circuit allows for the identification of small voltage differences between bit line pairs. Therefore, SRAM arrays (consisting of multiple subarrays) typically support a large number of memory cells per differential bit line pair, reaching 64 or 128, ensuring high SRAM storage density. However, for single-ended output memory arrays, the inability to use universal differential sensitive amplifier circuits necessitates a multi-stage single-ended dynamic bit line output strategy. This results in a significantly smaller number of memory cells per single-ended bit line, typically 8 or 16, severely impacting SRAM storage density. Therefore, developing single-ended sensitive amplifier circuits for single-ended output memory arrays to improve SRAM storage density is a pressing issue.

[0003] Currently, the sensitive amplifier circuit technology proposed for SRAM mainly focuses on differential sensitive amplifier circuits, with a small number of single-ended sensitive amplifier circuits. For example, Sharifkhani M et al., in the journal "IEEE Trans. Very Large Scale Integration," proposed a hybrid sensitive amplifier circuit with a differential structure, which combines voltage-type and current-type latching sensitive amplifier circuits, achieving almost "0" quiescent current. Nambu H et al., at the International Solid-State Circuit Conference (ISSCC), proposed a current-mirror differential sensitive amplifier that can amplify very small read currents. Authors Qazi M et al. proposed a single-ended sensitive amplifier circuit for single-ended 8-transistor SRAM in the international solid-state circuit journal "Journal Solid-State Circuit (JSSC)". This circuit effectively increases the storage density of 8T-SRAM, with 256 memory cells mounted on the local bitline (LBL), achieving an SRAM capacity of 512Kb. Its operating voltage range is 1.2V to 0.57V, with a fastest data readout time of 400ps and a read operation speed of 3.4ns at 0.57V. While this single-ended sensitive amplifier circuit effectively increases the storage density of 8T-SRAM, it employs a special SOI process, and the coupling capacitors are thick-gate oxide MOSFET capacitors, with each capacitor having an area of ​​4μm. 2 It is not suitable for general CMOS processes.

[0004] The first and second sensitive amplifier circuits mentioned above only support differential output and cannot achieve single-ended amplification output. Therefore, they cannot be used in single-ended output memory arrays to improve the storage density of SRAM. Although the third sensitive amplifier circuit can achieve single-ended output and effectively improve the storage density of SRAM, it requires special process support and has a relatively high process cost. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a single-ended sensitive amplifier circuit based on a variable capacitor that can achieve single-ended output, effectively improve the storage density of SRAM, and does not require special process support. It can be implemented using general CMOS process with relatively low process cost.

[0006] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a single-ended sensitive amplifier circuit based on a variable capacitor, comprising a switching circuit, a cross-coupled auxiliary amplifier circuit, and a variable capacitor; the switching circuit includes a first NMOS transistor and a second NMOS transistor, the gate of the first NMOS transistor is the control terminal of the switching circuit, used to connect the column select signal SEL, the drain of the first NMOS transistor is the input terminal of the switching circuit, used to connect to the global bit line GRBL of the SRAM, the source of the first NMOS transistor and the drain of the second NMOS transistor are connected, and their connection terminal is the output terminal of the switching circuit, the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is the clock terminal of the switching circuit, used to connect the clock signal CLKN; the cross-coupled auxiliary amplifier circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a third NMOS transistor, the sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to a power supply, the first PMOS transistor... The gate of the S-channel MOSFET, the drain of the second PMOS transistor, the drain of the third PMOS transistor, and the drain of the third NMOS transistor are connected, and their connection point is the output terminal of the cross-coupled auxiliary amplifier circuit, used to connect to the subsequent dynamic latch. The drain of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the third PMOS transistor, and the gate of the third NMOS transistor are connected, and their connection point is the input terminal of the cross-coupled auxiliary amplifier circuit. The source of the third NMOS transistor is grounded. The variable capacitor is implemented using an intrinsically doped NMOS transistor, referred to as the fourth NMOS transistor. The gate of the fourth NMOS transistor is one end of the variable capacitor, denoted as capacitor node SAN. The source and drain of the fourth NMOS transistor are connected, and their connection point is the other end of the variable capacitor. The other end of the variable capacitor is used to connect to the enable signal SA, which is a pulse signal. The output terminal of the switching circuit and the input terminal of the cross-coupled auxiliary amplifier circuit are both connected to the capacitor node SAN.

[0007] The enable signal SA enters the other end of the variable capacitor through a first inverter and a second inverter. The input terminal of the first inverter is connected to the enable signal SA, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the other end of the variable capacitor. In this structure, the enable signal SA entering the other end of the variable capacitor through the first and second inverters can cause the charge of the capacitor node SAN to have a high skew, enabling the charge of the capacitor node SAN to be transferred quickly and improving the data reading speed.

[0008] Compared with the prior art, the advantages of this invention lie in constructing a single-ended sensitive amplifier circuit based on a variable capacitor through a switching circuit, a cross-coupled auxiliary amplifier circuit, and a variable capacitor. The switching circuit includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor is the control terminal of the switching circuit, used to connect the column select signal SEL. The drain of the first NMOS transistor is the input terminal of the switching circuit, used to connect to the global bit line GRBL of the SRAM. The source of the first NMOS transistor and the drain of the second NMOS transistor are connected, and their connection terminal is the output terminal of the switching circuit. The source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is the clock terminal of the switching circuit, used to connect the clock signal CLKN. The cross-coupled auxiliary amplifier circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a third NMOS transistor. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the power supply. The gate of the OS transistor, the drain of the second PMOS transistor, the drain of the third PMOS transistor, and the drain of the third NMOS transistor are connected, and their connection point is the output of the cross-coupled auxiliary amplifier circuit, which is used to connect to the subsequent dynamic latch. The drain of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the third PMOS transistor, and the gate of the third NMOS transistor are connected, and their connection point is the input of the cross-coupled auxiliary amplifier circuit. The source of the third NMOS transistor is grounded. The variable capacitor is implemented using an intrinsically doped NMOS transistor, which is called the fourth NMOS transistor. The gate of the fourth NMOS transistor is one end of the variable capacitor, denoted as the capacitor node SAN. The source and drain of the fourth NMOS transistor are connected, and their connection point is the other end of the variable capacitor. The other end of the variable capacitor is used to connect the enable signal SA, which is a pulse signal. The output of the switching circuit and the input of the cross-coupled auxiliary amplifier circuit are both connected to the capacitor node SAN.When a single-ended sensitive amplifier circuit is used in an SRAM with a single-ended output memory array, the input of the switching circuit is connected to the global bit line GRBL of the SRAM. Each subarray of the single-ended output memory array in the SRAM is connected to the global bit line GRBL via a local bit line. Each subarray carries several memory cells. When the single-ended sensitive amplifier circuit performs a data read operation on the SRAM, it selects the memory cell of the corresponding column under the control of the column selection signal SEL. The voltage difference of the local bit lines of the SRAM changes, which causes a small voltage change in the global bit line GRBL. This voltage change in the global bit line GRBL is transmitted to the capacitor node SAN through the switching circuit, causing a change in the voltage of the capacitor node SAN. This voltage change in the capacitor node SAN causes the fourth NMOS transistor to turn on, thereby causing a change in the capacitance of the variable capacitor, enabling the signal. SA utilizes the coupling effect of capacitors to amplify the voltage of the capacitor node SAN in the first stage. If the voltage of the capacitor node SAN is greater than or equal to the switching threshold of the cross-coupled auxiliary amplifier circuit, the cross-coupled auxiliary amplifier circuit is activated, performing a second stage of amplification of the voltage of the capacitor node SAN, amplifying it to a high level and outputting a logic "0" to the subsequent dynamic latch for data storage. If the voltage of the capacitor node SAN is less than the switching threshold of the cross-coupled auxiliary amplifier circuit, the cross-coupled auxiliary amplifier circuit is turned off, outputting a "1" to the subsequent dynamic latch for data storage. This achieves single-ended amplification and output of data. Therefore, this invention can achieve single-ended output, effectively improving the storage density of SRAM, and does not require special process support; it can be implemented using general CMOS technology, resulting in relatively low process costs. Attached Figure Description

[0009] Figure 1 This is a circuit diagram of a first embodiment of the single-ended sensitive amplifier circuit based on a variable capacitor according to the present invention;

[0010] Figure 2 This is a circuit diagram of a second embodiment of the single-ended sensitive amplifier circuit based on a variable capacitor according to the present invention. Detailed Implementation

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0012] Example 1: A single-ended sensitive amplifier circuit based on a variable capacitor, comprising a switching circuit 300, a cross-coupled auxiliary amplifier circuit 500, and a variable capacitor; the switching circuit 300 includes a first NMOS transistor 301 and a second NMOS transistor 302, the gate of the first NMOS transistor 301 is the control terminal of the switching circuit 300, used to connect the column select signal SEL, the drain of the first NMOS transistor 301 is the input terminal of the switching circuit 300, used to connect to the global bit line GRBL of the SRAM, and the source of the first NMOS transistor 301 and the second NMOS transistor 302... The drain of transistor 302 is connected, and its connection terminal is the output terminal of switching circuit 300. The source of the second NMOS transistor 302 is grounded, and the gate of the second NMOS transistor 302 is the clock terminal of switching circuit 300, used to input the clock signal CLKN. The cross-coupled auxiliary amplifier circuit 500 includes a first PMOS transistor 501, a second PMOS transistor 502, a third PMOS transistor 503, and a third NMOS transistor 504. The sources of the first PMOS transistor 501, the second PMOS transistor 502, and the third PMOS transistor 503 are all connected to the power supply. The source, the gate of the first PMOS transistor 501, the drain of the second PMOS transistor 502, the drain of the third PMOS transistor 503, and the drain of the third NMOS transistor 504 are connected, and their connection point is the output terminal of the cross-coupled auxiliary amplifier circuit 500, used to connect to the subsequent dynamic latch. The drain of the first PMOS transistor 501, the gate of the second PMOS transistor 502, the gate of the third PMOS transistor 503, and the gate of the third NMOS transistor 504 are connected, and their connection point is the input terminal of the cross-coupled auxiliary amplifier circuit 500. The third NMOS transistor 504... The source of 4 is grounded; the variable capacitor is implemented using an intrinsically doped NMOS transistor, which is called the fourth NMOS transistor 401. The gate of the fourth NMOS transistor 401 is one end of the variable capacitor, denoted as the capacitor node SAN. The source and drain of the fourth NMOS transistor 401 are connected, and their connection point is the other end of the variable capacitor. The other end of the variable capacitor is used to connect the enable signal SA, which is a pulse signal; the output of the switching circuit 300 and the input of the cross-coupled auxiliary amplifier circuit 500 are both connected to the capacitor node SAN.

[0013] When the single-ended sensitive amplifier circuit of this embodiment is used in an SRAM with a single-ended output memory array, the input terminal of the switching circuit 300 is connected to the global bit line GRBL of the SRAM. Each subarray of the single-ended output memory array in the SRAM is connected to the global bit line GRBL through a local bit line. Each subarray carries several memory cells. When the single-ended sensitive amplifier circuit performs a data read operation on the SRAM, it selects the memory cell of the corresponding column under the control of the column selection signal SEL. The voltage difference of the local bit line of the SRAM changes, which causes a small voltage change in the global bit line GRBL. The voltage change of the global bit line GRBL is transmitted to the capacitor node SAN through the switching circuit 300, causing a change in the voltage of the capacitor node SAN. The voltage change of the capacitor node SAN causes... When the fourth NMOS transistor 401 is turned on, the capacitance of the variable capacitor changes. The enable signal SA uses the coupling effect of the capacitor to amplify the voltage of the capacitor node SAN in the first stage. If the voltage of the capacitor node SAN is greater than or equal to the switching threshold of the cross-coupled auxiliary amplifier circuit 500, the cross-coupled auxiliary amplifier circuit 500 is activated to amplify the voltage of the capacitor node SAN in the second stage, amplifying the voltage of the capacitor node SAN to a high level and outputting a logic "0" to the subsequent dynamic latch for data storage. If the voltage of the capacitor node SAN is less than the switching threshold of the cross-coupled auxiliary amplifier circuit 500, the cross-coupled auxiliary amplifier circuit 500 is turned off and outputs a "1" to the subsequent dynamic latch for data storage, thereby realizing single-ended amplified output of data.

[0014] Example 2: This example is basically the same as Example 1, except that: in this example, the enable signal SA enters the other end of the variable capacitor through the first inverter F1 and the second inverter F2. The input terminal of the first inverter F1 is connected to the enable signal SA. The output terminal of the first inverter F1 is connected to the input terminal of the second inverter F2. The output terminal of the second inverter F2 is connected to the other end of the variable capacitor.

[0015] In this embodiment, the enable signal SA enters the other end of the variable capacitor through the first inverter F1 and the second inverter F2, which can make the charge of the capacitor node SAN have a high skew, so that the charge of the capacitor node SAN can be transferred quickly and the data reading speed can be improved.

Claims

1. A single-ended sensitive amplifier circuit based on a variable capacitor, characterized in that... The system includes a switching circuit, a cross-coupled auxiliary amplifier circuit, and a variable capacitor. The switching circuit includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor serves as the control terminal of the switching circuit, used to connect to the column select signal SEL. The drain of the first NMOS transistor is the input terminal of the switching circuit, used to connect to the global bit line GRBL of the SRAM. The source of the first NMOS transistor and the drain of the second NMOS transistor are connected, and their connection point serves as the output terminal of the switching circuit. The source of the second NMOS transistor is grounded, and its gate serves as the clock terminal of the switching circuit, used to connect to the clock signal CLKN. The cross-coupled auxiliary amplifier circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a third NMOS transistor. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to a power supply. The gate of the first PMOS transistor and the drain of the second PMOS transistor... The drain of the third PMOS transistor and the drain of the third NMOS transistor are connected, and their connection point is the output terminal of the cross-coupled auxiliary amplifier circuit, used to connect to the subsequent dynamic latch. The drain of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the third PMOS transistor, and the gate of the third NMOS transistor are connected, and their connection point is the input terminal of the cross-coupled auxiliary amplifier circuit. The source of the third NMOS transistor is grounded. The variable capacitor is implemented using an intrinsically doped NMOS transistor, referred to as the fourth NMOS transistor. The gate of the fourth NMOS transistor is one end of the variable capacitor, denoted as capacitor node SAN. The source and drain of the fourth NMOS transistor are connected, and their connection point is the other end of the variable capacitor. The other end of the variable capacitor is used to connect to the enable signal SA, which is a pulse signal. The output terminal of the switching circuit and the input terminal of the cross-coupled auxiliary amplifier circuit are both connected to the capacitor node SAN.

2. The single-ended sensitive amplifier circuit based on a variable capacitor according to claim 1, characterized in that... The enable signal SA enters the other end of the variable capacitor through the first inverter and the second inverter. The input terminal of the first inverter is connected to the enable signal SA. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the other end of the variable capacitor.

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