Semiconductor package substrate, method of manufacturing the same, semiconductor package, and method of manufacturing the same

Abstract

A semiconductor package substrate and a manufacturing method thereof are provided. The semiconductor package substrate includes a base layer including a conductive material, having a first surface and a second surface opposite to the first surface, and having a first recess or a first groove at the first surface and a second recess or a second groove at the second surface; a first resin buried in the first recess or the first groove at the first surface of the base layer; and a recess portion at at least one inflection point of the first surface of the base layer, and a depth of the first surface is 1 / 2 or more of a thickness of the base layer.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging substrate, a method for manufacturing the same, a semiconductor package and a method for manufacturing the same, and more specifically, to a method for manufacturing an easily solderable semiconductor packaging substrate, a semiconductor packaging substrate manufactured using the method, and a method for manufacturing the same. Background Technology

[0002] Semiconductor devices are packaged in semiconductor packaging substrates, which have fine circuit patterns and / or input / output (I / O) terminals. With the increasing performance and / or high integration of semiconductor devices, and the miniaturization and / or high performance of electronic devices using them, the linewidth of the fine circuit patterns on semiconductor packaging substrates has become narrower, and their complexity has increased.

[0003] Existing semiconductor packaging substrates are manufactured through a process that involves forming vias using a copper clad laminate (CCL) stacked with copper foil. The inner surfaces of the vias are plated to electrically connect the top copper foil to the bottom copper foil, and then photoresist is used to pattern the top and bottom copper foils. However, this existing semiconductor packaging substrate manufacturing method suffers from complex manufacturing processes and low precision.

[0004] Therefore, in order to simplify the manufacturing process, a method for manufacturing semiconductor packaging substrates by filling a conductive substrate layer with an insulating material has recently been introduced. Summary of the Invention

[0005] The objective of this invention is to provide an easily solderable semiconductor packaging substrate and a method for manufacturing the same. However, these issues are exemplary, and the scope of the invention is not limited thereto.

[0006] According to one aspect of the present invention, a semiconductor packaging substrate is provided, comprising: a substrate layer including a conductive material and having a first surface and a second surface opposite to the first surface, and having a first groove or trench located on the first surface and a second groove or trench located on the second surface; a first resin embedded in the first groove or trench located on the first surface of the substrate layer; and a groove portion located at at least one inflection point on the first surface of the substrate layer, and having a depth based on the first surface that is 1 / 2 or greater than the thickness of the substrate layer.

[0007] In this embodiment, the depth of the groove can be 100 μm or greater.

[0008] In this embodiment, the thickness of the base layer corresponding to the groove portion can be 35 μm or greater.

[0009] In this embodiment, the width of the base layer based on the first surface corresponding to the groove portion can be 30 μm or more larger than the width of the groove portion based on the second surface.

[0010] In this embodiment, a coating may be further included, which is disposed on the surface of the base layer other than the first resin.

[0011] In this embodiment, at least a portion of the first resin can be exposed to the outside through the groove.

[0012] In this embodiment, a second resin may be further included, which is embedded in the second groove or trench located on the second surface of the substrate layer.

[0013] In this embodiment, the width of the base layer based on the first surface corresponding to the groove portion can be the same as the width of the groove portion based on the second surface.

[0014] According to another aspect of the present invention, a semiconductor package is provided, comprising: a semiconductor package substrate; and a semiconductor chip mounted on the semiconductor package substrate.

[0015] According to another aspect of the present invention, a method for manufacturing a semiconductor packaging substrate is provided, comprising: preparing a substrate layer made of a conductive material having a first surface and a second surface; forming a first groove or a first trench on the first surface of the substrate layer; filling the first groove or the first trench with a first resin; curing the first resin; removing exposed portions of the first resin that are overfilled in the first groove or the first trench; forming a second groove or a second trench on the second surface of the substrate layer to expose at least a portion of the first resin filled in the first groove or the first trench; and forming a third groove on the first surface of the substrate layer, wherein the depth of the third groove is 1 / 2 or greater than the thickness of the substrate layer.

[0016] In this embodiment, the formation of the second groove or second trench of the base layer can be performed simultaneously with the formation of the third groove.

[0017] In this embodiment, the third groove may have a width along the first direction and a length along the second direction intersecting the first direction, and the width of the cutting area may be less than the length of the third groove.

[0018] In this embodiment, the depth of the third groove can be 100 μm or greater.

[0019] In this embodiment, the thickness of the base layer corresponding to the third groove can be formed to be 35 μm or greater.

[0020] In this embodiment, the width of the base layer corresponding to the third groove, as observed from the second surface side, can be formed based on one side being equal to or greater than the width of the third groove as observed from the first surface side.

[0021] In this embodiment, at least a portion of the first resin can be exposed to the outside through the third groove.

[0022] In this embodiment, between forming the second groove or trench on the second surface of the substrate layer to expose at least a portion of the resin filling the first groove or trench, and forming the third groove on the first surface of the substrate layer, it may further include filling the second groove or trench with the second resin.

[0023] In this embodiment, the width of the base layer based on the first surface corresponding to the third groove can be the same as the width of the third groove based on the second surface.

[0024] In this embodiment, between forming the third groove on the first surface of the substrate layer and cutting the substrate layer along a cutting region passing through the center of the third groove, it may further include: plating the surface of the substrate layer exposed through the first surface and the second surface to form a coating.

[0025] According to another aspect of the present invention, a semiconductor packaging manufacturing method is provided, which further includes: mounting a semiconductor chip on a semiconductor packaging substrate; and cutting the semiconductor packaging substrate along the third groove.

[0026] Other aspects, features, and advantages beyond the foregoing will become more apparent from the following drawings, claims, and detailed description of the invention.

[0027] These general and specific aspects can be implemented using systems, methods, computer programs, or any combination of systems, methods, and computer programs. Attached Figure Description

[0028] Figures 1 to 5 This is a cross-sectional view schematically illustrating some processes of a method for manufacturing a semiconductor packaging substrate according to an embodiment of the present invention.

[0029] Figure 6 yes Figure 5 Back view of the semiconductor packaging substrate. Figure 7 It roughly shows along Figure 6A cross-sectional view of the third groove H3 intercepted by line A-A'. Figure 8 It roughly shows along Figure 6 A cross-sectional view of the third groove H3 cut by the B-B' line.

[0030] Figure 9 This is a cross-sectional view schematically illustrating some processes of a method for manufacturing a semiconductor packaging substrate according to an embodiment of the present invention.

[0031] Figures 10 to 12 This is a schematic cross-sectional view showing the manufacturing process of forming a semiconductor package using a semiconductor packaging substrate after the semiconductor packaging substrate has been formed.

[0032] Figures 13A to 13C This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor packaging substrate according to another embodiment of the present invention.

[0033] Figure 14 This is a schematic cross-sectional view of a semiconductor package including a semiconductor packaging substrate according to an embodiment of the present invention.

[0034] Figure 15 This is a perspective view schematically showing a recessed portion of a semiconductor packaging substrate according to an embodiment of the present invention.

[0035] Figure 16 This is a schematic cross-sectional view of a semiconductor package including a semiconductor packaging substrate according to an embodiment of the present invention. Detailed Implementation

[0036] Because this invention allows for various modifications and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the specification. The effects and features of the invention, as well as the methods for achieving these effects and features, will become more apparent with reference to the embodiments described in detail below and the accompanying drawings. However, the invention is not limited to the embodiments disclosed below, but can be implemented in various forms.

[0037] In the following description, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and in the description with reference to the drawings, the same reference numerals will be assigned to the same or corresponding constituent elements, and repeated descriptions thereof will be omitted.

[0038] In this specification, the terms "first," "second," etc., are used to distinguish one constituent element from other constituent elements, rather than having a limiting meaning.

[0039] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0040] In this specification, the terms "comprising" or "having" mean the presence of the features or constituent elements described in this specification, and do not preclude the possibility of adding at least one other feature or constituent element.

[0041] In this specification, when it is said that a part such as a membrane, region, or constituent element is located on or above another part, it includes not only that it is directly above the other part, but also that another membrane, region, or constituent element is interposed between it and the other part.

[0042] In this invention, when referring to connections such as membranes, regions, or constituent elements, it includes direct connections between membranes, regions, or constituent elements, and / or indirect connections between membranes, regions, or constituent elements. For example, in this specification, when referring to electrical connections such as membranes, regions, or constituent elements, it includes direct electrical connections between membranes, regions, or constituent elements, and / or indirect electrical connections between membranes, regions, or constituent elements.

[0043] In this specification, "A and / or B" means A, or B, or A and B. Furthermore, "at least one of A and B" means A, or B, or A and B.

[0044] In this specification, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system, and can be interpreted in a general sense. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but can also refer to different directions that are not orthogonal to each other.

[0045] In this specification, a particular process sequence may be performed differently than the described sequence, where certain embodiments can be implemented differently. For example, two processes described consecutively may be performed actually simultaneously, or may be performed in the reverse order of the described sequence.

[0046] In the accompanying drawings, for ease of illustration, the dimensions of the constituent elements may be enlarged or reduced. For example, for ease of illustration, the dimensions and thickness of each component shown in the drawings are arbitrarily shown, and therefore the invention is not necessarily limited to those shown.

[0047] Figures 1 to 5 This is a cross-sectional view schematically illustrating some processes of a method for manufacturing a semiconductor packaging substrate according to an embodiment of the present invention.

[0048] First, refer to Figure 1According to the manufacturing method of the semiconductor packaging substrate 10 of this embodiment, a substrate layer 100 made of a conductive material is prepared. The substrate layer 100 may have a flat plate shape including the conductive material. The conductive material may include Fe alloys such as Fe, Fe-Ni, and Fe-Ni-Co, and Cu alloys such as Cu, Cu-Sn, Cu-Zr, Cu-Fe, and Cu-Zn.

[0049] The base layer 100 is plate-shaped and may have a first surface 100a and a second surface 100b opposite to each other. The first surface 100a is the surface that is set to face the ground and serve as the back surface, and the second surface 100b is the surface that is opposite to the first surface 100a and serves as the top surface.

[0050] As an example, the thickness T0 of the substrate 100 can be from about 100 μm to 500 μm, for example, from about 185 μm to 200 μm.

[0051] Then, refer to Figure 2 A first groove or trench H1 is formed on the first surface 100a of the substrate layer 100. Here, the first groove or trench H1 refers to a groove that does not completely penetrate the substrate layer 100. Although Figure 2 It is a cross-sectional view, so it is not shown, but in the plan view, the remaining portion except for the first groove or first trench H1 of the first surface 100a of the base layer 100 can be understood as a wiring pattern extending or meandering along a predetermined direction.

[0052] To form this first groove or trench H1, a dry film resist (DFR) made of a photosensitive material is laminated onto the first surface 100a of the substrate 100, and processes such as exposure and development are performed to expose only the portion of the substrate 100 where the first groove or trench H1 will be formed. Then, the portions of the first surface 100a of the substrate 100 not covered by the DFR are etched using an etching solution such as copper chloride or ferric chloride, thereby forming the first groove or trench H1. Figure 2 As shown, the first groove or trench H1 formed on the first surface 100a can be formed so as not to penetrate the base layer 100.

[0053] The remaining portion of the first surface 100a of the substrate layer 100 that has not been removed, i.e., the portion other than the first groove or the first trench H1, can be used later as a wiring pattern. Therefore, preferably, when the first groove or the first trench H1 is formed on the first surface 100a of the substrate layer 100, the width of the portion between adjacent grooves or between trenches is the width of a conventional wiring pattern, i.e., about 20 μm to 30 μm.

[0054] like Figure 2As shown, preferably, when the first groove or first trench H1 is formed on the first surface 100a of the substrate 100, the depth of the first groove or first trench H1 is about 80% to 90% of the thickness of the substrate 100, but the present invention is not necessarily limited thereto.

[0055] When the depth of the first groove or trench H1 is greater than its depth, it may be difficult to manipulate the substrate 100 or the semiconductor packaging substrate during the manufacturing process of the semiconductor packaging substrate or during subsequent packaging processes. Additionally, in some cases, when the depth of the first groove or trench H1 is greater than its depth, due to tolerances in forming the first groove or trench H1, vias penetrating the first surface 100a and the second surface 100b of the substrate 100 may be formed. Simultaneously, when the depth of the first groove or trench H1 is less than its depth, subsequent processes may be difficult to execute during the later manufacturing of the semiconductor packaging substrate, or the final manufactured semiconductor packaging substrate may be too thin.

[0056] As one embodiment, an etching solution can be used to etch a substrate layer 100 containing copper (Cu) or copper alloy (Cu-alloy) as the main component by a spray coating method. In this case, the first surface 100a is half-etched to achieve the target shape in the copper (Cu) or copper alloy (Cu-alloy) material. Furthermore, preferably, to prevent material deformation and penetration of the substrate layer 100 due to etching, the remaining thickness T1 of the substrate layer 100 corresponding to the first groove or first trench H1 is formed to be at least 35 μm or greater.

[0057] Then, refer to Figure 3 The first groove or trench H1 of the substrate layer 100 is filled with the first resin 110. It is sufficient if the first resin 110 is made of a non-conductive insulating material. For example, the first resin 110 may be a thermosetting resin polymerized and cured by heat treatment. This first resin 110 is used for later electrical insulation between wiring patterns on the semiconductor packaging substrate. The filling of the first resin 110 can be performed using a liquid substance, or using a solid colloid comprising components of the first resin 110, or using a powder containing resin components.

[0058] Meanwhile, although not shown, in order to promote the adhesion between the first resin 110 and the inner surface H1-IS of the first groove or trench H1, a process can be added before filling the first resin 110 to increase the surface roughness or surface area of ​​the entire surface by using chemical methods (e.g., plating, etching, etc.) or physical methods (e.g., grinding, etc.). Thus, the first resin 110 filled in the first groove or trench H1 of the first surface 100a can have high uniformity (less void) and excellent adhesion.

[0059] Specifically, before filling the first groove or first trench H1 of the substrate layer 100 with the first resin 110, the inner surface of the first groove or first trench H1 can be roughened. This significantly increases the adhesion between the first resin 110 and the substrate layer 100. The roughening of the inner surface of the first groove or first trench H1 of the substrate layer 100 can be achieved by using plasma treatment, ultraviolet treatment, or a hydrogen peroxide / sulfuric acid-based solution. In this case, the roughness of the inner surface of the first groove or first trench H1 of the substrate layer 100 can be 150 nm or greater.

[0060] After filling with the first resin 110, the temperature is increased, and a curing process is performed. In particular, in the case of liquid resin, the residence time in the horizontal zone can be increased to prevent the resin from dripping during the curing process.

[0061] Then, refer to Figure 4 When the first resin 110 is over-coated, the over-coated first resin 110 can be removed.

[0062] In the first resin 110, such as Figure 3 As shown, the first resin 110 can not only fill the first groove or first trench H1 of the substrate layer 100, but also cover at least a portion of the first surface 100a of the substrate layer 100. At this time, by removing the first resin 110 that is over-coated on the first surface 100a, the first resin 110 is made to be located only inside the first groove or first trench H1 of the substrate layer 100.

[0063] The over-coated first resin 110 can be removed by mechanical processing such as laser, brushing, grinding or polishing, or by chemical etching of the first resin 110. Thus, as a portion of the first resin 110 covering at least a portion of the first surface 100a of the substrate 100 is removed, the first surface 100a of the substrate 100 can be exposed to the outside again.

[0064] Of course, the removal of excessive coating of the first resin 110 can be omitted. In other words, when filling the first resin 110, it can be considered that, for example... Figure 4 The first groove or trench H1 of the base layer 100 is filled only, instead of as shown Figure 3 The overfilling is shown. However, in this case, the first groove or trench H1 of the base layer 100 may not be properly filled by the first resin 110.

[0065] Then, refer to Figure 5The second groove or second trench H2 is formed by etching the second surface 100b of the substrate layer 100, so that the first resin 110 filling the first groove or first trench H1 is exposed.

[0066] The second surface 100b of the substrate layer 100 can be etched using various methods. Generally speaking, it can be done with, for example... Figure 2 The method for etching the first surface 100a of the substrate 100 is the same. For example, a DFR made of a photosensitive material is laminated onto the second surface 100b of the substrate 100, and processes such as exposure and development are performed to expose only the portion of the second surface 100b of the substrate 100 to be etched. Then, the portions of the second surface 100b of the substrate 100 not covered by the DFR are etched using an etching solution such as copper chloride or ferric chloride, thereby revealing the portion of the substrate 100 not covered by the DFR. Figure 5 As shown, at least a portion of the first resin 110 is exposed on the second surface 100b of the substrate layer 100.

[0067] Through the above process, the first conductive pattern 102 between the first resins 110 also appears on the first surface 100a of the substrate layer 100, and the second conductive pattern 104 between the first resins 110 also appears on the second surface 100b of the substrate layer 100. In the case of a semiconductor packaging substrate, the second conductive pattern 104 on the second surface 100b is electrically connected to the first conductive pattern 102 on the first surface 100a. Therefore, the conductive layer patterning of the second surface 100b and the conductive layer patterning of the first surface 100a must be performed according to a preset procedure.

[0068] At the same time, a third groove H3 is formed on the first surface 100a of the base layer 100.

[0069] This third groove H3 can be formed in the portion where the first groove or trench H1 is not formed, i.e., between the first groove or trench H1. During manufacturing, the third groove H3 is formed after the first resin 110 is filled into the first groove or trench H1; therefore, it can be understood that the third groove H3 is formed between the portions where the first resin 110 is formed. This third groove H3 can be used as a wettable flank structure to facilitate subsequent soldering of the semiconductor package.

[0070] In this embodiment, the third groove H3 is also formed in a manner that does not completely penetrate the substrate layer 100, similar to the first groove or the first trench H1. As one embodiment, the depth D of the third groove H3 can be formed to be approximately 100 μm or greater. As will be described in detail later, the third groove H3 serves as a wettable flank structure for bonding the semiconductor packaging substrate to a printed circuit board (PCB). Figure 16 Therefore, very preferably, to improve the reliability of the welded structure and facilitate the process, the depth D of the third groove H3 in the weld area is formed to be 100 μm or greater. However, in another embodiment, when the original thickness T0 of the substrate 100 is about 185 μm or less, the depth D of the third groove H3 can be formed to be about half the thickness T0 of the substrate 100. Thus, the semiconductor packaging substrate can ensure sufficient solder wettability.

[0071] The third groove H3 is formed to correspond to the cutting area CA. For example, the third groove H3 can be formed along one direction (e.g., the y direction) and another direction perpendicular to the one direction (e.g., the x direction).

[0072] Figure 6 yes Figure 5 Back view of the semiconductor packaging substrate. Figure 7 It roughly shows along Figure 6 A cross-sectional view of the third groove H3 intercepted by line A-A'. Figure 8 It roughly shows along Figure 6 A cross-sectional view of the third groove H3 cut by the B-B' line.

[0073] Refer to together Figure 5 and Figure 6 The third groove H3 can be formed to correspond to the cutting area CA. The third groove H3 can be defined as having a length L3 along one direction (e.g., the y direction) and a width W3 along another direction (e.g., the x direction).

[0074] At this point, the length L3 of the third groove H3 is formed to be greater than the width Wc of the dicing region CA. If the length L3 of the third groove H3 is equal to or less than the width Wc of the dicing region CA, it is important that the length L3 of the third groove H3 is greater than the width Wc of the dicing region CA, since the third groove H3 cannot be used as a wettable sidewall structure after dicing the semiconductor package substrate.

[0075] The width Wc of the cutting region CA is defined by the cutting line CA1 and the cutting tolerance CA2. Since the cutting tolerance CA2 is located on both sides of the cutting line CA1, the cutting region CA satisfies the following [Mathematical Equation 1].

[0076] [Mathematical Expression 1]

[0077] The width Wc of the cutting area CA = the width of the cutting line CA1 + the width of the cutting tolerance CA2 * 2. Therefore, the length L3 of the third groove H3 can be defined as follows [Mathematical Formula 2].

[0078] [Mathematical Expression 2]

[0079] The length L3 of the third groove H3 = the width Wc of the cutting area CA × the width WF of the groove * 2

[0080] The depth D of the third groove H3 can be defined as the maximum value of the depth D of the groove portion WF excluding the cutting area CA. Figure 7 The grooved portion WF can be used as a wettable wing structure after the semiconductor packaging substrate is cut.

[0081] Reference Figure 8 The depth D of the groove WF can be defined as Figure 8 The maximum value of WF in the groove shown.

[0082] As one embodiment, the depth D of the groove portion WF can be formed to be about 100 μm or more. In another embodiment, when the original thickness T0 of the substrate layer 100 is about 185 μm or less, the depth D of the third groove H3 can be formed to be about half the thickness T0 of the substrate layer 100. In summary, when the original thickness T0 of the substrate layer 100 exceeds about 185 μm, the depth D of the groove portion WF can be formed to be about 100 μm or more; when the original thickness T0 of the substrate layer 100 is about 185 μm or less, the depth D of the groove portion WF can be formed to be about half the thickness T0 of the substrate layer 100. That is, when the original thickness T0 of the substrate layer 100 is about 185 μm or less, if the depth D of the groove portion WF is formed to be about 100 μm or more, the remaining thickness T of the substrate layer 100 corresponding to the groove portion WF will be too thin, making it difficult to perform subsequent processes.

[0083] Meanwhile, the remaining thickness T of the base layer 100 corresponding to the groove portion WF can be approximately 35 μm or greater. This value may refer to the minimum remaining thickness T of the base layer 100. In other words, the semiconductor packaging substrate can only undergo subsequent processes if the remaining thickness T of the base layer 100 is ensured to be approximately 35 μm or greater. If the remaining thickness T of the base layer 100 is approximately 35 μm or less, the likelihood of defects is high because the semiconductor packaging substrate is cut in subsequent processes, or the third groove H3 penetrates the base layer 100.

[0084] As one embodiment, the width W2 of the substrate layer 100 as observed from the second surface 100b side can be formed to be greater than the width W3 of the third groove H3 as observed from the first surface 100a side, and the tolerance W1 can be at least 30 μm or greater based on one side. That is, the width W2 of the substrate layer 100 as observed from the second surface 100b side can be formed to be 30 μm or greater than the width W3 of the third groove H3 as observed from the first surface 100b side.

[0085] Since the semiconductor packaging substrate according to an embodiment of the present invention has a structure in which resin is filled in corresponding portions by a two-stage etching process of etching both sides, the width W3 of the third groove H3 reduces the possibility of penetrating the substrate layer 100, thereby achieving a maximum depth substantially similar to the width W2 (land width) of the second surface 100b. Therefore, it is possible for at least a portion of the first resin 110 to be exposed by the third groove H3.

[0086] Preferably, in order to prevent penetration or mold leakage caused by etching of both sides of the substrate 100 and misalignment caused by etching of both sides, it is formed such that the width W2 of the second surface 100b, i.e. the width of the lead pad LL, is at least 30 μm or greater on one side.

[0087] At the same time, refer to Figure 5 In a manufacturing method according to an embodiment of the present invention, while forming a second groove or second trench H2 on the second surface 100b of the substrate layer 100, a third groove H3 can be formed on the first surface 100a of the substrate layer 100. In other words, both the second surface 100b and the first surface 100a of the substrate layer 100 can be etched simultaneously. Therefore, no additional process for forming the third groove H3 is required; the third groove H3 can be formed on the first surface 100a of the substrate layer 100 while forming the second groove or second trench H2. This third groove H3 is formed after the substrate layer 100 is filled with a first resin 110, and the area where the third groove H3 is formed is surrounded and locked by the pre-filled first resin 110, thus forming a third groove H3 with the desired width and depth.

[0088] Then, refer to Figure 9The plating layer 120 can be formed on at least a portion of the remaining portion of the substrate layer 100. The plating layer 120 can be formed on the inner surface H3-IS of the third groove H3, and in some cases, it can also be formed on the inner surface of the first surface 100a, second surface 100b, first groove, or first trench H1 of the substrate layer 100, excluding the first resin 110. In particular, the plating layer 120 formed on the inner surface H3-IS of the third groove H3 can improve the solder wettability of the semiconductor packaging substrate 10.

[0089] This coating 120 can be applied using materials such as Au, Pd, NiPd, and Au-Alloy. Simultaneously, organic film coatings such as organic solderability preservers (OSP) or anti-tarnishing methods can be applied to the second surface 100b of the substrate 100.

[0090] As described above, a third groove H3 is formed during the manufacturing process of the semiconductor packaging substrate, which facilitates the soldering of the semiconductor package.

[0091] As a comparison, it can be assumed that during the soldering of the semiconductor packaging substrate, only right-angle inflection points are soldered, or that grooves are formed in the solder joints through a separate process after the semiconductor chip is packaged. However, when only right-angle inflection points are soldered, solder wettability may be significantly reduced, and when grooves are formed in the solder joints through a separate process, metal burrs are generated during the groove formation process, thereby reducing the quality of the semiconductor package.

[0092] Therefore, in the method for manufacturing a semiconductor packaging substrate according to an embodiment of the present invention, when manufacturing the semiconductor packaging substrate, i.e., the lead frame, since a third groove H3 for a wettable side wing structure corresponding to the dicing region CA is formed without performing a separate process, the wettable side wing structure can be effectively formed after the semiconductor chip is packaged without performing additional processes.

[0093] Figures 10 to 12 This is a schematic cross-sectional view showing the manufacturing process of forming a semiconductor package using a semiconductor packaging substrate after the semiconductor packaging substrate has been formed.

[0094] Figures 10 to 12 The process can be the same as the above. Figure 9 The processes can be performed separately or continuously.

[0095] exist Figure 9 Then, refer to Figures 10 to 12The semiconductor chip 130 is installed in the above-mentioned Figures 1 to 9 The semiconductor chip 130 is manufactured on a semiconductor packaging substrate 10 using a manufacturing process. The semiconductor chip 130 can be mounted on a planar portion of the top surface 100b of the semiconductor packaging substrate, and the semiconductor chip 130 can be electrically and physically connected to leads of the substrate layer 100 via wires 140. The wires 140 can be connected to the semiconductor chip 130 and the leads via wire bonding. One side of the wire 140 is attached to the leads, and the other side of the wire 140 is connected to the semiconductor chip 130.

[0096] A molding layer 150 can be formed on a semiconductor chip 130 mounted on a semiconductor packaging substrate 10. The molding layer 150 can serve to seal the semiconductor chip 130 from the outside, and can be formed, for example, as a single-layer molding structure, a double-layer molding structure, or a triple-layer or larger molding structure. This molding layer 150 can be formed, for example, by curing a resin, and can include, for example, at least one of a phosphor and a light diffusing agent. In some cases, a light-transmitting material that does not include a phosphor and a light diffusing agent can be used.

[0097] After the semiconductor chip 130 is mounted on the semiconductor packaging substrate 10, as Figure 11 As shown, the substrate layer 100 is cut. Cutting the substrate layer 100 can be understood as cutting the semiconductor packaging substrate 10 filled with the first resin 110. Figure 8 As shown, the base layer 100 can be cut along the cutting region CA formed by the third groove H3. As described above, the length L3 of the third groove H3 can be formed to be greater than the width Wc of the cutting region CA. Therefore, after cutting, as... Figure 12 As shown, the semiconductor packaging substrate 10 has a recessed portion WF, which is a wettable side wing structure with a recessed inflection point at the lower end. This improves the solder wettability of the semiconductor packaging substrate.

[0098] Figures 13A to 13C This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor packaging substrate according to another embodiment of the present invention.

[0099] As mentioned above Figure 5 The manufacturing process according to this embodiment can be used when it is difficult to form the third groove H3 on the first surface 100a of the substrate layer 100 while simultaneously forming the second groove or second trench H2 on the second surface 100b of the substrate layer 100. That is, in Figures 13A to 13C In this process, the process of forming a second groove or trench H2 on the second surface 100b of the substrate 100 and the process of forming a third groove H3 on the first surface 100a of the substrate 100 can be performed separately. Figures 13A to 13C The process can be used when the thickness T0 of the substrate layer 100 is relatively thin, or as described above. Figure 8 As shown, the tolerance W1 of the third groove H3 and the lead pad LL is difficult to ensure when used in situations where it is difficult to ensure 30μm.

[0100] First, refer to Figure 13A , can Figure 4 After the process is executed Figure 13A .like Figure 4 As shown, after filling the first surface 100a of the base layer 100 with the first resin 110, as Figure 13A As shown, a second groove or second trench H2 can be formed on the second surface 100b of the base layer 100. At this time, compared with the above... Figure 5 Unlike other materials, a third groove H3 is not formed on the first surface 100a of the base layer 100.

[0101] Then, refer to Figure 13B The second groove or trench H2 can be filled with a second resin 112. The second resin 112 can be the same as or different from the first resin 110. The method of filling the second resin 112 can be the same as the method of filling the first resin 110. Although not shown, the excess portion of the second resin 112 can be removed after overfilling.

[0102] In this embodiment, the first resin 110 and the second resin 112 can penetrate the substrate layer 100 and contact each other.

[0103] Then, refer to Figure 13C A third groove H3 can be formed on the third groove region H3-A of the first surface 100a of the base layer 100. The position and shape of the third groove H3 are the same as described above. Figure 5 The same as described above.

[0104] In this embodiment, the width W3 of the third groove H3 and the width W of the lead pad LL are... LL They can be the same. As mentioned above, in Figures 13A to 13C In this process, the process of forming a second groove or trench H2 on the second surface 100b of the substrate 100 and the process of forming a third groove H3 on the first surface 100a of the substrate 100 are performed separately, thereby overcoming design limitations when the thickness T0 of the substrate 100 is thin, or when the tolerance W1 of the third groove H3 and the lead pad LL is difficult to ensure at 30μm.

[0105] This summary primarily describes the manufacturing method of the semiconductor packaging substrate and the method for manufacturing a semiconductor package, but the invention is not limited thereto. For example, a semiconductor packaging substrate manufactured using this semiconductor packaging substrate manufacturing method and a semiconductor package including such a semiconductor packaging substrate also fall within the scope of this invention.

[0106] Figure 14This is a schematic cross-sectional view of a semiconductor package including a semiconductor packaging substrate according to an embodiment of the present invention. Figure 15 This is a perspective view schematically showing a recessed portion of a semiconductor packaging substrate according to an embodiment of the present invention.

[0107] Reference Figure 14 and Figure 15 According to an embodiment of the present invention, a semiconductor packaging substrate 10 includes a base layer 100, a first resin 110 buried in a first surface 100a of the base layer 100, and a recessed portion WF.

[0108] The substrate 100 may have a plate shape comprising a conductive material. The conductive material may include Fe alloys such as Fe, Fe-Ni, and Fe-Ni-Co, and Cu alloys such as Cu, Cu-Sn, Cu-Zr, Cu-Fe, and Cu-Zn. The substrate 100 is plate-shaped and may have a first surface 100a and a second surface 100b opposite to each other.

[0109] A first groove or trench H1 is provided on a first surface 100a of the substrate layer 100, and a first resin 110 can be filled in the first groove or trench H1. The first resin 110 can be filled to the same surface as the first surface 100a of the substrate layer 100, so that the first surface 100a of the substrate layer 100 can form a flat surface.

[0110] The second groove or second trench H2 may be provided on the second surface 100b of the substrate layer 100. The second groove or second trench H2 is etched until a portion of the first resin 110 is formed on the opposite side, and at least a portion of the first resin 110 buried in the first surface 100a may be exposed by the second groove or second trench H2.

[0111] A first conductive pattern 102 is formed on the first surface 100a of the substrate layer 100 through a first groove or trench H1 and a first resin 110 therebetween, and a second conductive pattern 104 appears on the second surface 100b of the substrate layer 100 through a second groove or trench H2 and the first resin 110 exposed therebetween.

[0112] Meanwhile, the groove WF can be located at an inflection point on the first surface 100a of the base layer 100. For example... Figure 15 As shown, the recessed portion WF can be a shape that is recessed towards the substrate 100 from an inflection point of the substrate 100. A plurality of recessed portions WF can be present at an inflection point of the first surface 100a of the substrate 100. As described above, forming recessed portions WF on the semiconductor packaging substrate 10 facilitates the soldering of the semiconductor package.

[0113] As one embodiment, the depth D of the groove portion WF can be 100 μm or greater. In this case, the depth D of the groove portion WF refers to the depth D measured based on the first surface 100a of the substrate layer 100, and can be defined as the maximum depth of the groove portion WF having a semi-circular shape through etching. Therefore, the depth D of the groove portion WF can have a maximum value on the same surface as the side surface 100c of the substrate layer 100.

[0114] In another embodiment, when the original thickness T0 of the substrate 100 is about 185 μm or less, the depth D of the recess WF can be formed to be about half the thickness T0 of the substrate 100. This minimizes defects in the semiconductor packaging substrate process.

[0115] As one embodiment, the remaining thickness T of the base layer 100 corresponding to the recess WF can be about 35 μm or greater. This value can refer to the minimum remaining thickness T of the base layer 100. In other words, the semiconductor packaging substrate can only undergo subsequent processes if the remaining thickness T of the base layer 100 is ensured to be about 35 μm or greater. If the remaining thickness T of the base layer 100 is about 35 μm or less, the likelihood of defects is high because the semiconductor packaging substrate is cut in subsequent processes, or the recess WF penetrates the base layer 100.

[0116] As one embodiment, the width W2' of the substrate layer 100 as observed from the second surface 100b side can be formed to be greater than the width W3' of the groove portion WF as observed from the first surface 100b side, and the tolerance W1 can be at least 30 μm or greater based on one side. That is, the width W2' of the substrate layer 100 as observed from the second surface 100b side can be formed to be 30 μm or greater than the width W3' of the groove portion WF as observed from the first surface 100b side based on one side.

[0117] The plating layer 120 can be disposed on the surface of the substrate layer 100. The plating layer 120 can be formed on the inner surface of the recessed portion WF, and in some cases, it can also be formed on the inner surface of the first surface 100a, the second surface 100b, the first recess, or the first trench H1 of the substrate layer 100, excluding the first resin 110. In particular, the plating layer 120 formed on the inner surface of the recessed portion WF can improve the solder wettability of the semiconductor packaging substrate 10.

[0118] This coating 120 can be applied using materials such as Au, Pd, NiPd, and Au-Alloy. Simultaneously, organic film coatings such as organic solderability preservers (OSP) or anti-tarnishing methods can be applied to the second surface 100b of the substrate 100.

[0119] Meanwhile, the depth D of the groove WF may be reduced due to the plating layer 120, but the thickness of the plating layer 120 is only a few μm, so it is not a factor that substantially affects the depth D of the groove WF. Furthermore, since the plating layer 120 is also formed on the first surface 100a of the substrate layer 100, therefore... Figure 16 As shown, when soldered to a printed circuit board (PCB), the depth D of the recess WF can be compensated based on the thickness formed on the inner surface of the recess WF.

[0120] Figure 16 This is a schematic cross-sectional view of a semiconductor package including a semiconductor packaging substrate according to an embodiment of the present invention.

[0121] Reference Figure 16 This shows that the execution includes Figures 13A to 13C The semiconductor package 20' is formed by the manufacturing process of the semiconductor packaging substrate 10'. Figure 16 The semiconductor packaging substrate 10' and the above Figures 13A to 13C Since they are the same, the repeated descriptions are replaced with the above content.

[0122] The second resin 112 embedded in the second surface 100b of the substrate 100 has the following properties: Figure 16 The second groove or trench H2 is provided on the second surface 100b of the substrate layer 100, and the second resin 112 can be filled in the second groove or trench H2. The second resin 112 can be filled to the same surface as the second surface 100b of the substrate layer 100, so that the second surface 100b of the substrate layer 100 can form a flat surface.

[0123] Furthermore, welding material S can be used to... Figure 16 The semiconductor package 20' is soldered onto the printed circuit board (PCB). The solder material S is formed directly on the recessed portion WF and can directly contact the printed circuit board (PCB).

[0124] Since the semiconductor packaging substrate 10' and the semiconductor package 20' including therethereof have a recessed portion WF with a depth D of 100 μm or greater according to an embodiment of the present invention, the defect rate in the welding process is minimized, thereby achieving efficient and stable welding.

[0125] While the invention has been described with reference to embodiments shown in the accompanying drawings, this description is merely exemplary, and those skilled in the art will understand that various modifications and equivalent embodiments can be implemented according to the invention. Therefore, the true scope of protection of the invention should be determined by the technical concept of the appended claims.

Claims

1. A semiconductor packaging substrate comprising: a substrate layer including a conductive material and having a first surface and a second surface opposite to the first surface, and having a first groove or trench located on the first surface and a second groove or trench located on the second surface; The first resin is embedded in the first groove or the first trench located on the first surface of the substrate layer; as well as A recessed portion, located at at least one inflection point on the first surface of the substrate layer, and having a depth based on the first surface that is 1 / 2 or greater than the thickness of the substrate layer, wherein... At least a portion of the first resin is exposed to the outside through the groove, and The width of the base layer based on the first surface corresponding to the groove is 30% larger than the width of the groove based on the second surface. Or larger.

2. The semiconductor packaging substrate according to claim 1, wherein, The depth of the groove is 100. Or larger.

3. The semiconductor packaging substrate according to claim 1, wherein, The thickness of the base layer corresponding to the groove portion is 35. Or larger.

4. The semiconductor packaging substrate according to claim 1, further comprising: A coating is applied to the surface of the base layer other than the first resin.

5. The semiconductor packaging substrate according to claim 1, further comprising: The second resin is embedded in the second groove or the second trench located on the second surface of the substrate layer.

6. A semiconductor package comprising: a semiconductor package substrate according to any one of claims 1 to 5; and A semiconductor chip, which is mounted on the semiconductor packaging substrate.

7. A method for manufacturing a semiconductor packaging substrate, comprising: Prepare a substrate layer made of conductive material having a first surface and a second surface; A first groove or trench is formed on the first surface of the base layer; The first groove or the first trench is filled with the first resin; Curing the first resin; Remove the exposed portion of the first resin that has been overfilled in the first groove or the first trench; A second groove or trench is formed on the second surface of the substrate layer to expose at least a portion of the first resin filling the first groove or trench; as well as A third groove is formed on the first surface of the base layer, wherein, The depth of the third groove is 1 / 2 or greater than the thickness of the base layer. At least a portion of the first resin is exposed to the outside through the third groove, and The width of the base layer, as observed from the second surface side corresponding to the third groove, is formed such that one side is 30 mm wider than the width of the third groove observed from the first surface side. Or larger.

8. The method for manufacturing a semiconductor packaging substrate according to claim 7, wherein, The formation of the second groove or the second trench of the base layer is performed simultaneously with the formation of the third groove.

9. The method for manufacturing a semiconductor packaging substrate according to claim 7, wherein, The third groove has a width along a first direction and a length along a second direction intersecting the first direction, and, The width of the cutting area is less than the length of the third groove.

10. The method for manufacturing a semiconductor packaging substrate according to claim 7, wherein, The depth of the third groove is 100. Or larger.

11. The method for manufacturing a semiconductor packaging substrate according to claim 7, wherein, Between forming the second groove or trench on the second surface of the substrate layer to expose at least a portion of the resin filling the first groove or trench, and forming the third groove on the first surface of the substrate layer, Further includes: filling the second groove or the second trench with a second resin.

12. The method for manufacturing a semiconductor packaging substrate according to claim 7, wherein, Between forming the third groove on the first surface of the substrate layer and cutting the substrate layer along a cutting region passing through the center of the third groove. Further comprising: depositing a coating onto the surfaces of the substrate layer exposed through the first surface and the second surface.

13. A semiconductor packaging manufacturing method, comprising: Prepare a substrate layer made of conductive material having a first surface and a second surface; A first groove or trench is formed on the first surface of the base layer; The first groove or the first trench is filled with the first resin; Curing the first resin; Remove the exposed portion of the first resin that has been overfilled in the first groove or the first trench; A second groove or trench is formed on the second surface of the substrate layer to expose at least a portion of the first resin filling the first groove or trench; A third groove is formed on the first surface of the base layer; Mounting semiconductor chips onto a semiconductor packaging substrate; and The semiconductor packaging substrate is cut along the third groove, wherein, The depth of the third groove is 1 / 2 or greater than the thickness of the base layer. At least a portion of the first resin is exposed to the outside through the third groove, and The width of the base layer, as observed from the second surface side corresponding to the third groove, is formed such that one side is 30 mm wider than the width of the third groove observed from the first surface side. Or larger.

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