A fan-out packaging structure and forming method thereof

Abstract

The present invention relates to a fan-out packaging structure, comprising: a metal interconnect structure, which includes multiple first insulating layers and multiple metal redistribution layers located in the multiple first insulating layers, and the multiple metal redistribution layers are electrically connected; a metal layer, which is arranged on the side of the metal interconnect structure and connected to the uppermost metal redistribution layer; a second insulating layer, which is located on the front of the metal interconnect structure; an underbump metallization layer, which is electrically connected to the metal redistribution layer; a chip, which is arranged on the underbump metallization layer; an underfill, which is arranged between the chip and the second insulating layer; a plastic encapsulation layer, which plastic encapsulates the metal interconnect structure to the chip; and solder balls, which are arranged on the back of the metal interconnect structure and on the metal layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a fan-out packaging structure and a forming method thereof. Background Art

[0002] With the rapid advancement of integrated circuit technology, IC packaging continues to improve. Chip feature sizes are gradually miniaturizing to meet the demands of Moore's Law. While chip feature sizes are decreasing, the number of electronic components within a chip continues to increase. To realize the functionality of chips in end-products, packaging technologies with compact dimensions and a larger number of output terminals (I / Os) are required. Fan-out packaging technology, with its high density, lightweight design, excellent heat dissipation, and high-frequency performance, is becoming one of the most promising development directions for heterogeneous integration. Fan-out packaging shares the characteristics of wafer-level packaging with the advantages of low cost and high integration density. However, due to the large number of materials involved and its complex structure, its reliability is a key technical issue that hinders its wider application.

[0003] Fan-out packaging structures can cause delamination of the insulation layer during reliability testing or in harsh environments. To improve the reliability of fan-out packaging structures, a new research approach and solution are needed. Summary of the Invention

[0004] The task of the present invention is to provide a fan-out packaging structure and a method for forming the same. By arranging a metal layer on the side of the metal interconnect structure, the insulating layer can be protected, the risk of delamination at the edge of the insulating layer can be reduced, and the delamination expansion can be blocked. In addition, the solder balls arranged on the metal layer can protect the inner circle solder balls and improve the reliability of the inner circle solder balls.

[0005] In a first aspect of the present invention, in order to solve the problems existing in the prior art, the present invention provides a fan-out packaging structure, comprising:

[0006] A metal interconnect structure comprising a plurality of first insulating layers and a plurality of metal redistribution layers located in the plurality of first insulating layers, wherein the plurality of metal redistribution layers are electrically connected;

[0007] a metal layer, arranged on a side of the metal interconnect structure and connected to the uppermost metal redistribution layer;

[0008] a second insulating layer located on the front side of the metal interconnect structure;

[0009] an under-bump metallization layer electrically connected to the metal redistribution layer;

[0010] a chip disposed on the under-bump metallization layer;

[0011] An underfill is arranged between the chip and the second insulating layer;

[0012] a plastic encapsulation layer, which encapsulates the metal interconnect structure to the chip; and

[0013] Solder balls are arranged on the back side of the metal interconnect structure and the metal layer.

[0014] Furthermore, the metal layer covers an edge of the first insulating layer.

[0015] Furthermore, the second insulating layer covers the front surface of the metal interconnect structure and a portion of the metal layer.

[0016] Furthermore, the front side of the chip has bumps, and the chip is flip-chip mounted on the under-bump metallization layer by welding the under-bump metallization layer and the bumps.

[0017] In a second aspect of the present invention, in order to solve the problems existing in the prior art, the present invention provides a method for forming a fan-out packaging structure, comprising:

[0018] Arranging a temporary bonding adhesive on a carrier wafer, forming a metal interconnection structure on the temporary bonding adhesive, and forming a metal layer on a side of the metal interconnection structure, wherein the metal interconnection structure includes a plurality of first insulating layers and a plurality of metal redistribution layers located in the plurality of first insulating layers;

[0019] forming a second insulating layer covering the front surface of the metal interconnect structure and a portion of the metal layer or the entire metal layer;

[0020] forming an under bump metallization layer electrically connected to the metal redistribution layer through the second insulating layer, and then forming a solder layer on the under bump metallization layer;

[0021] Arranging the chip on the under-bump metallization layer and filling underfill between the chip and the second insulating layer;

[0022] Plastic encapsulate the metal interconnect structure to the chip to form a plastic encapsulation layer;

[0023] Thin the plastic layer to expose the back of the chip;

[0024] removing the carrier and temporary bonding adhesive to expose the backside of the metal interconnect structure and a portion of the metal layer; and

[0025] Solder balls are arranged on the back side of the metal interconnect structure and the exposed metal layer.

[0026] Furthermore, the first insulating layer is formed by coating or depositing on the temporary bonding adhesive, and then the first insulating layer is etched to form a circuit pattern, and metal is electroplated on the circuit pattern to form the metal redistribution layer, and the operation is repeated multiple times to obtain a metal interconnection structure.

[0027] Furthermore, in the process of manufacturing the topmost metal redistribution layer, while electroplating the circuit pattern, a metal layer covering the side surfaces of the metal interconnection structure is electroplated and connected to the temporary bonding adhesive.

[0028] Furthermore, the second insulating layer located on the metal redistribution layer is removed by etching to form a hole pattern, and metal is electroplated in the hole pattern to form an under bump metallization layer.

[0029] Furthermore, the front side of the chip has bumps, and the chip is flip-chip mounted on the under-bump metallization layer by welding the under-bump metallization layer and the bumps.

[0030] Furthermore, the method for forming the fan-out packaging structure also includes cutting the plastic-encapsulated wafer to form a single fan-out packaging structure.

[0031] The present invention has at least the following beneficial effects: a fan-out packaging structure and a method for forming the same disclosed in the present invention can protect the insulating layer, reduce the risk of delamination at the edge of the insulating layer, and block the expansion of delamination by arranging a metal layer on the side of the metal interconnection structure; and the solder balls arranged on the metal layer can protect the inner circle solder balls and improve the reliability of the inner circle solder balls; the formation process of the fan-out packaging structure is feasible and consistent with the existing wafer-level fan-out packaging process, without the need to add additional processes and equipment, and the product has higher reliability than existing fan-out packaging products. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope thereof. In the drawings, for clarity, identical or corresponding parts will be represented by the same or similar reference numerals.

[0033] Figure 1 A schematic diagram of a fan-out packaging structure according to an embodiment of the present invention is shown;

[0034] Figures 2A to 2J A cross-sectional schematic diagram shows a process of forming a fan-out packaging structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] It should be noted that components in the drawings may be shown exaggerated for illustrative purposes and are not necessarily true to scale.

[0036] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0037] In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the presence of multiple elements.

[0038] It should also be pointed out that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but a person skilled in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario.

[0039] It should also be pointed out that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the two values ​​are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0040] It should also be noted that in the description of the present invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the present invention. They do not explicitly or implicitly state that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] In addition, the embodiments of the present invention describe the process steps in a specific order, but this is only for the convenience of distinguishing the steps, and does not limit the order of the steps. In different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0042] Figure 1 A schematic diagram of a fan-out packaging structure according to an embodiment of the present invention is shown.

[0043] like Figure 1 As shown, a fan-out package structure includes a metal interconnect structure 101, a metal layer 102, a second insulating layer 103, an under-bump metallization layer 104, a chip 105, an underfill 106, a plastic layer 107 and solder balls 108.

[0044] The metal interconnect structure 101 has a front side and a back side opposite to the front side. The metal interconnect structure 101 includes a plurality of first insulating layers 1011 and metal redistribution layers 1012 located in the plurality of first insulating layers, and the plurality of metal redistribution layers 1012 are electrically connected.

[0045] Metal layer 102 is arranged on the side of metal interconnect structure 101 and is connected to the topmost metal redistribution layer 1012. Metal layer 102 covers the edge of first insulating layer 1011, protecting it, reducing the risk of delamination at the edge of first insulating layer 1011, and preventing the delamination from extending inward. A portion of metal layer 102 is flush with the backside of metal interconnect structure 101 and can serve as a pad for solder balls.

[0046] The second insulating layer 103 is located on the front surface of the metal interconnect structure 101. In one embodiment of the present invention, the second insulating layer 103 covers the front surface of the metal interconnect structure 101 and a portion of the metal layer 102.

[0047] The under bump metallization layer 104 is electrically connected to the metal redistribution layer 1012 , and a portion of the under bump metallization layer 104 is located in the second insulating layer 103 .

[0048] Chip 105 is disposed on underbump metallurgy layer 104. Bumps 1051 are provided on the front surface of chip 105. Chip 105 is flip-chip mounted on underbump metallurgy layer 104 by soldering underbump metallurgy layer 104 to bumps 1051. Solder layer 109 is located between bumps 1051 and underbump metallurgy layer 104. Here, there are two chips. In other embodiments of the present invention, there may be fewer or more chips.

[0049] The underfill 106 is disposed between the chip 105 and the second insulating layer 103. The underfill 106 is used to protect the connection between the bump 1051 and the underbump metallization layer 104.

[0050] The molding layer 107 molds the metal interconnect structure 101 to the chip 105 , wherein the back side of the chip 105 is exposed to the molding layer 107 .

[0051] Solder balls 108 are arranged on the back side of the metal interconnect structure 101 and on the metal layer 102. Solder balls 108 are arranged on the metal redistribution layer 1012 on the back side of the metal interconnect structure 101 and on the portion of the metal layer 102 that is flush with the back side of the metal interconnect structure 101. Because the solder balls 108 arranged on the metal layer 102 are located at the outermost circle of the package, they provide support for the plastic encapsulation area above, which can be used to increase the strength of the package structure and improve the reliability of the solder balls in the inner circle.

[0052] Figures 2A to 2J A cross-sectional schematic diagram shows a process of forming a fan-out packaging structure according to an embodiment of the present invention.

[0053] In step 1, if Figure 2A and 2BAs shown, a temporary bonding adhesive 302 is applied to a carrier wafer 301, a metal interconnect structure 201 is formed on the temporary bonding adhesive 302, and a metal layer 202 is formed on the side of the metal interconnect structure 201. The metal interconnect structure 201 includes a first insulating layer 2011 and a plurality of metal redistribution layers 2012 located within the plurality of first insulating layers 2011, and the plurality of metal redistribution layers 2012 are electrically connected.

[0054] A first insulating layer 2011 is formed on the temporary bonding glue 302 by coating, deposition, and other methods, and then the first insulating layer is etched to form a circuit pattern, and metal is electroplated on the circuit pattern to form a metal redistribution layer 2012. The above steps are repeated many times to obtain a metal interconnection structure 201. Here, the metal interconnection structure 201 is located in the middle area of ​​the temporary bonding glue 302, and the edge of the temporary bonding glue 302 is exposed. In the process of making the topmost metal redistribution layer 2012, while electroplating the circuit pattern, a metal layer 202 covering the side of the metal interconnection structure 201 is electroplated and connected to the temporary bonding glue 302. The metal layer 202 is connected to the topmost metal redistribution layer 2012. The metal layer 202 covers the edge of the first insulating layer 2011, which can protect the first insulating layer 2011, reduce the risk of delamination at the edge of the first insulating layer 2011, and can prevent the delamination from expanding inward.

[0055] In step 2, if Figure 2C and 2D As shown, a second insulating layer 203 is formed to cover the front surface of the metal interconnection structure 201 and a portion of the metal layer 202 or the entire metal layer. The second insulating layer 203 is formed by coating, deposition, or other methods.

[0056] In step 3, if Figure 2E As shown, an under-bump metallization layer 204 is formed to be electrically connected to the metal redistribution layer 2012 through the second insulating layer 203, and then a solder layer 209 is formed on the under-bump metallization layer 204. The second insulating layer 203 located on the metal redistribution layer 2012 is removed by etching to form a hole pattern, and metal is electroplated in the hole pattern to form the under-bump metallization layer 204. A portion of the under-bump metallization layer 204 is located in the second insulating layer 203, and another portion is located above the second insulating layer 203.

[0057] In step 4, if Figure 2FAs shown, a chip 205 is arranged on the UBM layer 204, and an underfill 206 is filled between the chip 205 and the second insulating layer 203. The front side of the chip 205 has bumps 2051. The chip 205 is flip-chip mounted on the UBM layer 204 by soldering the UBM layer 204 to the bumps 2051. A solder layer 209 is located between the bumps 2051 and the UBM layer 204. The underfill 206 is filled between the chip 205 and the second insulating layer 203 through an underfill process. Here, the number of chips is two. In other embodiments of the present invention, there may be fewer or more chips.

[0058] In step 5, if Figure 2G As shown, the wafer is molded to form a molding layer 207. The molding layer 207 molds the metal interconnect structure 201 to the chip 205.

[0059] In step 6, if Figure 2H As shown, the plastic layer 207 is thinned to expose the back side of the chip 205 .

[0060] In step 7, if Figure 2I As shown, the carrier 301 and the temporary bonding adhesive 302 are removed by a debonding process. After the carrier 301 and the temporary bonding adhesive 302 are removed, the back side of the metal interconnect structure 201 and a portion of the metal layer 202 are exposed.

[0061] Step 8, such as Figure 2J As shown, solder balls 208 are placed on the backside of metal interconnect structure 201 and the exposed metal layer 202 through a ball placement process. The inner circle of solder balls 208 are electrically connected to the metal redistribution layer 2012 located on the backside of metal interconnect structure 201 and are considered active solder balls. The solder balls connected to metal layer 202 are located at the outermost circle of the package, providing support for the plastic encapsulation area above, thereby increasing the strength of the package structure and improving the reliability of the inner circle of solder balls.

[0062] Optionally, in step 9, the plastic-encapsulated wafer is cut to form a single fan-out packaging structure.

[0063] The present invention has at least the following beneficial effects: a fan-out packaging structure and a method for forming the same disclosed in the present invention can protect the insulating layer, reduce the risk of delamination at the edge of the insulating layer, and block the expansion of delamination by arranging a metal layer on the side of the metal interconnection structure; and the solder balls arranged on the metal layer can protect the inner circle solder balls and improve the reliability of the inner circle solder balls; the formation process of the fan-out packaging structure is feasible and consistent with the existing wafer-level fan-out packaging process, without the need to add additional processes and equipment, and the product has higher reliability than existing fan-out packaging products.

[0064] Although certain embodiments of the present invention have been described in this application, those skilled in the art will appreciate that these embodiments are provided by way of example only. Numerous variations, alternatives, and modifications will be contemplated by those skilled in the art in light of the teachings of this disclosure without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and are intended to encompass methods and structures within the scope of these claims and their equivalents.

Claims

1. A fan-out packaging structure, comprising: A metal interconnect structure comprising a plurality of first insulating layers and a plurality of metal redistribution layers located in the plurality of first insulating layers, wherein the plurality of metal redistribution layers are electrically connected; a metal layer, arranged on a side of the metal interconnect structure and connected to the uppermost metal redistribution layer; the metal layer covers an edge of the first insulating layer; a second insulating layer located on the front surface of the metal interconnect structure; the second insulating layer covers the front surface of the metal interconnect structure and a portion of the metal layer; an under-bump metallization layer electrically connected to the metal redistribution layer; a chip disposed on the under-bump metallization layer; An underfill is arranged between the chip and the second insulating layer; A plastic encapsulation layer, which encapsulates the metal interconnect structure to the chip; as well as Solder balls are arranged on the back side of the metal interconnect structure and the metal layer.

2. The fan-out packaging structure according to claim 1, wherein: The front side of the chip is provided with bumps, and the chip is flip-mounted on the under-bump metallization layer by welding the under-bump metallization layer and the bumps.

3. A method for forming a fan-out packaging structure, comprising: Arranging a temporary bonding adhesive on a carrier wafer, forming a metal interconnect structure on the temporary bonding adhesive, and forming a metal layer on the side of the metal interconnect structure, wherein the metal interconnect structure includes a plurality of first insulating layers and a plurality of metal redistribution layers located within the plurality of first insulating layers; in the process of forming the topmost metal redistribution layer, while electroplating the circuit pattern, electroplating a metal layer covering the side of the metal interconnect structure and connecting it to the temporary bonding adhesive so that the metal layer covers the edge of the first insulating layer; forming a second insulating layer covering the front surface of the metal interconnect structure and a portion of the metal layer or the entire metal layer; forming an under bump metallization layer electrically connected to the metal redistribution layer through the second insulating layer, and then forming a solder layer on the under bump metallization layer; Arranging the chip on the under-bump metallization layer and filling underfill between the chip and the second insulating layer; Plastic encapsulate the metal interconnect structure to the chip to form a plastic encapsulation layer; Thin the plastic layer to expose the back of the chip; removing the carrier and temporary bonding adhesive to expose the back side of the metal interconnect structure and part of the metal layer; as well as Solder balls are arranged on the back side of the metal interconnect structure and the exposed metal layer.

4. The method for forming a fan-out package structure according to claim 3, wherein: The first insulating layer is formed by coating or depositing on the temporary bonding adhesive, then etching the first insulating layer to form a circuit pattern, and electroplating metal on the circuit pattern to form the metal redistribution layer. The operation is repeated multiple times to obtain a metal interconnection structure.

5. The method for forming a fan-out package structure according to claim 3, wherein: The second insulating layer located on the metal redistribution layer is removed by etching to form a hole pattern, and metal is electroplated in the hole pattern to form an under-bump metallization layer.

6. The method for forming a fan-out package structure according to claim 3, wherein: The front side of the chip is provided with bumps, and the chip is flip-mounted on the under-bump metallization layer by welding the under-bump metallization layer and the bumps.

7. The method for forming a fan-out package structure according to claim 3, wherein: It also includes cutting the plastic-encapsulated wafer to form a single fan-out package structure.

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