Opto-electronic detector for wideband signals

Abstract

The present disclosure relates to semiconductor structures, and more particularly to photodetectors for wideband signals and methods of manufacture. The structure includes a first photodetector, a second photodetector adjacent to the first photodetector, a first air gap of a first size located below the first photodetector configured to detect a first wavelength of light, and a second air gap of a second size located below the second photodetector configured to detect a second wavelength of light.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor structures, and more particularly to photodetectors for wideband signals and methods of manufacture. BACKGROUND

[0002] Photodetectors are devices that precisely convert light into electrical signals, for example for many different types of imaging, sensing, and communication applications. To this end, photodetectors are typically formed using light-sensitive materials (e.g., Si), which are excellent light absorbers. However, in use, photodetectors typically do not absorb all of the light that is shined on them, and in many cases, a significant amount of light can pass completely through the photodetector without being absorbed. This can cause problems in terms of accuracy and efficiency of the device.

[0003] Photodetectors are typically formed using light-sensitive materials (e.g., Si), which are excellent light absorbers. However, in use, photodetectors often need to detect specific wavelengths from a wideband source. This currently requires splitters and demultiplexers, thereby increasing the complexity of the manufacturing process. SUMMARY

[0004] In an aspect of the disclosure, a structure includes a first photodetector, a second photodetector adjacent to the first photodetector, a first air gap of a first size located below the first photodetector configured to detect a first wavelength of light, and a second air gap of a second size located below the second photodetector configured to detect a second wavelength of light.

[0005] In an aspect of the disclosure, a structure includes a first photodetector including a first air gap structure of a first size and an epitaxial material sealing the first air gap structure, a second photodetector including a second air gap structure of a second size and the epitaxial material sealing the second air gap structure, and a shallow trench isolation structure isolating the first photodetector from the second photodetector.

[0006] In an aspect of the disclosure, a method includes forming a first photodetector, forming a second photodetector, forming a first air gap of a first size located below the first photodetector, and forming a second air gap of a second size located below the second photodetector. BRIEF DESCRIPTION OF DRAWINGS

[0007] In the following detailed description, the present disclosure is described, by way of non-limiting example, with reference to the drawings mentioned.

[0008] Figure 1 Structures according to some aspects of the disclosure are shown.

[0009] Figure 2 Multiple trenches patterned in a pad dielectric film and a substrate, and the corresponding manufacturing process, are shown according to some aspects of this disclosure.

[0010] Figure 3 The present disclosure illustrates, among other features, grooves and cavity structures lined with liner material and of different sizes, as well as the corresponding manufacturing processes.

[0011] Figure 4 The grooves for peeling lining material according to some aspects of this disclosure and the corresponding manufacturing process are shown.

[0012] Figure 5 The following are shown: sealing air gap structures of different sizes according to some aspects of this disclosure, among other features, and the corresponding manufacturing processes.

[0013] Figure 6 The present disclosure illustrates, among other features, a doped epitaxial material situated on a sealed air gap structure and a corresponding manufacturing process.

[0014] Figure 7 The contact to the photodetector and the corresponding manufacturing process are shown, among other features, according to some aspects of this disclosure.

[0015] Figure 8 Photodetectors with hermetically sealed air gap structures of different sizes lined with epitaxial material, among other features, are shown according to some aspects of this disclosure, as well as the corresponding manufacturing processes.

[0016] Figure 9 It shows Figure 7 or Figure 8 A top view of the structure. Detailed Implementation

[0017] This disclosure relates to semiconductor structures, and more specifically to photodetectors for broadband signals and methods of manufacturing them. More specifically, this disclosure provides a photodetector capable of detecting different wavelengths from a broadband source. For example, in an embodiment, the photodetector includes multiple Ge photodetectors with air gap structures of different sizes below the photodetectors. Advantageously, the air gap structure below the photodetectors can amplify the desired wavelength, improve specular reflectivity, and can be individually tuned to different wavelengths. Furthermore, the air gap structure below the photodetectors acts as a mirror, allowing for a thinner Ge region required to absorb electromagnetic radiation (e.g., light), i.e., a reduction in Ge thickness of approximately 10-30%.

[0018] In a more specific embodiment, the photodetector includes an underlying air gap structure with a specific curvature, which acts as a spherical mirror, and its dimensions can be varied to amplify a selected wavelength. The air gap structure can consist of a single cavity or a combination of cavities to form an adjustable air gap structure below the photodetector. Multiple air gap structures of different sizes can be used to detect different wavelengths on the same plane. Furthermore, the dimensions of the air gap structure can be designed (tuned) for constructive interference at the desired wavelength, i.e., wavelength tuning.

[0019] For example, air gap structures of different sizes beneath individual photodetectors (e.g., coplanar Ge detectors) can detect light of different wavelengths, with smaller air gap structures detecting shorter wavelengths and larger air gap structures detecting longer wavelengths. Furthermore, different photodetectors and air gap structures can be mixed within a region or isolated in different regions on the same chip. And, the photodetectors can be coplanar (e.g., Ge-based photodetectors).

[0020] The photodetector disclosed herein can be fabricated using a variety of different tools and in a variety of ways. However, typically, methods and tools are used to form structures with micron and nanometer scales. Methods (i.e., techniques) for fabricating the photodetector of this disclosure have been adopted according to integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a material film patterned on top of the wafer by means of a photolithography process. In particular, the fabrication of the photodetector uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithography imaging; and (iii) selectively etching the film onto the mask.

[0021] Figure 1 An introductory structure according to some aspects of this disclosure is illustrated. Specifically, structure 10 includes a substrate 12 comprising any bulk semiconductor material. For example, substrate 12 may be made of any suitable bulk semiconductor material, such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. In an embodiment, substrate 12 may be a p-type substrate having an additional highly doped region 14. The additional doped region 14 includes a p-type dopant, such as boron (B), for the p-type doped region. Undoped semiconductor material 16 may be formed on the doped region 14. In an embodiment, undoped semiconductor material 16 may be intrinsic Si material epitaxially grown on the doped region 14. The undoped semiconductor material 16 effectively buries the doped region 14 deeper into the substrate.

[0022] Still referencing Figure 1One or more pad films 18 can be formed (e.g., deposited) on the undoped semiconductor material 16. As an example, the pad film 18 can be an oxide or a nitride. As an illustrative, non-limiting example, nitrides can be deposited to a thickness of about 100 nm to 200 nm using conventional deposition processes, such as chemical vapor deposition (CVD); while oxides can be deposited to a thickness of about 10 nm. In an embodiment, when the substrate 12 comprises Si material, the oxide can be formed in a furnace oxidation of Si.

[0023] exist Figure 2 In this embodiment, multiple trenches 20a, 20b can be patterned in the pad film 18 and extend into the substrates 12, 16. In an embodiment, the multiple trenches 20a, 20b can have different widths and / or different depths, depending on the wavelength to be detected by the photodetector, as described in more detail herein. In an embodiment, each of the trenches 20a, 20b can extend into the doped region 14, wherein the width and / or depth of trench 20a is smaller than that of trench 20b. In an illustrative, non-limiting example, trenches 20a, 20b can have widths ranging from about 0.1 μm to 0.20 μm and depths ranging from about 0.5 μm to 0.7 μm; although other scales may be contemplated herein based on the specific wavelength to be detected by the photodetector.

[0024] Trench 20a, 20b can be formed using conventional photolithography and etching processes. For example, the resist formed on the pad film 18 is exposed to energy (light) to form a pattern (openings). The openings can have different dimensions to match the different widths (and lengths) of the trenches 20a, 20b. An etching process with selective chemical action, such as reactive ion etching (RIE), will be used to form the trenches 20a, 20b through the resist openings, through the pad film 18, and into the substrate 12. The resist can then be removed by a conventional oxygen ashing process or other known stripping agents.

[0025] refer to Figure 3 A sidewall liner 22 can be formed on the sidewalls of trenches 20a and 20b by depositing a dielectric material and then performing anisotropic etching on the dielectric material at the bottom and top planar features of the trenches 20a and 20b. In embodiments, the sidewall liner 22 can be any suitable dielectric material deposited using any known deposition method (e.g., CVD, thermal oxidation of silicon substrates, atomic layer deposition (ALD), or any combination thereof), such as oxides or nitrides or combinations of dielectric layers. Anisotropic etching includes a re-etching process (RIE) using perfluorinated carbon-based chemicals, which etches material from planar surfaces but leaves dielectric material (e.g., sidewall liner 22) on the sidewalls of trenches 20a and 20b.

[0026] In this embodiment, the sidewall liner 22 should firmly coat the sidewalls of trenches 20a, 20b to protect the underlying substrates 12, 16 (including the highly doped region 14 of substrate 12) from subsequent etching processes (for cavity formation). To achieve this robust sidewall coverage, the dielectric material should be thick enough to leave a film on the sidewalls of trenches 20a, 20b, but not so thick that it pinches off the top opening of trenches 20a, 20b, which would prevent cavity formation during the subsequent cavity etching process.

[0027] like Figure 3 As further shown, cavity structures 24a and 24b can be formed in substrate 12 by etching through the bottoms of trenches 20a and 20b, respectively. The pad film 18 on the substrate surface and the sidewall linings 22 of trenches 20a and 20b protect substrate 12 from unintentional etching during the formation of cavity structures 24a and 24b. Material removal from substrates 12 and 16 can be accomplished using either wet or dry etching processes. For example, dry etchants may include plasma-based CF4, plasma-based SF6, or gaseous XeF4 silicon etching, while wet etching processes may include KOH and NH4OH.

[0028] Because trenches 20a and 20b are used with different dimensions, cavity structures 24a and 24b can have different dimensions. For example, when deeper and / or wider trenches 20b are used, cavity structures 24a and 24b will be wider (and deeper). Similarly, when shallower and / or narrower trenches 20a are used, cavity structures 24a and 24b will be narrower (and shallower). This is because more etchant chemicals can penetrate deeper and / or wider trenches 20b, thus eroding away more substrate material. In an illustrative, non-limiting example, the diameter of cavity structures 24a and 24b can range from approximately 200 nm to 2 μm.

[0029] In this embodiment, prior to cavity formation, any excess dielectric at the bottom of trenches 20a, 20b can be removed using optional gas or liquid HF cleaning, hydrogen plasma, annealing, alkaline or acidic chemical cleaning, or any process known for removing thin or natural dielectrics or residual spacer etch polymers from substrate 12 (e.g., silicon). The back sidewall liner etch cleaning (e.g., anisotropic etching) should leave a robust dielectric liner, such as sidewall liner 22, at the top corners and sidewalls of trenches 20a, 20b to prevent etching of substrate 12 through the sidewalls of trench 16 during cavity formation.

[0030] exist Figure 4In this process, the sidewall liner and pad film can be removed from the structure, thereby exposing the upper surface of the substrate 16 and the sidewalls of trenches 20a, 20b. In embodiments, the sidewall liner and pad film can be removed using conventional etching processes that selectively target these materials. For example, the sidewall liner and pad dielectric film can be removed by thermal phosphorus followed by HF chemical treatment or by HF chemical treatment followed by thermal phosphorus treatment, depending on whether the sidewall liner is a single dielectric layer or a stack of different dielectric layers.

[0031] After removing the sidewall liner and gasket film, trenches 20a and 20b can be optionally annealed to soften or round (bend) the edges of trenches 20a and 20b. In embodiments, annealing can be performed in H2 or other hydrogen atmospheres, which can also remove any native oxides or other oxides from the silicon substrate surface. Annealing can also be provided in other atmospheres, such as NH3, B2H6, Ph3, AsH2, or other gases combined with hydrogen. For example, after an HF pre-cleaning process, the structure can undergo an annealing process for up to about 60 seconds in a temperature range of about 800°C to about 1100°C. If little or no bending is required, the annealing temperature can be reduced, the time shortened, or the hydrogen-based gas flow rate reduced to eliminate or minimize silicon substrate reflow. Therefore, those skilled in the art will understand that curvature can be adjusted by temperature and gas flow.

[0032] In an embodiment, during annealing, the critical scale between the optionally curved silicon at the top of trenches 20a, 20b can be increased by about 20% or more. For example, as a non-limiting illustrative example, for a trench opening of 120 nm, the critical scale of the silicon curvature after annealing can be increased to about 156 nm. This increases the volume at the top opening of trenches 20a, 20b, which effectively allows more material to be deposited and reflowed therein to completely seal the trenches.

[0033] exist Figure 5 In this embodiment, material 26 can be formed on the surface of substrate 16, including the sidewalls of trenches 20a, 20b and the sidewalls of cavity structures 24a, 24b. In this embodiment, material 26 can be an epitaxial Ge or SiGe material deposited using ultra-high vacuum CVD (UHVCVD); although other photodetector semiconductor materials formed in trenches 20a, 20b are contemplated herein. Furthermore, material 26 should have a lower reflow temperature than Si or other materials of substrates 12, 16. In this example, material 26 can be deposited at a temperature of approximately 600°C to 750°C, resulting in a thickness of approximately 100 nm to approximately 1 μm; although other thicknesses of material 26 can be applied depending on the critical scale of trenches 20a, 20b. For example, more material can be deposited with larger trenches.

[0034] like Figure 5As further shown, the wafer is heated to a temperature equal to or greater than the reflow temperature of the material, causing the material to form plugs 26a that fill the tops of the trenches 20a, 20b. Those skilled in the art will understand that the epitaxial Ge or SiGe material (e.g., plugs 26a) has reflective properties that facilitate light reflection and can therefore be used as photodetectors that are coplanar with each other. Plugs 26a also seal the cavity structure, thereby forming sealed air gap structures 24a', 24b'. It is conceivable that some material 26 can be retained as a liner within the sealed air gap structures 24a', 24b'.

[0035] In embodiments, the sealed air gap structures 24a', 24b' can have a diameter ranging from approximately 200 nm to 2 μm. Furthermore, material 26 can be reflowed and seal or plug the trenches 20a, 20b without filling the cavity structures 24a, 24b. For example, the reflow temperature can be 800-1050°C, and the reflow time can be any time up to approximately 600 seconds. Typically, the thickness and other dimensions of the reflow material 26 forming the plug 26a can vary depending on the depth and other dimensions of the trenches 20a, 20b. Illustratively, the plug 26a can be thicker when the trench 20b is deeper, wider when the trench 20b is wider, and longer when the trench 16b is longer. It should also be understood that, depending on the shape of the trenches 20a, 20b, the plug 26a (e.g., photodetector material) can have various shapes, including circular, elliptical, hexagonal, octagonal, square, rectangular, etc.

[0036] exist Figure 6 In this embodiment, an epitaxial semiconductor material 28 can be formed (e.g., grown) on the sealed air gap structures 24a', 24b', i.e., the plug (photodetector material) 26a. In this embodiment, the epitaxial semiconductor material 28 can be an intrinsic Si material having a planar upper surface. An n-doped region 32 can be formed in the epitaxial semiconductor material 28 on the sealed air gap structures 24a', 24b' using an ion implantation process with an n-type dopant (e.g., arsenic (As), phosphorus (P), and Sb, and other suitable examples). Thus, the photodetector can be a PIN photodiode (e.g., comprising p-doped region 14, intrinsic material 16, 28, and n-doped region 32) or an avalanche junction photodetector. Additional p-type doping of the epitaxial semiconductor material 28 is also envisioned for use in forming a PIPN photodiode.

[0037] The epitaxial semiconductor material 28 may also include a p-doped region 30 on one side of the sealed air gap structures 24a', 24b' that contacts the doped region 14. The p-doped region 30 may be formed by an ion implantation process using a p-type dopant (e.g., boron). This allows the contact to be electrically connected from the underside of the structure (e.g., via the contact p-doped region 14) to the photodetector.

[0038] Figure 7 Individual photodetectors 36 separated by shallow trench isolation regions 34 are shown. The shallow trench isolation regions 34 are formed in the epitaxial semiconductor material 28, effectively isolating and separating the individual photodetectors 36. In an embodiment, the individual photodetectors 36 may have a maximum width of about 0.25 μm. The shallow trench isolation structure 34 is formed by conventional photolithography, etching, and deposition processes known to those skilled in the art, and thus this disclosure will be fully understood without further explanation.

[0039] It should be understood that each photodetector 36 includes a p-doped region 14, a sealed air gap structure 24a' or 24b', a photodetector material 26a, intrinsic materials 16 and 28, and an n-doped region 32. Furthermore, those skilled in the art will now understand that the photodetector 36 can detect different wavelengths depending on the size and / or shape of the respective sealed air gap structures 24a' and 24b'.

[0040] Still referencing Figure 7 An interlayer dielectric material 38, such as SiO2, can be formed on the shallow trench isolation structure 34, the n-doped region 32, and the p-doped region 14. The interlayer dielectric material 38 can be deposited using conventional CVD processes. Multiple contacts 40 can be formed in the interlayer dielectric material 38 and electrically connected (e.g., contacts) to the photodetector 36 (e.g., the n-doped region 32 and the p-doped region 14). The contacts 40 can be formed using conventional photolithography, etching, and deposition processes, and therefore this disclosure is fully understood without further explanation. Conventional planarization processes, such as chemical mechanical polishing, can also be performed on the contacts 40.

[0041] Correspondingly sealed air gap structures 24a' and 24b' of different sizes can be used to detect different wavelengths. For example, the etching process used to form the individual cavity structure and subsequently the air gap structures 24a' and 24b' of corresponding sizes can be controlled to provide an optimal radius of curvature for the curved lower surface, used to focus reflected light back onto the lower surface of the photodetector, such as plug 26a. In this way, different sizes of the individual air gap structures 24a' and 24b' provide different absorption characteristics and can therefore be used to detect different wavelengths. Air gap structures of multiple sizes are used for different wavelength detection on the same plane, and each air gap structure can be tuned for constructive interference for the desired wavelength, i.e., wavelength tuning.

[0042] Figure 8 Photodetectors with sealed air-gap structures, each with different dimensions and lined with epitaxial material, are shown, among other features. More specifically, Figure 8The illustrated structure 10a includes sealed air gap structures 24a' and 24b' of different sizes lined with material 26a'. In this embodiment, material 26a' is an epitaxial semiconductor material. More specifically, material 26a' is an epitaxial SiGe material, which can be used in relation to… Figure 5 The process described (i.e., forming the plug 26a for the sealing cavity structure) is performed during this process. The thickness of the material 26a' on the sidewalls of the sealed air gap structures 24a', 24b' can vary depending on the scale of the sealed air gap structures 24a', 24b'. For example, the material thickness can range from about 5 nm to about 100 nm, with thicker material lining larger sealed air gap structures 24b'. As another example, the thickness of the lining material 26a' can depend on the size of the trench opening, with larger trench openings allowing for thicker material lining.

[0043] Figure 9 It shows Figure 7 or Figure 8 This is a top view of the structure. As shown in this view, the contact 40 is eccentric relative to the sealed air gap structures 24a', 24b'. Although shown as circular, those skilled in the art will understand that the sealed air gap structures 24a', 24b' can be elliptical or other shapes described herein. Furthermore, as shown from this angle, shallow grooved insulating materials, such as materials 40, 32, 16, separate the contacts of each sealed air gap structure 24a', 24b'.

[0044] Those skilled in the art will understand that the lower surface of either of the aforementioned air gap structures 24a' and 24b' will reflect paraxial rays passing through the photodetector, thereby improving the light absorption efficiency of the photodetector. This concept is applicable to air gap structures of different sizes. In particular, the lower surface of the respective air gap structures 24a' and 24b' can be configured to have a radius of curvature relative to the center of curvature, such that paraxial rays passing through the photodetector will be reflected from the pole P of the curved lower surface, positioned along the principal axis of the light rays, back to the focal point F based on the focal length of the converging mirror formed by the curved lower surface. According to some aspects of this disclosure, the lower surface can be configured such that the focal point is located at the lower surface of the photodetector. For example, the radius of curvature of the sphere around the center of curvature can be 500 nm, and the focal length of the focal point can be 250 nm. In other words, in this example, the distance between the pole of the curved lower surface and the bottom surface of the photodetector can be 250 nm. Of course, other spacings are conceivable according to this disclosure.

[0045] These photodetectors can be utilized in System-on-Chip (SoC) technology. Those skilled in the art will understand that an SoC is an integrated circuit (also called a “chip”) that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes significantly less power and occupies a much smaller area compared to a multi-chip design with equivalent functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things (IoT).

[0046] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0047] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: The first photodetector is used to detect light of a first wavelength; A second photodetector adjacent to the first photodetector is used to detect light of a second wavelength, which is different from the first wavelength. A first air gap of a first size located below the first photodetector, which can be individually tuned to the first wavelength of light; as well as A second air gap of a second size located below the second photodetector, which can be individually tuned to the second wavelength of light. The first dimension and the second dimension include different scales.

2. The structure according to claim 1, wherein the first dimension and the second dimension include different curvatures at the bottom.

3. The structure according to claim 1 further includes a first groove connected to a first dimension of the first air gap and a second groove connected to a second dimension of the second air gap.

4. The structure of claim 3, wherein a deeper or wider first groove extends into a first air gap having a larger size than the second air gap, and a shallower or narrower second groove extends into a second air gap having a smaller size than the first air gap.

5. The structure according to claim 1, wherein the first air gap and the second air gap are located in a P-doped region of the substrate, the intrinsic semiconductor material is located above the first photodetector and the second photodetector, and the N-doped semiconductor material is located above the intrinsic semiconductor material.

6. The structure according to claim 5 further includes a shallow trench isolation structure extending to the intrinsic semiconductor material and the N-doped semiconductor material of different photodetectors.

7. The structure according to claim 6, further comprising: The first contact of the N-doped semiconductor material connected to the first photodetector; A second contact of the N-doped semiconductor material connected to the second photodetector; And a third contact electrically connected to the P-doped region of the substrate.

8. The structure of claim 1, wherein the first photodetector and the second photodetector each include an epitaxial semiconductor material plug located in a corresponding trench extending into the first air gap and the second air gap.

9. The structure according to claim 1, wherein the first photodetector and the second photodetector comprise a Ge material sealing the first air gap and the second air gap.

10. The structure according to claim 1, wherein the first photodetector and the second photodetector comprise SiGe material sealing the first air gap and the second air gap.

11. A semiconductor structure, comprising: A first photodetector includes a first air gap structure of a first size and an epitaxial material sealing the first air gap structure; A second photodetector includes a second air gap structure of a second size and the epitaxial material sealing the second air gap structure; as well as A shallow trench isolation structure isolates the first photodetector from the second photodetector. The first dimension and the second dimension include different scales.

12. The structure according to claim 11, wherein The first photodetector further includes: Intrinsic semiconductor material located on the epitaxial material sealing the first air gap structure; as well as n-doped semiconductor material located above the intrinsic semiconductor material; and The second photodetector also includes: The intrinsic semiconductor material located on the epitaxial material sealing the second air gap structure; as well as The n-doped semiconductor material located above the intrinsic semiconductor material.

13. The structure according to claim 11 further includes a first groove connected to a first dimension of the first air gap structure and a second groove connected to a second dimension of the second air gap structure.

14. The structure of claim 13, wherein the first trench is deeper or wider than the second trench.

15. The structure of claim 13, wherein the epitaxial material plugs the first trench and the second trench to seal the first air gap structure and the second air gap structure.

16. The structure according to claim 11, wherein the epitaxial material comprises Ge material sealing the first air gap structure and the second air gap structure.

17. The structure according to claim 11, wherein the epitaxial material comprises SiGe material sealing the first air gap structure and the second air gap structure.

18. A method for forming a semiconductor structure, comprising: Form the first photodetector; Form a second photodetector; A first air gap of a first size is formed below the first photodetector; as well as A second air gap of a second size is formed below the second photodetector. The first dimension and the second dimension include different scales.

Images