Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof, the semiconductor device comprising a substrate, a first thin film transistor and a variable resistance memory. The first thin film transistor comprises a first gate, a first stacking structure, a second gate, a source and a drain. The first stacking structure comprises a first metal oxide layer and a second metal oxide layer overlapping each other. The first stacking structure is located between the first gate and the second gate. The variable resistance memory comprises a first electrode, a second stacking structure and a second electrode. The first electrode is electrically connected to the first gate. The second stacking structure comprises a third metal oxide layer and a fourth metal oxide layer overlapping each other. The second stacking structure is located between the first electrode and the second electrode and connects the first electrode and the second electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Since thin-film transistors containing metal oxide semiconductors are easily affected by oxygen, hydrogen and water in the environment, their performance is prone to degradation after long-term use, affecting the electrical properties of the thin-film transistors. For example, in a display device including a thin-film transistor array, if the metal oxide semiconductors of some thin-film transistors experience performance degradation, it is easy to cause the picture displayed by the display device to have an uneven (Mura) problem. Generally speaking, in order to reduce this uneven problem, the pixel circuit is connected to an external chip, and a large amount of current information is stored in an external compensation memory. The above-mentioned current information is calculated by an algorithm to obtain a compensation current or voltage, and then the compensation current or voltage is fed back to the pixel circuit. However, the circuit design of the external chip is complex and the cost is high. Summary of the invention

[0003] The invention provides a semiconductor device, wherein the variable resistance memory has excellent resistance switching performance.

[0004] The invention provides a method for manufacturing a semiconductor device, wherein the variable resistance memory has excellent resistance switching performance.

[0005] At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a first thin film transistor and a variable resistance memory. The first thin film transistor is arranged on the substrate and includes a first gate, a first stacking structure, a second gate, a source and a drain. The first stacking structure includes a first metal oxide layer and a second metal oxide layer overlapping each other. The first stacking structure is located between the first gate and the second gate. The source and the drain are electrically connected to the first stacking structure. The variable resistance memory is arranged on the substrate and includes a first electrode, a second stacking structure and a second electrode. The first electrode is electrically connected to the first gate. The second stacking structure includes a third metal oxide layer and a fourth metal oxide layer overlapping each other. The second stacking structure is located between the first electrode and the second electrode and connects the first electrode to the second electrode.

[0006] At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first gate and a first electrode on a substrate; forming a first gate dielectric layer on the first gate and the first electrode, the first gate dielectric layer having a first opening exposing the first electrode; forming a first stacking structure and a second stacking structure on the first gate dielectric layer, wherein the first stacking structure comprises a first metal oxide layer and a second metal oxide layer overlapping each other, and the second stacking structure comprises a third metal oxide layer and a fourth metal oxide layer overlapping each other, and the third metal oxide layer is filled in the first opening; forming a second gate dielectric layer on the first stacking structure and the second stacking structure, the second gate dielectric layer having a second opening exposing the fourth metal oxide layer; forming a second gate and a second electrode on the second gate dielectric layer, wherein the first stacking structure is located between the first gate and the second gate, and the second electrode is filled in the second opening; forming a source and a drain electrically connected to the first stacking structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0008] FIG. 2A to FIG. 2H yes Figure 1 A schematic cross-sectional view of a method for manufacturing a semiconductor device.

[0009] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0010] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0011] Figure 5 is a schematic diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present invention.

[0012] Figure 6 A display device according to an embodiment of the present invention is Figure 5 Pixel compensation operation flow chart under the pixel circuit setting.

[0013] Description of reference numerals:

[0014] 10A, 10B, 10C: Semiconductor devices

[0015] 100: Substrate

[0016] 110: First gate dielectric layer

[0017] 120: Second gate dielectric layer

[0018] 130: Interlayer dielectric layer

[0019] 2DEG: Two-dimensional electron gas

[0020] 202: First gate

[0021] 204: First electrode

[0022] 212: First metal oxide layer

[0023] 212a: first doping region

[0024] 212c: second doping region

[0025] 214: Third metal oxide layer

[0026] 222,222': Second metal oxide layer

[0027] 222a: Source region

[0028] 222b: Channel area

[0029] 222c: Drain region

[0030] 224: Fourth metal oxide layer

[0031] 232: Second gate

[0032] 234: Second electrode

[0033] 242: Source

[0034] 244: Drain

[0035] a: first node

[0036] b: Second node

[0037] c: The third node

[0038] Cst: Storage capacitor

[0039] EL: Light Emitting Element

[0040] ND: Normal Direction

[0041] P: Doping process

[0042] PX: Pixel circuit

[0043] O1: First opening

[0044] O2: Second opening

[0045] R1: Variable resistance memory

[0046] ST1, ST1': first stacking structure

[0047] ST2: Second stacking structure

[0048] T1: First thin film transistor

[0049] T2: Second thin film transistor

[0050] T3: The third thin film transistor

[0051] t1, t2: thickness

[0052] V1, V2, V3: Open

[0053] V S1 ,V data ,V DD ,V S2 ,V sus ,V SS :Voltage DETAILED DESCRIPTION

[0054] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0055] Please refer to Figure 1 The semiconductor device 10A includes a substrate 100 , a first thin film transistor T1 , and a variable resistance memory R1 .

[0056] The material of the substrate 100 may be glass, quartz, organic polymer, or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyimide (PI) or metal foil or other flexible materials.

[0057] The first thin film transistor T1 and the variable resistance memory R1 are disposed on the substrate 100. In some embodiments, one or more buffer layers (not shown) are further disposed between the first thin film transistor T1 and the substrate 100 and between the variable resistance memory R1 and the substrate 100, but the present invention is not limited thereto. The first thin film transistor T1 includes a first gate 202, a first stacked structure ST1, a second gate 232, a source 242, and a drain 244. The variable resistance memory R1 includes a first electrode 204, a second stacked structure ST2, and a second electrode 234.

[0058] The first gate 202 and the first electrode 204 are disposed on the substrate 100. In one embodiment, the first gate 202 and the first electrode 204 may be an inactive metal that is not easily oxidized and has a high work function, such as tungsten, molybdenum, platinum, palladium, gold, molybdenum / aluminum / molybdenum or a combination thereof. In some embodiments, the first gate 202 and the first electrode 204 include materials of the same or different compositions. In some embodiments, the first gate 202 and the first electrode 204 include the same or different thicknesses. In some embodiments, the first gate 202 and the first electrode 204 belong to the same patterned layer, and the first gate 202 and the first electrode 204 are connected as one.

[0059] The first gate dielectric layer 110 is located on the first gate 202 and the first electrode 204. The first gate dielectric layer 110 covers the first gate 202 and the first electrode 204, and has a first opening overlapping the first electrode 204. The material of the first gate dielectric layer 110 is, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or other suitable materials.

[0060] The first stacked structure ST1 and the second stacked structure ST2 are located on the first gate dielectric layer 110. The first stacked structure ST1 includes a first metal oxide layer 212 and a second metal oxide layer 222 overlapping each other. The second stacked structure ST2 includes a third metal oxide layer 214 and a fourth metal oxide layer 224 overlapping each other.

[0061] The first metal oxide layer 212 overlaps the first gate electrode 202 in the normal direction ND of the top surface of the substrate 100, and the third metal oxide layer 214 overlaps the first electrode 204 in the normal direction ND of the top surface of the substrate 100. The third metal oxide layer 214 fills the first opening of the first gate dielectric layer 110 and is connected to the first electrode 204. In some embodiments, a Schottky contact is formed between the third metal oxide layer 214 and the first electrode 204. In some embodiments, the first metal oxide layer 212 and the third metal oxide layer 214 belong to the same patterned layer.

[0062] The second metal oxide layer 222 and the fourth metal oxide layer 224 overlap the first metal oxide layer 212 and the third metal oxide layer 214 respectively in the normal direction ND of the top surface of the substrate 100. The second metal oxide layer 222 includes a source region 222a, a drain region 222c, and a channel region 222b located between the source region 222a and the drain region 222c, wherein the channel region 222b overlaps the first gate 202 in the normal direction ND. In some embodiments, the source region 222a and the drain region 222c are doped to have a lower resistivity than the channel region 222b. In some embodiments, the fourth metal oxide layer 224 has substantially the same resistivity as the channel region 222b of the second metal oxide layer 222. In some embodiments, the second metal oxide layer 222 and the fourth metal oxide layer 224 belong to the same patterned layer.

[0063] The carrier concentration of the first metal oxide layer 212 is greater than the carrier concentration of the channel region 222b of the second metal oxide layer 222. The oxygen concentration of the first metal oxide layer 212 is less than the oxygen concentration of the channel region 222b of the second metal oxide layer 222. In some embodiments, the oxygen concentration of the first metal oxide layer 212 is 10at% to 50at%, and the oxygen concentration of the channel region 222b of the second metal oxide layer 222 is 30at% to 70at%. In some embodiments, by adjusting the oxygen concentration, the band gap of the first metal oxide layer 212 is smaller than the band gap of the second metal oxide layer 222, thereby forming a two-dimensional electron gas 2DEG at the interface between the first metal oxide layer 212 and the second metal oxide layer 222. The thickness t2 of the second metal oxide layer 222 is less than or equal to the thickness t1 of the first metal oxide layer 212, thereby making it easier for the two-dimensional electron gas 2DEG to form at the aforementioned interface. In some embodiments, the thickness t1 of the first metal oxide layer 212 is 10 nanometers to 50 nanometers, and the thickness t2 of the second metal oxide layer 222 is 5 nanometers to 50 nanometers. In some embodiments, the materials of the first metal oxide layer 212 and the second metal oxide layer 222 include quaternary compounds such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, or ternary compounds including two metal elements among the quaternary compounds and oxygen.

[0064] The carrier concentration of the third metal oxide layer 214 is greater than the carrier concentration of the fourth metal oxide layer 224. The oxygen concentration of the third metal oxide layer 214 is less than the oxygen concentration of the fourth metal oxide layer 224. In some embodiments, the oxygen concentration of the third metal oxide layer 214 is 10 at% to 50 at%, and the oxygen concentration of the fourth metal oxide layer 224 is 30 at% to 70 at%. In some embodiments, applying a voltage to the second stacked structure ST2 can switch the second stacked structure ST2 between states of different resistivities. In other words, the second stacked structure ST2 has a plurality of states of different resistivities. Since the carrier concentration of the third metal oxide layer 214 is different from the carrier concentration of the fourth metal oxide layer 224, the resistivity of different states of the second stacked structure ST2 is gradual. In other words, the variable resistive memory R1 can store single-level cells, multi-level cells, three-level cells, four-level cells, and even analog information. The thickness t2 of the fourth metal oxide layer 224 is less than or equal to the thickness t1 of the third metal oxide layer 214. In some embodiments, the thickness t1 of the third metal oxide layer 214 is 10 nanometers to 50 nanometers, and the thickness t2 of the fourth metal oxide layer 224 is 5 nanometers to 50 nanometers. In some embodiments, the materials of the third metal oxide layer 214 and the fourth metal oxide layer 224 include quaternary compounds such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, or ternary compounds including two metal elements among the quaternary compounds and oxygen.

[0065] The second gate dielectric layer 120 covers the first stack structure ST1 and the second stack structure ST2 and has a second opening overlapping the second stack structure ST2. The material of the second gate dielectric layer 120 is, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide or other suitable materials.

[0066] The second gate 232 and the second electrode 234 are disposed on the second gate dielectric layer 120. The second gate 232 overlaps the channel region 222b of the third metal oxide layer 222 in the normal direction ND of the top surface of the substrate 100. The first stacked structure ST1 is located between the first gate 202 and the second gate 232. The second electrode 234 overlaps the fourth metal oxide layer 224 in the normal direction ND of the top surface of the substrate 100. The second electrode 234 fills the second opening of the second gate dielectric layer 120 and is connected to the fourth metal oxide layer 224. In some embodiments, the second electrode 234 has a Schottky contact with the fourth metal oxide layer 224. The second stacked structure ST2 is located between the first electrode 204 and the second electrode 234, and connects the first electrode 204 and the second electrode 234.

[0067] In one embodiment, the second gate 232 and the second electrode 234 may be an inactive metal that is not easily oxidized and has a high work function, such as tungsten, molybdenum, platinum, palladium, gold, molybdenum / aluminum / molybdenum or a combination thereof. In some embodiments, the second gate 232 and the second electrode 234 include materials of the same or different compositions. In some embodiments, the second gate 232 and the second electrode 234 include the same or different thicknesses. In some embodiments, the second gate 232 and the second electrode 234 belong to the same patterned layer, and the second gate 232 and the second electrode 234 are separated from each other.

[0068] The interlayer dielectric layer 130 is disposed on the second gate 232 and the second electrode 234, and covers the second gate 232 and the second electrode 234. The material of the interlayer dielectric layer 130 is, for example, silicon oxide, silicon nitride, silicon oxynitride or other suitable materials.

[0069] The source 242 and the drain 244 are located on the interlayer dielectric layer 130, and are respectively filled into the openings penetrating the interlayer dielectric layer 130 and the second gate dielectric layer 120 to be electrically connected to the first stacked structure ST1. In some embodiments, the source 242 and the drain 244 are respectively electrically connected to the source region 222a and the drain region 222c of the second metal oxide layer 222. In addition, the source 242 is also filled into the opening penetrating the interlayer dielectric layer 130 to be electrically connected to the second electrode 234.

[0070] Based on the above, the first thin film transistor T1 of the semiconductor device 10A has a two-dimensional electron gas 2DEG, so the output current of the first thin film transistor T1 can be increased. In addition, the second stacked structure ST2 in the variable resistance memory R1 includes a third metal oxide layer 214 and a fourth metal oxide layer 224 with different carrier concentrations, so the variable resistance memory R1 can store analog information. In addition, the first electrode 204 of the variable resistance memory R1 is electrically connected to the first gate 202 of the first thin film transistor T1, so the first gate 202 can be used as a shielding electrode to block the adverse effects of the external electric field on the first thin film transistor T1.

[0071] FIG. 2A to FIG. 2H yes Figure 1 A schematic cross-sectional view of a method for manufacturing a semiconductor device.

[0072] Please refer to Figure 2A, forming a first gate 202 and a first electrode 204 on the substrate 100. In some embodiments, the method of forming the first gate 202 and the first electrode 204 includes the following steps: first, forming a blanket conductive material layer (not shown) on the substrate 100; then, using a photolithography process, forming a patterned photoresist (not shown) on the conductive material layer; then, using the patterned photoresist as a mask, wet or dry etching the conductive material layer to form the first gate 202 and the first electrode 204; then, removing the patterned photoresist. In other words, the first gate 202 and the first electrode 204 are, for example, formed at the same time.

[0073] Please refer to Figure 2B , a first gate dielectric layer 110 is formed on the first gate electrode 202 and the first electrode 204 . The first gate dielectric layer 110 has a first opening O1 exposing the first electrode 204 .

[0074] Please refer to Figure 2C and Figure 2D A first stack structure ST1′ and a second stack structure ST2 are formed on the first gate dielectric layer 110. The first stack structure ST1′ includes a first metal oxide layer 212 and a second metal oxide layer 222′ overlapping each other, and the second stack structure ST2 includes a third metal oxide layer 214 and a fourth metal oxide layer 224 overlapping each other.

[0075] The method of forming the first stack structure ST1′ and the second stack structure ST2 includes: Figure 2C As shown, a first metal oxide layer 212 and a third metal oxide layer 214 are formed on the first gate dielectric layer 110, wherein the third metal oxide layer 214 is filled into the first opening O1 of the first gate dielectric layer 110 to contact the first electrode 204. Figure 2D As shown, the second metal oxide layer 222 ′ and the fourth metal oxide layer 224 are formed on the first metal oxide layer 212 and the third metal oxide layer 214 .

[0076] In some embodiments, the method of forming the first metal oxide layer 212 and the third metal oxide layer 214 includes the following steps: first, a blanket semiconductor material layer (not shown) is formed on the first gate dielectric layer 110; then, a patterned photoresist (not shown) is formed on the semiconductor material layer using a photolithography process; then, the semiconductor material layer is wet or dry etched using the patterned photoresist as a mask to form the first metal oxide layer 212 and the third metal oxide layer 214; then, the patterned photoresist is removed. In other words, the first metal oxide layer 212 and the third metal oxide layer 214 are formed at the same time, for example.

[0077] In some embodiments, the method of forming the second metal oxide layer 222' and the fourth metal oxide layer 224 includes the following steps: first, a blanket semiconductor material layer (not shown) is formed on the first gate dielectric layer 110, the first metal oxide layer 212, and the third metal oxide layer 214; then, a patterned photoresist (not shown) is formed on the semiconductor material layer using a photolithography process; then, the semiconductor material layer is wet or dry etched using the patterned photoresist as a mask to form the second metal oxide layer 222' and the fourth metal oxide layer 224; then, the patterned photoresist is removed. In other words, the second metal oxide layer 222' and the fourth metal oxide layer 224 are, for example, formed simultaneously.

[0078] In other embodiments, the method for forming the first stacked structure ST1' and the second stacked structure ST2 includes a single photolithography and etching process. For example, two blanket semiconductor material layers are formed on the first gate dielectric layer 110; then, a patterned photoresist (not shown) is formed on the semiconductor material layer using a photolithography process; then, the semiconductor material layer is wet or dry etched using the patterned photoresist as a mask to form the first stacked structure ST1' and the second stacked structure ST2; thereafter, the patterned photoresist is removed.

[0079] Please refer to Figure 2E , a second gate dielectric layer 120 is formed on the first stacked structure ST1 ′ and the second stacked structure ST2 , and the second gate dielectric layer 120 has a second opening O2 exposing the fourth metal oxide layer 224 .

[0080] Please refer to Figure 2F , a second gate 232 and a second electrode 234 are formed on the second gate dielectric layer 120 . The second electrode 234 is filled into the second opening O2 of the second gate dielectric layer 120 to contact the fourth metal oxide layer 224 .

[0081] Next, the second metal oxide layer 222′ is subjected to a doping process P using the second gate 232 and the second electrode 234 as masks to form a second metal oxide layer 222 including a source region 222a, a channel region 222b, and a drain region 222c. In some embodiments, the doping process P includes a hydrogen plasma process or an ion implantation process. In this embodiment, since the fourth metal oxide layer 224 is covered by the second electrode 234, the doping process P will not dope the fourth metal oxide layer 224.

[0082] Please refer to Figure 2G, an interlayer dielectric layer 130 is formed on the second gate dielectric layer 120, the second gate electrode 232 and the second electrode 234. In some embodiments, the interlayer dielectric layer 130 is an insulating layer that does not contain hydrogen, thereby preventing hydrogen atoms in the interlayer dielectric layer 130 from diffusing into the first stacked structure ST1 and the second stacked structure ST2, but the present invention is not limited thereto. In some embodiments, the interlayer dielectric layer 130 contains hydrogen atoms, and therefore, the hydrogen atoms can be diffused into the first stacked structure ST1 by heat treatment to adjust the resistivity of the first stacked structure ST1. In some embodiments, when the hydrogen atoms in the interlayer dielectric layer 130 are used to dope the first stacked structure ST1, the step of doping the first stacked structure ST1 can be omitted. Figure 2F The doping process P.

[0083] Please refer to Figure 2H , forming openings V1, V2, and V3, the method includes the following steps: first, using a photolithography process to form a patterned photoresist (not shown) on the interlayer dielectric layer 130; then, using the patterned photoresist as a mask, a wet or dry etching process is performed to form openings V1 and V2 in the interlayer dielectric layer 130 and the second gate dielectric layer 120, and an opening V3 is formed in the interlayer dielectric layer 130; then, the patterned photoresist is removed. The openings V1 and V2 expose the drain region 222c and the source region 222a of the second metal oxide layer 222, respectively, and the opening V3 exposes the second electrode 234.

[0084] Finally, please return Figure 1 , forming a drain 244 and a source 242 on the interlayer dielectric layer 130. The drain 244 and the source 242 are respectively filled into the openings V1 and V2 to electrically connect the drain region 222c and the source region 222a. In addition, the source 242 is also filled into the opening V3 to electrically connect the second electrode 234. In some embodiments, the method for forming the drain 244 and the source 242 includes the following steps: first, forming a blanket conductive material layer (not shown) on the interlayer dielectric layer 130; then, using a photolithography process, forming a patterned photoresist (not shown) on the conductive material layer; then, using the patterned photoresist as a mask, wet or dry etching the conductive material layer to form the drain 244 and the source 242; thereafter, removing the patterned photoresist. In other words, the drain 244 and the source 242 are, for example, formed simultaneously.

[0085] After the above processes, the manufacturing of the active device substrate 10A can be substantially completed.

[0086] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 3 The implementation examples are used Figure 1The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0087] Figure 3 The semiconductor device 10B and Figure 1 The main difference between the semiconductor device 10A and the semiconductor device 10B is that the drain 244 and the source 242 of the semiconductor device 10B extend through the second metal oxide layer 222 .

[0088] Please refer to Figure 3 The drain 244 and the source 242 extend through the second metal oxide layer 222 and contact the interface between the first metal oxide layer 212 and the second metal oxide layer 222. In other words, the drain 244 and the source 242 directly contact the two-dimensional electron gas 2DEG, thereby increasing the output current of the first thin film transistor T1.

[0089] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 4 The implementation examples are used Figure 1 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0090] Figure 4 The semiconductor device 10C and Figure 1 The main difference between the semiconductor device 10A and the semiconductor device 10C is that the first metal oxide layer 212 of the semiconductor device 10C includes a first doping region 212a and a second doping region 212c.

[0091] In the present embodiment, a doping process is performed to form a source region 222a and a drain region 222c in the second metal oxide layer 222, and a first doping region 212a and a second doping region 212c are formed in the first metal oxide layer 212. In other words, dopants (e.g., hydrogen atoms) in the doping process pass through the second metal oxide layer 222 and reach the first metal oxide layer 212, and form the first doping region 212a and the second doping region 212c in the first metal oxide layer 212. The first doping region 212a and the second doping region 212c contact the bottom of the source region 222c and the drain region 222a, respectively.

[0092] In some embodiments, the thickness of the first doping region 212 a and the thickness of the second doping region 212 c are less than the thickness of the first metal oxide layer 212 .

[0093] In some embodiments, the widths of the source region 222a, the drain region 222c, the first doped region 212a, and the second doped region 212c gradually decrease as they approach the substrate 100. The surfaces of the source region 222a and the drain region 222c facing the channel region 222b are arc surfaces.

[0094] Figure 5 is a schematic diagram of an equivalent circuit of a pixel circuit PX according to an embodiment of the present invention. Figure 5 The pixel circuit PX includes, for example, the semiconductor device in any of the aforementioned embodiments.

[0095] Please refer to Figure 5 The pixel circuit PX includes a first thin film transistor T1, a variable resistance memory R1, a second thin film transistor T2, a third thin film transistor T3, a storage capacitor Cst and a light emitting element EL.

[0096] The second thin film transistor T2 can be used as a switch transistor. The gate of the second thin film transistor T2 is electrically connected to the voltage V S1 (for example, a scan line voltage), the drain (or source) of the second thin film transistor T2 is electrically connected to the voltage V data (eg, a data line voltage), the source (or drain) of the second thin film transistor T2 is electrically connected to the first node a.

[0097] The first thin film transistor T1 can be used as a driving transistor. The second gate of the first thin film transistor T1 is electrically connected to the first node a. The drain of the first thin film transistor T1 is electrically connected to the voltage V DD The source of the first thin film transistor T1 is electrically connected to one end (second electrode) of the variable resistance memory R1. The first gate of the first thin film transistor T1 and the other end (first electrode) of the variable resistance memory R1 are electrically connected to the second node b.

[0098] The third thin film transistor T3 can be used as a sensing transistor, for example. The gate of the third thin film transistor T3 is electrically connected to the voltage V S2 The drain of the third thin film transistor T3 is electrically connected to the third node c, and the source of the third thin film transistor T3 is electrically connected to the voltage V sus Voltage V S2 It is used to control the switch of the third thin film transistor T3 so as to transmit the information of the driving current to the external chip through the third thin film transistor T3.

[0099] One end of the storage capacitor Cst is electrically connected to the first node a, and the other end of the storage capacitor Cst is electrically connected to the third node c. The second node b is electrically connected to the third node c. Since the second gate of the first thin film transistor T1 is electrically connected to the storage capacitor Cst, even if the second thin film transistor T2 is turned off, the first thin film transistor T1 can still be turned on for a short period of time.

[0100] One end of the light emitting element EL is electrically connected to the second node b, and the other end of the light emitting element EL is electrically connected to the voltage V SS The brightness of the light emitting element EL will change due to the different magnitudes of the driving current passing through the first thin film transistor T1. The light emitting element EL is, for example, a micro light emitting diode, an organic light emitting diode or other light emitting elements.

[0101] In the present embodiment, at the first node a, the source (or drain) of the second thin film transistor T2, the second gate of the first thin film transistor T1, and one end of the storage capacitor Cst are electrically connected to each other. At the second node b, the first gate of the first thin film transistor T1 and the other end of the variable resistance memory R1 are electrically connected to each other. At the third node c, the drain of the third thin film transistor T3 and the other end of the storage capacitor Cst are electrically connected to each other. The drain of the third thin film transistor T3 is electrically connected to the other end of the variable resistance memory R1 and the first gate of the first thin film transistor T1 through the third node c and the second node b.

[0102] Figure 6 A display device according to an embodiment of the present invention is Figure 5 Pixel compensation operation flow chart under the pixel circuit setting.

[0103] The following briefly describes the operation mode of pixel compensation of the display device under the setting of the pixel circuit PX. Please also refer to Figure 5 and Figure 6 First, the display device is in a closed state, so that the pixel circuit PX performs gray level sensing in the background. The gray level sensing method is, for example, to turn on the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3, so that the driving current passing through the first thin film transistor T1 can be transmitted to the external chip through the third semiconductor element T3.

[0104] Next, the external chip establishes a corresponding model through signal processing and calculation, and then calculates the corresponding compensation information. After that, the compensation information is written into the pixel circuit PX. For example, the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are turned on to write the compensation information calculated by the external chip into the variable resistance memory R1. Specifically, the resistance value of the variable resistance memory R1 is changed by the voltage difference between the first electrode and the second electrode of the variable resistance memory R1.

[0105] Next, the display device is turned on. Since the compensation information has been written into the variable resistance memory R1, the magnitude of the driving current through the first thin film transistor T1 and the variable resistance memory R1 can be adjusted, thereby achieving the function of pixel compensation. In some embodiments, when the display device is turned on, the third thin film transistor T3 is in an off state.

[0106] In summary, the variable resistance memory R1 of the present invention has the function of a memory, so there is no need to set a compensation memory in an external chip, which simplifies the overall system and reduces the cost. In addition, since the variable resistance memory R1 can store analog information, the driving current of pixels at different positions can be adjusted more finely to improve the problem of uneven picture.

Claims

1. A semiconductor device comprising: a substrate; A first thin film transistor is disposed on the substrate and comprises: a first gate; A first stacked structure, comprising a first metal oxide layer and a second metal oxide layer overlapping each other; a second gate, wherein the first stacked structure is located between the first gate and the second gate; and a source and a drain, electrically connected to the first stack structure; and A variable resistance memory is disposed on the substrate and comprises: a first electrode electrically connected to the first grid; a second stacked structure, comprising a third metal oxide layer and a fourth metal oxide layer overlapping each other; and a second electrode, wherein the second stacking structure is located between the first electrode and the second electrode, and the second stacking structure connects the first electrode and the second electrode, A Schottky contact is formed between the second electrode and the fourth metal oxide layer.

2. The semiconductor device as claimed in claim 1, wherein the first electrode is integrally connected to the first gate, and the materials of the first electrode, the second electrode, the first gate and the second gate include tungsten, molybdenum, platinum, palladium, gold, molybdenum / aluminum / molybdenum or a combination thereof. 3 . The semiconductor device as claimed in claim 1 , wherein a carrier concentration of the first metal oxide layer is greater than a carrier concentration of a channel region of the second metal oxide layer. 4 . The semiconductor device as claimed in claim 3 , wherein a two-dimensional electron gas is located at an interface between the first metal oxide layer and the second metal oxide layer. 5 . The semiconductor device as claimed in claim 3 , wherein an oxygen concentration of the first metal oxide layer is less than an oxygen concentration of a channel region of the second metal oxide layer, and a thickness of the second metal oxide layer is less than or equal to a thickness of the first metal oxide layer. 6 . The semiconductor device as claimed in claim 1 , wherein a carrier concentration of the third metal oxide layer is greater than a carrier concentration of the fourth metal oxide layer. 7 . The semiconductor device as claimed in claim 6 , wherein an oxygen concentration of the third metal oxide layer is less than an oxygen concentration of the fourth metal oxide layer, and a thickness of the fourth metal oxide layer is less than or equal to a thickness of the third metal oxide layer. 8 . The semiconductor device as claimed in claim 1 , wherein the first metal oxide layer and the third metal oxide layer belong to the same patterned layer, and the second metal oxide layer and the fourth metal oxide layer belong to another same patterned layer.

9. The semiconductor device according to claim 1, further comprising: a light emitting element electrically connected to the first electrode; as well as A second thin film transistor is electrically connected to the light emitting element and the first electrode. 10 . The semiconductor device as claimed in claim 1 , wherein the thickness of the first metal oxide layer and the third metal oxide layer is 10 nm to 50 nm, and the thickness of the second metal oxide layer and the fourth metal oxide layer is 5 nm to 50 nm.

11. The semiconductor device as claimed in claim 1, wherein the oxygen concentration of the first metal oxide layer and the third metal oxide layer is 10 at% to 50 at%, and the oxygen concentration of a channel region of the second metal oxide layer and the fourth metal oxide layer is 30 at% to 70 at%. 12 . The semiconductor device as claimed in claim 1 , wherein the source is electrically connected to the second electrode.

13. A method for manufacturing a semiconductor device, comprising: forming a first gate and a first electrode on a substrate; Forming a first gate dielectric layer on the first gate and the first electrode, the first gate dielectric layer having a first opening exposing the first electrode; Forming a first stack structure and a second stack structure on the first gate dielectric layer, wherein the first stack structure includes a first metal oxide layer and a second metal oxide layer overlapping each other, and the second stack structure includes a third metal oxide layer and a fourth metal oxide layer overlapping each other, and the third metal oxide layer fills the first opening; forming a second gate dielectric layer on the first stack structure and the second stack structure, wherein the second gate dielectric layer has a second opening exposing the fourth metal oxide layer; forming a second gate and a second electrode on the second gate dielectric layer, wherein the first stacked structure is located between the first gate and the second gate, and the second electrode is filled in the second opening; as well as forming a source and a drain electrically connected to the first stack structure, The first electrode is electrically connected to the first gate. The second stacking structure is located between the first electrode and the second electrode, and the second stacking structure connects the first electrode and the second electrode. 14 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein the first metal oxide layer and the third metal oxide layer are formed simultaneously, and the second metal oxide layer and the fourth metal oxide layer are formed simultaneously.

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