Wiring substrate and electronic device

Abstract

The wiring substrate and electronic device provided by the present disclosure comprise a plurality of pad areas arranged along a first direction, each pad area comprising a plurality of first pad groups and a plurality of second pad groups, the plurality of first pad groups are arranged in a cascade manner along a second direction, one first pad group in the plurality of first pad groups is connected with one second pad group, and the second pad group comprises at least two sub-pad groups connected with each other; wherein each pad area comprises a functional line and a selected pad group, each sub-pad group in the selected pad group is connected with at least one functional line respectively, and one end of all the functional lines is connected with a first trace; the selected pad group is one second pad group closest to a selected side edge in one pad area, and the selected side edge is a side edge extending along the first direction of the wiring substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a wiring substrate and an electronic device. Background Technology

[0002] In recent years, backlighting and display technologies based on ultra-small pitch light-emitting diodes (Mini LED, Micro LED) have developed rapidly. Compared with traditional LCD products, ultra-small pitch light-emitting diode products can achieve local dimming within a smaller area, better brightness uniformity, higher color contrast, and a thinner and lighter product form. Their display effect is basically the same as that of organic light-emitting diodes (OLEDs), but the cost is only 60% of that of OLEDs, and the product lifespan is significantly improved. Based on these advantages, the development of ultra-small pitch light-emitting diodes has been rapid in recent years, and they have a promising market prospect. Summary of the Invention

[0003] This disclosure provides a wiring board and an electronic device, specifically,

[0004] This disclosure provides a wiring substrate, comprising:

[0005] Multiple pad areas are arranged along a first direction, each pad area including multiple first pad groups and multiple second pad groups. The multiple first pad groups are cascaded along a second direction. One of the first pad groups is connected to one of the second pad groups. The second pad group includes at least two interconnected sub-pad groups.

[0006] Each of the pad areas includes a function line and a selected pad group, each sub-pad group in the selected pad group is connected to at least one of the function lines, and one end of all the function lines is connected to a first trace.

[0007] The selected pad group is a second pad group that is closest to the selected side in the pad area, and the selected side is the side of the wiring substrate that extends along the first direction.

[0008] In some embodiments, in the wiring substrate provided in the present disclosure, the number of functional lines in one pad area is one more than the number of sub-pad groups in the selected pad group.

[0009] In some embodiments, the wiring substrate provided in this disclosure further includes a constant voltage signal line and a feedback signal line. Each of the sub-pad groups of the selected pad group is connected in series. The first sub-pad group in the selected pad group is connected to the constant voltage signal line, and the last sub-pad group in the selected pad group is connected to the feedback signal line.

[0010] In some embodiments, in the wiring substrate provided in the present disclosure, the functional line connected to the first sub-pad group is also connected to the constant voltage signal line; the functional line connected to the last sub-pad group is also connected to the feedback signal line.

[0011] In some embodiments, the wiring substrate provided in the present disclosure further includes a first connecting line, wherein two adjacent sub-pad groups in the selected pad group are connected in series through the first connecting line, and each first connecting line is connected to a functional line.

[0012] In some embodiments, the wiring substrate provided in this disclosure further includes a second connecting line, wherein the functional line connected to the last sub-pad group is simultaneously connected to one of the first pad groups through the second connecting line.

[0013] In some embodiments, the wiring substrate provided in this disclosure further includes an insulating layer, the insulating layer including an opening that exposes only the first pad group and the second pad group.

[0014] In some embodiments, in the wiring substrate provided in the present disclosure, one selected pad group is connected to one first trace, or all selected pad groups are connected to the same first trace.

[0015] Based on the same inventive concept, embodiments of this disclosure provide an electronic device, including:

[0016] A wiring substrate includes a plurality of pad areas arranged along a first direction. Each pad area includes a plurality of first pad groups and a plurality of second pad groups. The plurality of first pad groups are cascaded along a second direction. One of the first pad groups is connected to one of the second pad groups. The second pad group includes at least two interconnected sub-pad groups.

[0017] Each of the pad areas includes a function line and a selected pad group, each sub-pad group in the selected pad group is connected to at least one of the function lines, and one end of all the function lines is left unconnected.

[0018] The selected pad group is a second pad group that is closest to the selected side in the pad area, and the selected side is the side of the wiring substrate that extends along the first direction;

[0019] The driver chip is connected to the first pad group;

[0020] Electronic components are connected to the second pad group.

[0021] In some embodiments, in the electronic device provided in the present disclosure, the length of the function line in the second direction is greater than or equal to 1 μm and less than or equal to 30 μm.

[0022] In some embodiments, in the electronic device provided in the present disclosure, the function line is one or any combination of a straight line, a curve, a broken line.

[0023] The beneficial effects of this disclosure are as follows:

[0024] The wiring substrate and electronic device provided in this disclosure include a plurality of pad areas arranged along a first direction. Each pad area includes a plurality of first pad groups and a plurality of second pad groups. The plurality of first pad groups are cascaded along a second direction. One of the first pad groups is connected to a second pad group. The second pad group includes at least two interconnected sub-pad groups. Each pad area includes a functional line and a selected pad group. Each sub-pad group in the selected pad group is connected to at least one functional line. One end of all functional lines is connected to a first trace. The selected pad group is the second pad group closest to the selected side in a pad area. The selected side is the side of the wiring substrate extending along the first direction. The second pad group closest to the selected side is susceptible to electrostatic charge, which can cause parallel plate capacitor breakdown in areas where adjacent traces face each other in the traces connected to the second pad group. By using the second pad group closest to the selected side as the selected pad group, and connecting each sub-pad group in the selected pad group to the first trace using function lines, the static charge on any sub-pad group can be dispersed to each sub-pad group through the first trace and function lines. Therefore, the potential of each sub-pad group in the selected pad group is equal, which makes the potential of the traces connected to each sub-pad group in the selected pad group the same. Therefore, the problem of parallel plate capacitor breakdown will not occur in the area where two adjacent traces have mutually facing surfaces. Attached Figure Description

[0025] Figure 1 These are actual microscope images of short circuits occurring between adjacent traces in related technologies.

[0026] Figure 2 These are actual microscope images of short circuits occurring between adjacent traces in related technologies.

[0027] Figure 3 This diagram serves as a mechanism verification diagram for short circuits occurring between adjacent traces, as provided in an embodiment of this disclosure.

[0028] Figure 4 This diagram serves as a verification of another mechanism for short circuits occurring between adjacent traces, as provided in the embodiments of this disclosure.

[0029] Figure 5The electrostatic breakdown model provided in the embodiments of this disclosure;

[0030] Figure 6 This is a schematic diagram of a wiring substrate provided in an embodiment of the present disclosure;

[0031] Figure 7 This is another schematic diagram of the wiring substrate provided in the embodiments of this disclosure;

[0032] Figure 8 This is another schematic diagram of the wiring substrate provided in the embodiments of this disclosure;

[0033] Figure 9 This is another schematic diagram of the wiring substrate provided in the embodiments of this disclosure;

[0034] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure;

[0035] Figure 11 This is a schematic diagram of the structure of the electronic device before cutting the first trace, as provided in an embodiment of this disclosure. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0037] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0038] In related technologies, the inventors discovered that the pads P of a wiring substrate, including the pads themselves, are exposed portions of the traces and are not covered by an insulating layer. Therefore, during the manufacturing process, static charge can easily be introduced into the wiring substrate from the pads located at the edge of the substrate. Because there are opposing areas between adjacent traces, when static electricity accumulates to a certain level, parallel-plate capacitors can break down the insulating layer, leading to a short circuit between two adjacent traces. Figure 1 and Figure 2 As shown. To investigate the mechanism of the aforementioned short circuit problem, the inventors increased the surface impedance of the pad P exposed at the opening K of the insulating layer (e.g., by treating the pad P through high-temperature calcination, laser sintering, oxidation, etc.), thus preventing the aforementioned short circuit phenomenon. Figure 3 and Figure 4 As shown, static charge is introduced onto pad P through opening K in the insulating layer. However, as the surface impedance of pad P increases, static charge will not accumulate on the surface of pad P, thus preventing a short circuit. Combined with... Figures 1 to 4 An electrostatic discharge (ESD) breakdown model can be derived, where static charges of different polarities accumulate on the surface of pad P through the opening K of the insulating layer. When charges of the same polarity accumulate to a certain amount on the surface of pad P, parallel-plate capacitor breakdown occurs in the region where adjacent traces face each other. Figure 5 As shown, this leads to damage to the insulation layer.

[0039] To address the aforementioned technical problems in related technologies, embodiments of this disclosure provide a wiring substrate, such as... Figure 6 and Figure 7 As shown, it includes:

[0040] Multiple pad areas PA are arranged along a first direction X. Each pad area PA includes multiple first pad groups 101 and multiple second pad groups 102. The multiple first pad groups 101 are cascaded along a second direction Y. One of the first pad groups 101 is connected to one of the second pad groups 102. The second pad group 102 includes at least two interconnected sub-pad groups 21. Optionally, the sub-pad group 21 includes a first pad P that is electrically connected to the pins of a two-pin electronic component (e.g., a light-emitting diode). pad Second pad N pad ;in,

[0041] Each pad area PA includes a function line 103 and a selected pad group 102'. Each sub-pad group 21 in the selected pad group 102' is connected to at least one function line 103. One end of all function lines 103 is connected to the first trace 104.

[0042] The selected pad group 102' is the second pad group 102 closest to the selected side S in a pad area PA, and the selected side S is the side of the wiring substrate extending along the first direction X.

[0043] In the wiring substrate provided in this embodiment, the second pad group 102 closest to the selected side S is susceptible to electrostatic charge, which can cause parallel plate capacitor breakdown in the region where adjacent traces of the multiple traces including the second pad group 102 face each other. By designating the second pad group 102 closest to the selected side S as the selected pad group 102', and connecting each sub-pad group 21 in the selected pad group 102' to the first trace 104 using the function line 103, the electrostatic charge on any sub-pad group 21 can be dispersed to each sub-pad group 21 through the first trace 104 and the function line 103. Therefore, the potential of each sub-pad group 21 in the selected pad group 102' is equal, thereby making the potential of each trace including each sub-pad group 21 in the selected pad group 102' the same. Therefore, the problem of parallel plate capacitor breakdown will not occur in the region where adjacent traces face each other.

[0044] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 6 and Figure 7 As shown, within a pad area PA, the number of function lines 103 is one more than the number of sub-pad groups 21 in the selected pad group 102'. For example, in... Figure 2 Within a pad area PA, the number of function lines 103 is 5, and the number of sub-pad groups 21 in the selected pad group 102' is 4.

[0045] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 6 and Figure 7 As shown, it also includes a constant voltage signal line (VLED) 105 and a feedback signal line (FB) 106. Each sub-pad group 21 of the selected pad group 102' is connected in series. The first sub-pad group 21 in the selected pad group 102' is connected to the constant voltage signal line 105 to provide a drive voltage to the selected pad group 102' through the constant voltage signal line 105. The last sub-pad group 21 in the selected pad group 102' is connected to the feedback signal line 106. Optionally, the feedback signal line 106 is also coupled to the output pad Out of the last stage first pad group 101 in a pad area PA to form a loop for transmitting address signals in a pad area PA.

[0046] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 6 and Figure 7As shown, the function line 103 connected to the first sub-pad group 21 in the selected pad group 102' is also connected to the constant voltage signal line 105; the function line 103 connected to the last sub-pad group 21 in the selected pad group 102' is also connected to the feedback signal line 106. This allows the constant voltage signal line 105 and the feedback signal line 106 to further disperse static charge, preventing excessive accumulation of static charge of the same polarity on a single trace, which could cause parallel plate capacitor breakdown in areas where adjacent traces face each other.

[0047] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 6 and Figure 7 As shown, it also includes a first connecting line 107, through which two adjacent sub-pad groups 21 in the selected pad group 102' are connected in series, and each first connecting line 107 is connected to a function line 103. Compared with connecting each sub-pad group 21 to the first trace 104 separately through different function lines 103, this disclosure connects two series-connected sub-pad groups 21 to a function line 103 through the first connecting line 107, which can effectively reduce the number of function lines 103, simplify the wiring design, and save wiring space.

[0048] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 6 and Figure 7 As shown, it also includes a second connection line 108. The function line 103, which connects to the last sub-pad group 21 in the selected pad group 102', is simultaneously connected to the output pad Out of the last-stage first pad group 101 via the second connection line 108. In this way, the output pad Out of the last-stage first pad group 101 can be used to further disperse static charge, avoiding the problem of parallel plate capacitor breakdown caused by excessive accumulation of static charge of the same polarity on a single trace, which would occur in the area where two adjacent traces have directly facing surfaces.

[0049] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 8 As shown, it also includes an insulating layer 109, which includes an opening K that exposes only the first pad group 101 and the second pad group 102. Optionally, the opening K is connected to each pad of the first pad group 101 (e.g., address pad Di, power supply pad Pwr, output pad Out, ground pad Gnd) and each pad of the second pad group 102 (e.g., the first pad P). pad Second pad N padEach pad is in a one-to-one correspondence with the corresponding pad, and each opening K exposes the central area of ​​the corresponding pad. The first pad group 101 is electrically connected to the driver chip through the pads exposed at the corresponding opening K, and the second pad group 102 is electrically connected to the electronic components through the pads exposed at the corresponding opening K. In the area outside the first pad group 101 and the second pad group 102, the insulating layer 109 can cover the functional line 103, the first trace 104, the constant voltage signal line 105, the feedback signal line 106, the first connection line 107, the second connection line 108, and other signal lines. This not only prevents water and oxygen from corroding the signal lines, but also blocks static charges from entering the wiring substrate through the signal lines and traces.

[0050] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 7 As shown, a selected pad group 102' can be connected to a first trace 104, or, to better distribute static charge, as... Figure 6 As shown, all selected pad groups 102' can be connected to the same first trace 104.

[0051] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 6 , Figure 7 and Figure 9 As shown, the orthographic projection of the selected pad group 102' in the second direction Y at least partially overlaps with the orthographic projection of the constant voltage signal line 105 in the second direction Y; and the orthographic projection of the selected pad group 102' in the second direction Y at least partially overlaps with the orthographic projection of the feedback signal line 106 in the second direction Y, or they do not overlap. Optionally, Figure 6 and Figure 7 The diagram shows that the orthographic projection of the selected pad group 102' in the second direction Y partially overlaps with the orthographic projection of the constant voltage signal line 105 in the second direction Y, and the orthographic projection of the selected pad group 102' in the second direction Y does not overlap with the orthographic projection of the feedback signal line 106 in the second direction Y. Figure 9 This shows that the orthogonal projection of the selected pad group 102' in the second direction Y lies within the orthogonal projection of the constant voltage signal line 105 in the second direction Y, and the orthogonal projection of the selected pad group 102' in the second direction Y lies within the orthogonal projection of the feedback signal line 106 in the second direction Y. Figure 9 In the edge area near the selected side S, a selected pad group 102' and constant voltage signal lines 105 and feedback signal lines 106 on both sides are simultaneously provided. This allows the static charge at the selected side S to be dispersed onto the selected pad group 102' and the constant voltage signal lines 105 and feedback signal lines 106 on both sides, reducing the amount of static charge that may accumulate on the selected pad group 102'. This also reduces the risk of parallel plate capacitor breakdown caused by excessive accumulation of static charge of the same polarity on a single trace.

[0052] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 6 , Figure 7 and Figure 9 As shown, it may also include a common voltage signal line (GND) 110, a power supply line (PWR) 111, a third connection line 112, an address signal line (DI) 113, and a cascade line 114. The ground pads Gnd of all the first pad groups 101 cascaded within a pad area PA are connected to the same common voltage signal line 110. The power supply line 111 is composed of multiple spaced sub-segments 111'. One sub-segment 111' is connected to the power supply pad of one first pad group 101 in a pad area PA. Optionally, two adjacent sub-segments 111' within a pad area PA can be connected to each other through a third connection line 112. Optionally, the third connection line 112 and the sub-segment 111' are an integral structure. Within each pad area PA, the address pad Di of the first-level first pad group 101 is connected to the address signal line 113, the output pad Out of the k-th (k is a positive integer)-level first pad group 101 and the address pad Di of the (k+1)-th level first pad group 101 are connected through the cascading line 114, and the output pad Out of the last-level first pad group 101 is connected to the feedback signal line 106.

[0053] Accordingly, embodiments of this disclosure provide an electronic device, such as... Figure 10 As shown, it includes:

[0054] The wiring substrate 001 includes multiple pad areas PA arranged along a first direction X. Each pad area PA includes multiple first pad groups 101 and multiple second pad groups 102. The multiple first pad groups 101 are cascaded along a second direction Y. One of the first pad groups 101 is connected to one of the second pad groups 102. The second pad group 102 includes at least two interconnected sub-pad groups 21. Each pad area PA includes a function line 103 and a selected pad group 102'. Each sub-pad group 21 in the selected pad group 102' is connected to at least one function line 103. To avoid signal crosstalk, such as... Figure 11 As shown, the first trace 104 can be cut off, so that one end of all functional lines 103 is suspended; the selected pad group 102' is the second pad group 102 closest to the selected side S in a pad area PA, and the selected side S is the side of the wiring substrate extending along the first direction X; the driver chip 002 is connected to the first pad group 101; the electronic component 003 is connected to the second pad group 102.

[0055] In some embodiments, in the electronic devices provided in the present disclosure, such as Figure 10As shown, the length l of the function line 103 in the second direction Y is greater than or equal to 1 μm and less than or equal to 30 μm. Optionally, the function line 103 can be one of a straight line, a curve, a broken line, or any combination thereof. Furthermore, it should be understood that when the function line 103 is a straight line, the length of the function line 103 in its extension direction is equal to its length in the second direction Y; when the function line 103 includes a curve and / or a broken line, the length of the function line 103 in its extension direction is greater than its length in the second direction Y.

[0056] In some embodiments, the electronic device provided in this disclosure can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. This electronic device includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, memory, processor, and power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the electronic device provided in this disclosure; in other words, the electronic device provided in this disclosure may include more or fewer of the aforementioned components, or a combination of certain components, or different component arrangements.

[0057] Accordingly, this disclosure also provides a method for manufacturing the above-mentioned electronic device, including the following steps:

[0058] The first step is to provide a substrate 100, which includes a plurality of pad areas PA arranged side by side.

[0059] The second step, as Figure 6As shown, in each pad area PA, multiple first pad groups 101 are cascaded together, multiple second pad groups 102 are coupled to each first pad group 101, a function line 103, a first trace 104, a constant voltage signal line 105, a feedback signal line 106, a first connection line 107, a second connection line 108, a common voltage signal line 110, a power line 111, a third connection line 112, an address signal line 113, and a cascade line 114. The second pad group 102 includes at least two interconnected sub-pad groups 21. Each pad area PA includes a selected pad group 102'. Each sub-pad group 21 in the selected pad group 102' is connected to at least one functional line 103, and one end of all functional lines 103 is connected to a first trace 104. The selected pad group 102' is the second pad group 102 in a pad area PA that is closest to the selected side S. The selected side S is the side of the wiring substrate extending along the first direction X. The sub-pad groups 21 in each second pad group 102 are connected in series. The first sub-pad group 21 in the selected pad group 102' is connected to the constant voltage signal line 105, and the last sub-pad group 21 in the selected pad group 102' is connected to the feedback signal line 106. The ground pad Gnd of all the first pad groups 101 cascaded in a pad area PA is connected to the same common voltage signal line 110. The power line 111 has multiple segments 111'. Each segment 111' is connected to the power supply pad of a first pad group 101 in a pad area PA. Optionally, two adjacent segments 111' within a pad area PA can be connected to each other via a third connection line 112. Optionally, the third connection line 112 and the segment 111' are integrally formed. Within each pad area PA, the address pad Di of the first-level first pad group 101 is connected to the address signal line 113. The output pad Out of the k-th (k is a positive integer)-th first pad group 101 and the address pad Di of the (k+1)-th first pad group 101 are connected via a cascading line 114. The output pad Out of the last-level first pad group 101 is connected to the feedback signal line 106. Optionally, the first traces 104 of each pad area PA can be set independently, or the first traces 104 of each pad area PA can be integrally formed.

[0060] The third step, as Figure 8 As shown, an insulating layer 109 is formed on the layer containing multiple first pad groups 101, multiple second pad groups 102, function lines 103, first traces 104, constant voltage signal lines 105, feedback signal lines 106, first connection lines 107, second connection lines 108, common voltage signal lines 110, power lines 111, third connection lines 112, address signal lines 113, and cascade lines 114. The insulating layer 109 has an opening K at the position of the first pad groups 101 and the second pad groups 102, and covers the area outside the first pad groups 101 and the second pad groups 102.

[0061] Step four, as Figure 11 As shown, a driver chip 002 is coupled to the first pad group 101, and an electronic component 003 is coupled to the sub-pad group 21.

[0062] Fifth step, along Figure 11 The C-line shown cuts off the first trace 104 and the portions of each functional line 103 adjacent to the first trace 104, leaving one end of each functional line 103 suspended. The remaining functional lines 103 have a length l in the second direction Y that is greater than or equal to 1 μm and less than or equal to 30 μm. Figure 10 As shown.

[0063] It should be noted that in some embodiments, the functional line 103 and the first trace 104 may not be covered by the insulating layer 109. After cutting and removing the first trace 104 and the portion of each functional line 103 adjacent to the first trace 104, in order to further prevent static charge from entering the wiring substrate, a protective adhesive made of insulating material may be applied to the end of the functional line 103 that is not covered by the insulating layer 109.

[0064] Although preferred embodiments have been described in this disclosure, it should be understood that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A wiring substrate, characterized in that, include: Multiple pad areas are arranged along a first direction, each pad area including multiple first pad groups and multiple second pad groups. The multiple first pad groups are cascaded along a second direction. One of the first pad groups is connected to one of the second pad groups. The second pad group includes at least two interconnected sub-pad groups. Each of the pad areas includes a function line and a selected pad group, each sub-pad group in the selected pad group is connected to at least one of the function lines, and one end of all the function lines is connected to a first trace. The selected pad group is a second pad group that is closest to the selected side in the pad area, and the selected side is the side of the wiring substrate that extends along the first direction; Within one of the pad areas, the number of function lines is one more than the number of sub-pad groups in the selected pad group.

2. The wiring substrate as described in claim 1, characterized in that, It also includes a constant voltage signal line and a feedback signal line. The sub-pad groups of the selected pad group are connected in series. The first sub-pad group in the selected pad group is connected to the constant voltage signal line, and the last sub-pad group in the selected pad group is connected to the feedback signal line.

3. The wiring substrate as described in claim 2, characterized in that, The function line connected to the first sub-pad group is also connected to the constant voltage signal line; the function line connected to the last sub-pad group is also connected to the feedback signal line.

4. The wiring substrate as described in claim 2, characterized in that, It also includes a first connection line, through which two adjacent sub-pad groups in the selected pad group are connected in series, and each first connection line is connected to one of the functional lines.

5. The wiring substrate as described in claim 2, characterized in that, It also includes a second connection line, through which the function line connected to the last sub-pad group is simultaneously connected to one of the first pad groups.

6. The wiring substrate according to any one of claims 1 to 5, characterized in that, It also includes an insulating layer, which includes openings that expose only the first pad group and the second pad group.

7. The wiring substrate according to any one of claims 1 to 5, characterized in that, One of the selected pad groups is connected to one of the first traces, or all of the selected pad groups are connected to the same first trace.

8. An electronic device, characterized in that, include: A wiring substrate includes a plurality of pad areas arranged along a first direction. Each pad area includes a plurality of first pad groups and a plurality of second pad groups. The plurality of first pad groups are cascaded along a second direction. One of the first pad groups is connected to one of the second pad groups. The second pad group includes at least two interconnected sub-pad groups. Each of the pad areas includes a function line and a selected pad group, each sub-pad group in the selected pad group is connected to at least one of the function lines, and one end of all the function lines is left unconnected. The selected pad group is a second pad group that is closest to the selected side in the pad area, and the selected side is the side of the wiring substrate that extends along the first direction; The driver chip is connected to the first pad group; Electronic components are connected to the second pad group.

9. The electronic device as claimed in claim 8, characterized in that, The length of the functional line in the second direction is greater than or equal to 1 μm and less than or equal to 30 μm.

10. The electronic device as claimed in claim 8 or 9, characterized in that, The function line can be one of a straight line, a curve, a broken line, or any combination thereof.

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