Clock generator circuit for generating duty cycle clock signals at low power

Abstract

Clock generator circuits for generating a duty cycle clock signal at low power are disclosed. In one embodiment, an apparatus includes a clock generator circuit to receive a first clock signal at a first frequency and output a second clock signal at a second frequency that is less than the first clock frequency. The clock generator circuit can include a frequency divider circuit to frequency divide the first clock signal to obtain at least a first frequency divided clock signal and a second frequency divided clock signal, and a gating circuit coupled to the frequency divider circuit, the gating circuit to gate the first clock signal with at least one of the first frequency divided clock signal and the second frequency divided clock signal to output the second clock signal.

Description

Background Technology

[0001] In many integrated circuits (ICs), the clock signals used to operate the IC's components—including clock signals related to up-conversion and down-conversion of radio frequency (RF) signals—are typically generated within the IC itself. Commonly, a clock generator receives the clock signal and processes it to generate multiple clock signals with desired properties, such as different frequencies, duty cycles, etc.

[0002] Specifically, generating a local oscillator (LO) clock signal requires careful design of clock generator components that utilize high-power-consuming, tightly matched devices such as various transistors and logic circuits. These components, for example, use relatively large components to ensure the clock signal is generated to meet desired specifications—including low phase noise and a high level of matching between quadrature (IQ) signal paths. In this way, these clock generators consume relatively high power to output a high-frequency LO clock signal with low phase noise and a high level of matching. Summary of the Invention

[0003] In one aspect, an apparatus includes a clock generator circuit for receiving a first clock signal at a first frequency and outputting a second clock signal at a second frequency less than the first clock frequency. The clock generator circuit may include: a frequency divider circuit for dividing the first clock signal to obtain at least a first divided clock signal and a second divided clock signal; and a gating circuit coupled to the frequency divider circuit, the gating circuit being used to select the first clock signal using at least one of the first divided clock signal and the second divided clock signal to output the second clock signal. A mixer is coupled to the clock generator circuit to down-convert a radio frequency (RF) signal using the second clock signal.

[0004] In the example, the gating circuit is used to receive a first clock signal and to gating the first clock signal using a first divided clock signal and a second divided clock signal. The gating circuit may include a plurality of NAND gates, each of which is used to receive the first clock signal and one of the first divided clock signal and the second divided clock signal. The gating circuit may further include a plurality of inverters, each of which is coupled to the output of one of the NAND gates. Each of the inverters outputs the phase of a second clock signal, which includes a differential quadrature clock signal.

[0005] In the example, the gating circuit includes a first gated metal-oxide-semiconductor field-effect transistor (MOSFET) and a second gated MOSFET, which are selected by a first divided clock signal. The first gated MOSFET has a first terminal coupled to a second terminal of a third MOSFET, and the second gated MOSFET also has a first terminal coupled to the first terminal of the third MOSFET, which is selected by the first clock signal. The first gated MOSFET may have a first width-to-length ratio, and the second gated MOSFET may have a second width-to-length ratio, wherein the first width-to-length ratio is greater than the second width-to-length ratio.

[0006] In the example, the first and second divided clock signals include strobe signals. The width of the second clock signal is defined by the width of the first clock signal, not by the width of either the first or second divided clock signal. The edge rate of the second clock signal is defined by the edge rate of the first clock signal, not by the edge rate of either the first or second divided clock signal. In the example, the pulse width of the first divided clock signal is greater than the pulse width of the first clock signal, and the pulse width of the second clock signal is at least substantially equal to the pulse width of the first clock signal. The clock generator circuit may be a local oscillator circuit used to generate a quadrature 25% duty cycle clock signal that includes the second clock signal.

[0007] In another aspect, one method includes: receiving a clock signal in a clock generator of an integrated circuit; clocking multiple latches of a frequency divider of the clock generator using the incoming clock signal to generate multiple intermediate clock signal phases; and using the multiple intermediate clock signal phases to gate the incoming clock signal to generate a local oscillator (LO) clock signal from the incoming clock signal, the LO clock signal having a reduced duty cycle relative to the incoming clock signal.

[0008] In the example, the method further includes outputting the LO clock signal to a mixer of an integrated circuit to down-convert the incoming radio frequency signal to a second frequency signal. The method may further include: latching a first latch of a frequency divider using a first phase of the incoming clock signal, and latching a second latch of the frequency divider using a second phase of the incoming clock signal; providing a first output signal from the first latch to an input of the second latch, and providing a second output signal from the second latch to an input of the first latch. The method may also include: performing a logical operation between the first output signal and a second phase of the incoming clock signal to generate a quadrature phase of the LO clock signal; and performing a logical operation between the second output signal and a first phase of the incoming clock signal to generate a non-inverting phase of the LO clock signal.

[0009] In another aspect, an integrated circuit includes: a low-noise amplifier (LNA) for receiving and amplifying an RF signal; a mixer coupled to the LNA to down-convert the RF signal to a second frequency signal using an LO clock signal; and a clock generator circuit that receives a first clock signal of a first frequency and outputs an LO clock signal having a duty cycle as a fraction of the duty cycle of the first clock signal. The clock generator circuit may include: a frequency divider circuit for dividing the first clock signal to obtain a plurality of intermediate clock signals; and a gating circuit coupled to the frequency divider circuit for gating the first clock signal using the plurality of intermediate clock signals to generate the LO clock signal.

[0010] In the example, the gating circuit includes: a plurality of logic gates, each of which receives a first clock signal and one of a plurality of intermediate clock signals; and a plurality of inverters, each of which is coupled to the output of one of the logic gates. Each of the plurality of inverters is used to output the phase of an LO clock signal, which includes differential quadrature clock signals. The clock generator circuit can generate an LO clock signal having an edge rate defined by the edge rate of the first clock signal and a pulse width at least substantially equal to the pulse width of the first clock signal, the pulse width of the LO clock signal being greater than the pulse width of the plurality of intermediate clock signals. Attached Figure Description

[0011] Figure 1 This is a block diagram of a clock generator circuit according to an embodiment.

[0012] Figure 2A This is a schematic diagram of a clock generator circuit according to an embodiment.

[0013] Figure 2B This is a timing diagram of the operation of the clock generator circuit according to an embodiment.

[0014] Figure 3A This is a schematic diagram of a latch circuit according to an embodiment.

[0015] Figure 3B This is a schematic diagram of a latch circuit according to another embodiment.

[0016] Figure 3C This is a schematic diagram of the gating circuit according to an embodiment.

[0017] Figure 3D This is a timing diagram of the operation of the gating circuit according to an embodiment.

[0018] Figure 4 This is a high-level block diagram of a portion of the receiver according to an embodiment.

[0019] Figure 5 This is a flowchart of a method according to an embodiment.

[0020] Figure 6 This is a block diagram of a representative integrated circuit according to an embodiment.

[0021] Figure 7 This is a high-level diagram of a network according to an embodiment. Detailed Implementation

[0022] In various embodiments, a clock generator is provided that can operate at low power (e.g., less than about 5 milliwatts) while still generating clock signals with desired signal properties, including good IQ matching and low phase noise. In a particular embodiment, the clock generator can be implemented in a local oscillator (LO) circuit that generates a clock signal with an orthogonal 25% duty cycle. These resulting clock signals can be used, for example, in a mixer circuit, such as a down-conversion mixer that receives differential RF signals and down-converts them to lower frequency signals.

[0023] In low-power operation, clock signals with low phase noise and high speed can be generated for a given power budget. An example use case is wireless devices such as Internet of Things (IoT) integrated circuits. These wireless devices include transceivers that can operate at frequencies between, for example, 2.4 GHz and 2.5 GHz or between 4.9 GHz and 5.9 GHz. The 2.4 GHz to 2.5 GHz band is used, for example, for Bluetooth transceivers, and the 4.9 GHz to 5.9 GHz band is used for 5 GHz WiFi transceivers. Of course, embodiments are not limited in this respect, and in other implementations, the clock generator described herein can be used in relation to transceivers operating at, for example, 10 GHz. To accommodate such transceivers, the LO circuit according to the embodiment can generate an LO clock signal with frequencies at approximately 2.4 GHz and 2.5 GHz.

[0024] Now refer to Figure 1 A block diagram of a clock generator circuit according to an embodiment is shown. Figure 1 As shown, the clock generator circuit 100 receives a clock signal. In implementation, this clock signal can be generated by an on-chip oscillator such as a voltage-controlled oscillator (VCO). Figure 1 In the embodiment shown, the clock signal is a differential signal having a positive phase portion (p) and a negative phase portion (n).

[0025] As shown, the differential clock signal is provided to the frequency divider circuit 110. In an embodiment, the frequency divider circuit 110 can operate to generate a divided clock signal from the incoming differential clock signal, such as a divided-by-four clock signal. In an embodiment, the frequency divider circuit 110 can be implemented using multiple latch circuits, as further described below.

[0026] The resulting divided clock signal is then provided to the gating circuit 120, which also receives the received differential clock signal. In this embodiment, the gating circuit 120 can use these divided clock signals to select the incoming differential clock signal to generate one or more LO clock signals. The LO clock signal may have substantially the same shape as the VCO clock signal, but at a lower duty cycle, such as 25%. In this way, the LO clock signal may have at least substantially the same pulse width as the VCO clock signal, but generated at a lower frequency.

[0027] In the gating circuit 120, the divided clock signal acts as a gating signal for high-speed incoming (e.g., VCO) clock signals and does not limit the width or edge rate of the resulting LO clock signal. As a result, these gating signals have relaxed design requirements, where the only real requirement is that the divided clock signal does not transition when the incoming clock signal (i.e., the signal to be gated) is high or transitions (from low to high or from high to low). As a result of this lack of requirement, the divider circuit 110 can be designed to have a lower power budget. Alternatively, the divider circuit 110 can operate at a higher speed for a given power budget because its matching and edge rate are not critical. This is because the divided clock signal does not limit the overall matching and does not contribute to the phase noise of the resulting LO signal. Therefore, better matching and lower phase noise can be achieved for a given power budget. That is, for a given power budget, lower clock jitter can be achieved due to the lower number of gates—the LO edges limit the clock through these gates. Furthermore, due to the lower number of gates, a lower mismatch result is achieved, resulting in higher native image rejection. Also further, since the intermediate clock signal generated by the divider circuit 110 does not limit the LO signal width or edge rate, a faster possible maximum operating speed can be achieved.

[0028] Now refer to Figure 2A A schematic diagram of a clock generator circuit according to an embodiment is shown. Figure 2A As shown in the diagram, the clock generator circuit 200 may include Figure 1The circuit includes a frequency divider circuit 110 and a gating circuit 120. As shown, the frequency divider circuit 110 includes multiple latch circuits 210 and 220, which can be implemented as D-type latches. As shown, each latch circuit 210 and 220 is clocked by one phase of a differential clock signal (CLKn, CLKp). The output of latch circuit 210 is cross-coupled to the input of latch circuit 220. Furthermore, the output of latch circuit 220 is fed back to the input of latch circuit 210. These outputs are the phases of the divided clock signals, also referred to herein as intermediate clock signals.

[0029] The outputs of latch circuits 210 and 220 (i.e., the divided clock signals Ix, Ixb, Qx, Qxb) are then provided as inputs to gating circuit 120, which in Figure 2A This is shown in further detail below. For example... Figure 2A As shown, the gating circuit 120 receives the phase of the divided clock signal and the incoming differential clock signal in a plurality of logic gates (i.e., NAND gates 232a-d). More specifically, each NAND gate 232 receives one of the phases of the incoming clock signal and the divided clock signal. Furthermore, each NAND gate 232 provides an output signal to the corresponding inverter 242a-d. In this way, the gating circuit 120 operates to gating the incoming differential clock signal using the phase of the divided clock signal, thus reducing the reliance on matching or pulse width control of the divided clock signal. Although illustrated using this particular set of logic gates, other logic gate configurations such as AND gates or NOR gates may be used in other implementations.

[0030] Now refer to Figure 2B The diagram 250 illustrates the operation of clock generator circuit 200. As seen, the incoming differential clock signals CLKp and CLKn are provided as inputs for clocking latches in the divider circuit. These latches then output multiple divided clock signal phases Ix, Ixb, Qx, and Qxb. Although a divide-by-two operation is shown, it is understood that the divider input can be generated from an additional divider placed at the VCO output. For a 25% duty cycle quadrature LO generator, the incoming clock signal is a 50% duty cycle signal. Therefore, even integer division ratios (e.g., 6, 8, 10) are typically used. Note that due to mismatches, phase noise, etc., in the latch devices, the phases of these divided clock signals are not perfectly aligned with the transitions in the input clock signal. Instead, in the embodiment, there may be a delay, for example, reaching approximately 20% of the input clock cycle. The actual delay is primarily determined by the transistor drive strength and parasitic capacitance of the implemented latches. Furthermore, although... Figure 2BThe diagram uses relatively steep edges, but again, due to the use of smaller devices, the phase of these divided clock signals may not maintain a steep rectangular waveform.

[0031] Still refer to Figure 2B When supplied to a gating circuit such as gating circuit 120, the phase of these divided clock signals is used to perform a logical AND operation (such as...). Figure 2B As shown in the diagram, the incoming differential clock signal is selected to create second clock signals (Ip, In, Qp, Qn), each second clock signal having a 25% duty cycle relative to the incoming clock signal. It is understood that although in... Figure 2B The example shown utilizes this specific implementation, but other implementations are capable of achieving a similar 25% duty cycle for clock signal generation. Of course, other duty cycles and logic circuit implementations are possible in other embodiments.

[0032] Now refer to Figure 3A A schematic diagram of an example latch circuit according to an embodiment is shown. Figure 3A In its implementation, the latch circuit 310 can be a pseudo-differential latch circuit with a load formed by a P-type metal-oxide-semiconductor field-effect transistor (MOSFET).

[0033] As shown, the differential data signals Dp and Dn provided via input nodes 312 and 314 are coupled to the corresponding gate terminal of the N-type MOSFET (NMOS) device at each input node. Specifically, as shown, the positive input data signal Dp is coupled to the gate terminal of the NMOS device M1 at input node 312, and the negative input data signal Dn is coupled to the gate terminal of the NMOS device M2 at input node 314.

[0034] NMOS devices M1 and M2 have source terminals coupled to reference voltage node 313 and drain terminals coupled to the source terminals of corresponding NMOS devices M3 and M4. As shown, the common-coupled gate terminals of MOSFETs M3 and M4 receive the clock signal CK at clock node 311. Furthermore, the drain terminals of NMOS devices M3 and M4 are coupled to output nodes 316 and 318 to provide corresponding output signals On and Op (which can be used as clock signals for frequency division and can also be provided as input to another latch circuit of the frequency divider circuit, as described herein). As further shown, output nodes 316 and 318 are further coupled to the drain terminals of P-type MOSFET (PMOS) devices M5 and M6, which have gate terminals cross-coupled to output nodes 316 and 318 and source terminals coupled to supply voltage node 317. Note that the MOSFET of latch circuit 310 can tolerate large mismatches and high noise, and therefore can be a relatively small device, since the resulting divided clock signal is used as the strobe signal.

[0035] Although this implementation is shown, other implementations are of course possible. Figure 3A In the implementation shown, the clock signal (e.g., VCO clock) is received at the top of the data input received at input nodes 312 and 314. Alternatively, in other embodiments, a clock below the data input node may be received.

[0036] Now refer to Figure 3B A schematic diagram of a latch circuit according to another embodiment is shown. As illustrated, the latch circuit 320 receives a clock signal (e.g., a VCO clock) at clock node 321 coupled to an NMOS device M13, which has a source terminal coupled to a reference voltage node 323 and a drain terminal coupled to the source terminals of NMOS devices M11 and M12. This arrangement, with a single device receiving the clock signal, results in a smaller load on the VCO or other clock source, enabling potentially faster operation.

[0037] like Figure 3BAs further shown, the differential data signals Dp and Dn provided via input nodes 322 and 324 are coupled to the corresponding gate terminals of the respective NMOS devices M11 and M12. Furthermore, the NMOS devices M11 and M12 have drain terminals coupled to the corresponding PMOS devices M15 and M16, and also coupled to output nodes 326 and 328 to provide the corresponding output signals On and Op (which can be used as clock signals for frequency division and can also be provided as inputs to additional latch circuits in the frequency divider circuit, as described herein). As further shown, the PMOS devices M15 and M16 have gate terminals cross-coupled to output nodes 326 and 328 and source terminals coupled to the supply voltage node 327. Note that, as mentioned above... Figure 3A As described, the MOSFET of latch circuit 320 can have a relatively large mismatch and can be a relatively small device.

[0038] Now refer to Figure 3C A schematic diagram of a gating circuit according to an embodiment is shown. (As in...) Figure 3C As shown, gating circuit 350 can be used to gating an incoming clock signal (CLKn) using an intermediate clock phase, which can be generated by a frequency divider circuit. As an example, gating circuit 350 can be a representative implementation of gating circuit 120.

[0039] As shown, the incoming clock signal CLKn is received via input clock node 351, which is coupled to the gate terminals of the corresponding NMOS device Mc1 and PMOS device Mc2. The source terminal of NMOS device Mc1 is coupled to the drain terminal of gate-controlled NMOS device Mlarge. As shown, the gate-controlled NMOS device Mlarge has a gate terminal coupled to receive the intermediate clock signal phase Ix via input node 352 and a source terminal coupled to reference voltage node 356.

[0040] The NMOS device Mc1 further has a drain terminal coupled to the drain terminal of the PMOS device Mc2, and the PMOS device Mc2 has a source terminal coupled to the supply voltage node 354. As illustrated, the common drain terminal of the NMOS device Mc1 and the PMOS device Mc2 is further coupled to the drain terminal of the gate-controlled PMOS device Msmall.

[0041] As illustrated, the gate-controlled PMOS device Msmall further has a gate terminal coupled to receive the phase of the divided clock signal via input node 352 and a source terminal coupled to supply voltage node 354. Its drain terminal is also coupled to the corresponding gate terminals of the inverter PMOS device Mi2 and the NMOS device Mi1. These inverter devices have a common coupled drain terminal that provides the resulting 25% duty cycle clock signal Ip at output node 358. As further shown, the inverter NMOS device Mi1 has a source terminal coupled to reference voltage node 356, and the inverter PMOS device Mi2 has a source terminal coupled to supply voltage node 354.

[0042] Using this arrangement of the gating circuit 350, the gated NMOS device Mlarge can have a relatively large width-to-length ratio (W / L) for better edge rate performance. In an embodiment, the gated NMOS device can have a W / L ratio between approximately two and four times that of Mc1. Similarly, for less load and therefore better edge rate gating, the gated PMOS device Msmall can have a smaller W / L ratio, for example, between approximately one-quarter and one-half that of Mc2. It is understood that, although using... Figure 3C This particular implementation is shown in the embodiments, but many variations and substitutions are possible.

[0043] Now refer to Figure 3D A timing diagram 360 illustrating the operation of the gating circuit 350 is shown. As illustrated, the incoming divided clock signal phase Ix has a relatively slow rise and relatively gentle edges, as illustrated at the rising portion 361. Furthermore, this divided clock signal used as the gating signal has periods that are not perfectly aligned with the incoming clock signal CLKn. As shown, the rising edge 362 and falling edge 363 of the incoming clock signal CLKn are not aligned with the corresponding rising portions 361 and falling portions 364 of the divided clock signal. However, by using the embodiment described herein, the resulting output clock signal Ip maintains a shape (pulse width and edges) and phase that are substantially identical to the incoming clock signal CLKn.

[0044] Now refer to Figure 4 A high-level block diagram of a portion of a receiver according to an embodiment is shown. Figure 4 As shown, receiver 400 can be any type of IC including RF capability, including a low-noise amplifier (LNA) 410 to receive the received RF signal RFin, which can be received from an off-chip antenna. After amplification in LNA 410, the resulting amplified RF signal is coupled to signal processing path 415 via coupling capacitor CC.I 415 Q Each signal processing path has a passive mixer 430 driven by a current generated by a switch. I and 430 Q As shown, mixer 430 I 430 Q This includes the corresponding 180-degree out-of-phase controlled switches. Although shown as a relatively simple switch arrangement, it is understood that differential mixers can take various forms. As shown, mixer 430 I、Q Clocking can be achieved using a 25% quadrature LO clock signal received from clock generator 420. According to embodiments, the clock generator can be an IQ LO clock generator. For example, clock generator 420 may include a divider circuit 110 and a gating circuit 120 as described above (and it may include...). Figure 3A (and / or Figure 3B )and Figure 3C (Specific implementation described in the figure). The resulting 25% quadrature LO clock signal is shown in illustration 425. In this way, the passive mixer 430 downconverts the incoming RF signal into a lower frequency signal, such as intermediate frequency (IF) or baseband (zero to IF).

[0045] The resulting down-converted current signal is then supplied to the corresponding transimpedance amplifier (TIA) 440. I 440 Q An RC circuit is coupled between the input and output of the TIA to convert the incoming current signal into a voltage signal. These gain-controlled signals are then fed to a low-pass filter 450. I 450 Q And then provided to the digitizer 460 I 460 Q It can be implemented as an analog-to-digital converter. This allows it to convert the obtained digital signal (D signal) that might be in baseband into a digital signal. out-I and D out-Q This is provided to the digital signal processor 470. The digital signal processor 470 can perform various processes on the signal to obtain the message content. It is understood that, although in Figure 4 The embodiments are shown at this high level, but many variations and substitutions are possible. Note that in the embodiments, Figure 4 All the circuits shown can be implemented on a single semiconductor die of an integrated circuit.

[0046] Now refer to Figure 5 A flowchart of a method according to an embodiment is shown. Figure 5As shown, method 500 is a method for generating a clock signal in a low-power clock generator circuit as described herein. In this way, method 500 can be performed within a clock generator circuit, which can be configured for specific operating characteristics (e.g., pulse width, duty cycle, frequency, etc.) based, for example, at least in part, on the frequency band of wireless operation.

[0047] As illustrated, method 500 begins with a clock signal received in a clock generator (block 510). This incoming clock signal may be a differential VCO clock signal, and in implementation may be a VCO clock signal, which is a square wave having a frequency between approximately 1 and 10 GHz.

[0048] Still refer to Figure 5 Next, at box 520, the incoming clock signal can be used to clock the latch of the frequency divider circuit. In this way, multiple intermediate clock signal phases can be generated within the frequency divider circuit. For example, using the incoming differential clock signal, four intermediate clock signal phases can be generated. Although these intermediate clock signal phases can have different characteristics depending on the desired operating characteristics, in some cases, the frequency divider circuit can perform a divide-by-2 operation, such that the resulting intermediate quadrature clock signal is at 50% of the frequency of the incoming clock signal. Of course, other examples are possible. It should be further noted that, as described herein, these intermediate clock signal phases can be generated in a low-power manner, so that the resulting signal can tolerate relatively large amounts of noise and device mismatch.

[0049] Next, at block 530, these intermediate clock signal phases can be used in the gating circuit to gating the incoming clock signal. In this way, these intermediate clock signal phases, which have a certain amount of noise and other undesirable characteristics, act as gating signals so that the resulting gated incoming clock signal maintains the signal integrity of the original incoming clock signal, although at a reduced duty cycle (e.g., 25%).

[0050] Finally, at block 540, the strobed incoming clock signal can be output as a quadrature LO clock signal with a reduced duty cycle (i.e., a 90-degree phase shift between Ip and Qp or between In and Qn). In the embodiment described herein, this LO clock signal can be used by a down-conversion mixer that receives the RF signal and down-converts it to a lower frequency signal. It is understood that, although in Figure 5 The embodiments are shown at this high level, but many variations and substitutions are possible.

[0051] Now refer to Figure 6 A block diagram of a representative integrated circuit 600, which may include clock generator circuitry as described herein, is shown. Figure 6 In the embodiments shown, the integrated circuit 600 may be, for example, a microcontroller, a wireless transceiver, or other device that can be used in a variety of applications including sensing, metering, monitoring, embedded applications, communications, etc., and it may be particularly adapted for use in IoT devices.

[0052] In the illustrated embodiment, integrated circuit 600 includes a memory system 610, which may include non-volatile memory such as flash memory and volatile storage such as RAM. In the embodiment, the non-volatile memory may be implemented as a non-transitory storage medium capable of storing instructions and data. Such a non-volatile memory can store instructions, including instructions for controlling the operation of a clock generator, for example, based on a desired operating channel as described herein.

[0053] Memory system 610 is coupled to digital core 620 via bus 650, which may include one or more cores and / or microcontrollers serving as the main processing unit of an integrated circuit. Digital core 620 may further be coupled to clock generator 630, which may provide one or more phase-locked loops or other clock generator circuits to generate various clocks for use by the circuitry of the IC. As shown, clock generator 630 may include clock generator 635, which may generate an LO clock signal via gating of an incoming clock signal as described herein.

[0054] As further illustrated, IC 600 further includes power circuitry 640, which may include one or more voltage regulators. Depending on the specific implementation, additional circuitry may be optionally provided to provide various functions and interaction with external devices. Such circuitry may include: interface circuitry 660, which provides an interface with various off-chip devices; and sensor circuitry 670, which may include various on-chip sensors, including digital and analog sensors, to sense desired signals, such as for metering applications.

[0055] In addition, such as Figure 6 As shown, transceiver circuitry 680 can be provided to enable the transmission and reception of wireless signals, for example, according to one or more of local or wide-area wireless communication schemes, such as Zigbee, Bluetooth, IEEE 802.11, IEEE 802.15.4, and cellular communication. It is understood that although shown in this high-level view, many variations and substitutions are possible.

[0056] Note that ICs such as those described herein can be implemented in a variety of different devices, such as IoT devices. These IoT devices can be smart metering devices used in smart function networks, such as mesh networks where communication is based on the IEEE 802.15.4 standard.

[0057] Now refer to Figure 7 A high-level diagram of a network according to an embodiment is shown. Figure 7 As shown, Network 700 includes various devices, including smart devices such as IoT devices, routers, and remote service providers. Figure 7 In embodiments, the mesh network 705 may exist, for example, in a network with multiple IoT devices 710. 0-n In the neighborhood. Such IoT devices can generate LO and other clock signals in a low-power manner via the gating described herein. As shown, at least one IoT device 710 is coupled to router 730, which in turn communicates with a remote service provider 760 via a wide area network 750 (e.g., the Internet). In embodiments, the remote service provider 760 may be a backend server of an entity handling communication with the IoT device 710. It is understood that, although in Figure 7 The embodiments are shown at this high level, but many variations and substitutions are possible.

[0058] Although the invention has been described with respect to a limited number of embodiments, many modifications and variations will be apparent to those skilled in the art. The appended claims are intended to cover all such modifications and variations that fall within the true spirit and scope of the invention.

Claims

1. An apparatus for processing clock signals, comprising: A clock generator circuit is used to receive a first clock signal at a first frequency and output a second clock signal at a second frequency lower than the first clock frequency. The clock generator circuit includes: A frequency divider circuit is used to divide a first clock signal to obtain at least a first divided clock signal and a second divided clock signal; and A gating circuit, coupled to a frequency divider circuit, is used to select the first clock signal using at least one of a first divided clock signal and a second divided clock signal, so as to output the second clock signal; and A mixer, coupled to a clock generator circuit, to down-convert a radio frequency (RF) signal using a second clock signal. The gating circuit includes multiple NAND gates, each of which is used to receive a first clock signal and either a first divided clock signal or a second divided clock signal.

2. The apparatus of claim 1, wherein the gating circuit is configured to receive a first clock signal, and to gating the first clock signal using a first divided clock signal, and to gating the first clock signal using a second divided clock signal.

3. The apparatus of claim 1, wherein the gating circuit further comprises a plurality of inverters, each of the plurality of inverters being coupled to the output of one of the plurality of NAND gates.

4. The apparatus of claim 3, wherein each of the plurality of inverters is configured to output the phase of a second clock signal, the second clock signal comprising a differential quadrature clock signal.

5. The apparatus of claim 3, wherein the gating circuit comprises: The first gated metal-oxide-semiconductor field-effect transistor (MOSFET) and the second gated MOSFET are selected by a first divided clock signal. The first gated MOSFET has a first terminal coupled to a second terminal of a third MOSFET, and the second gated MOSFET has a first terminal coupled to a first terminal of the third MOSFET. The third MOSFET is selected by the first clock signal.

6. The apparatus of claim 5, wherein the first gate-controlled MOSFET has a first width-to-length ratio, and the second gate-controlled MOSFET has a second width-to-length ratio, wherein the first width-to-length ratio is greater than the second width-to-length ratio.

7. The apparatus of claim 1, wherein the first frequency-divided clock signal and the second frequency-divided clock signal include strobe signals.

8. The apparatus of claim 7, wherein the width of the second clock signal is defined by the width of the first clock signal, rather than by the width of the first divided clock signal or the width of the second divided clock signal.

9. The apparatus of claim 8, wherein the edge rate of the second clock signal is defined by the edge rate of the first clock signal, rather than by the edge rate of the first divided clock signal or the edge rate of the second divided clock signal.

10. The apparatus of claim 1, wherein the pulse width of the first frequency-divided clock signal is greater than the pulse width of the first clock signal, and the pulse width of the second clock signal is at least substantially equal to the pulse width of the first clock signal.

11. The apparatus of claim 1, wherein the clock generator circuit includes a local oscillator circuit for generating a quadrature 25% duty cycle clock signal including a second clock signal.

12. An integrated circuit, comprising: A low-noise amplifier (LNA) is used to receive and amplify radio frequency (RF) signals; A mixer coupled to the LNA is used to down-convert an RF signal to a second frequency signal using a local oscillator (LO) clock signal; as well as A clock generator circuit is used to receive a first clock signal at a first frequency and output a LO clock signal, wherein the LO clock signal has a duty cycle that is a fraction of the duty cycle of the first clock signal. The clock generator circuit includes: A frequency divider circuit is used to divide the first clock signal to obtain multiple intermediate clock signals; and A gating circuit, coupled to a frequency divider circuit, is used to select a first clock signal using the plurality of intermediate clock signals to generate an LO clock signal. The gating circuit includes multiple logic gates, each of which receives a first clock signal and one of the multiple intermediate clock signals.

13. The integrated circuit of claim 12, wherein the gating circuit further comprises: Multiple inverters, each of which is coupled to the output of one of the multiple logic gates.

14. The integrated circuit of claim 13, wherein each of the plurality of inverters is used to output a phase of an LO clock signal, the LO clock signal comprising a differential quadrature clock signal.

15. The integrated circuit of claim 12, wherein the clock generator circuit is used to generate an LO clock signal having an edge rate defined by the edge rate of a first clock signal and a pulse width at least substantially equal to the pulse width of the first clock signal, the pulse width of the LO clock signal being greater than the pulse width of the plurality of intermediate clock signals.

16. A method for processing clock signals using an integrated circuit according to any one of claims 12 to 15, comprising: The clock signal received in the clock generator of the integrated circuit; The incoming clock signal is used to clock multiple latches of the frequency divider of the clock generator to generate multiple intermediate clock signal phases; as well as The incoming clock signal is phase-gated using the multiple intermediate clock signals to generate a local oscillator (LO) clock signal from the incoming clock signal, the LO clock signal having a reduced duty cycle relative to the incoming clock signal.

17. The method of claim 16, further comprising outputting an LO clock signal to a mixer of an integrated circuit to down-convert an incoming radio frequency signal to a second frequency signal.

18. The method of claim 16, further comprising: The first latch of the frequency divider is latched using the first phase of the incoming clock signal, and the second latch of the frequency divider is latched using the second phase of the incoming clock signal; as well as The first output signal from the first latch is provided to the input of the second latch, and the second output signal from the second latch is provided to the input of the first latch.

19. The method of claim 18, further comprising: A logic operation is performed between the first output signal and the second phase of the incoming clock signal to generate an orthogonal phase of the LO clock signal; as well as A logic operation is performed between the second output signal and the first phase of the incoming clock signal to generate the in-phase phase of the LO clock signal.

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