High performance phase-locked loop

Abstract

The present invention discloses a high-performance phase-locked loop, comprising: a multi-phase comparator, used to obtain multiple reference signal phases and multiple local oscillator signal phases, wherein the multi-phase comparator comprises: multiple partial phase comparators and multiple charge pumps; a capacitive element, used to inject or delete charges into the capacitive element based on the multiple partial phase error signals to generate a composite phase error signal; a local oscillator, used to receive the composite phase error signal and adjust the fixed phase of the local oscillator in a responsive manner according to the composite phase error signal, wherein the local oscillator generates the multiple local oscillator signal phases.

Description

[0001] This application is a divisional application of the patent application with application number 201780036606.2, application date April 21, 2017, and invention name “High Performance Phase-Locked Loop”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 326,591, filed on April 22, 2016, and entitled “HIGH PERFORMANCE PHASE-LOCKED LOOP,” filed by Armin Tajalli, and is hereby incorporated by reference in its entirety.

[0004] References

[0005] The following references are incorporated herein by reference in their entirety for all purposes:

[0006] U.S. Patent Application Publication No. 2011 / 0268225, Application No. 12 / 784,414, filed May 20, 2010, inventors Harm Cronie and Amin Shokrollahi, entitled “Orthogonal Differential Vector Signaling,” hereinafter referred to as “Cronie 1”;

[0007] U.S. Patent Application Publication No. 2011 / 0302478, Application No. 12 / 982,777, filed December 30, 2010, inventors Harm Cronie and Amin Shokrollahi, entitled “High Pin Utilization, High Power Utilization Chip-to-Chip Communication with Common Mode Noise and Simultaneous Switching Output Noise Immunity,” hereinafter referred to as “Cronie 2”;

[0008] U.S. Patent Application No. 13 / 030,027, filed February 17, 2011, inventors Harm Cronie, Amin Shokrollahi and Armin Tajalli, entitled “Method and System for Noise-Resistant, High Pin Utilization, Low Power Communications Using Sparse Signaling Codes,” hereinafter referred to as “Cronie 3”;

[0009] U.S. Patent Application No. 13 / 176,657, filed on July 5, 2011, by Harm Cronie and Amin Shokrollahi, entitled “Method and System for Low Power High Pin Utilization Communications Using Superimposed Signaling Codes,” hereinafter referred to as “Cronie 4”;

[0010] U.S. Patent Application No. 13 / 542,599, filed on July 5, 2012, inventors are Armin Tajalli, Harm Cronie and Amin Shokrollahi, entitled “Method and Circuit for Efficient Processing and Detection of Balanced Codes”, hereinafter referred to as “Tajalli 1”;

[0011] U.S. Patent Application No. 13 / 842,740, filed on March 15, 2013, inventors are Brian Holden, Amin Shokrollahi and Anant Singh, entitled “Method and System for Skew Tolerance of Vector Signaling Codes for Inter-Chip Communications and Advanced Detector of Vector Signaling Codes for Inter-Chip Communications”, hereinafter “Holden 1”;

[0012] U.S. Provisional Patent Application No. 61 / 946,574, filed on February 28, 2014, with inventors Amin Shokrollahi, Brian Holden and Richard Simpson, entitled “Clock-Embedded Vector Signaling Codes,” hereinafter referred to as “Shokrollahi 1”;

[0013] U.S. Patent Application No. 14 / 612,241, filed on August 4, 2015, with inventors Amin Shokrollahi, Ali Hormati and Roger Ulrich, entitled “Method and Apparatus for Low Power Inter-Chip Communication with Low Inter-Symbol Interference Ratio”, hereinafter referred to as “Shokrollahi 2”;

[0014] U.S. Patent Application No. 13 / 895,206, filed May 15, 2013, with inventors Roger Ulrich and Peter Hunt, entitled “Circuit for Efficient Detection of Vector Signaling Codes for Inter-Chip Communications by Difference Sum,” hereinafter referred to as “Ulrich 1”;

[0015] U.S. Patent Application No. 14 / 816,896, filed on August 3, 2015, with inventors Brian Holden and Amin Shokrollahi, entitled “ORTHODUAL DIFFERENTIAL VECTOR SIGNALING CODES WITH EMBEDDED CLOCKS” (hereinafter “Holden2”);

[0016] U.S. Patent Application No. 14 / 926,958, filed on October 29, 2015, with inventors Richard Simpson, Andrew Stewart and Ali Hormati, entitled “Clock Data Alignment System for Vector Signaling Code Communication Links,” hereinafter referred to as “Stewart 1”;

[0017] U.S. Patent Application No. 14 / 925,686, filed on October 28, 2015, inventor Armin Tajalli, and entitled “Improved Phase Interpolator,” hereinafter referred to as “Tajalli 2”;

[0018] The application number is 62 / 286,717, the application date is January 25, 2016, the inventor is Armin Tajalli, and the name is the U.S. provisional patent application for "High Frequency Gain Improved Voltage Sampling Driver", hereinafter referred to as "Tajalli 3".

[0019] In addition, the following prior art references are cited in this application:

[0020] Patent No. 6,509,773, filed on April 30, 2001, inventors are Buchwald et al., and the name is “Phase Interpolator Apparatus and Method”, hereinafter referred to as “Buchwald”;

[0021] "Linear Phase Detection Using a Two-Phase Latch", A. Tajalli et al., IEEE Electronics Letters, 2003, hereinafter referred to as "Tajalli 4";

[0022] “Low-Jitter Low-Phase-Noise 10-GHz Subharmonic Injection-Locked Phase-Locked Loop with Self-Aligned DLL in 65-nm CMOS Technology,” Hong-Yeh Chang, Yen-Liang Yeh, Yu-Cheng Liu, Meng-Han Li, and Kevin Chen, IEEE Transactions on Microwave Theory and Techniques, Vol. 62, No. 3, March 2014, pp. 543–555, hereinafter Chang et al.

[0023] “A Low Phase Noise 77 GHz Fractional-N Phase-Locked Loop with Delay-Locked-Loop-Based Reference Multiplier for FMCW Radar,” Herman Jalli Ng, Rainer Stuhlberger, Linus Maurer, Thomas Sailer, and Andreas Stelzer, Proceedings of the 6th European Microwave Integrated Circuits Conference, October 10–11, 2011, pp. 196–199, hereinafter Ng et al.

[0024] “High Noise Robust Clock Data Recovery Design Using Bandwidth Adaptive Hybrid PLL / DLL”, Han-Yuan Tan, PhD dissertation, Harvard University, November 2006, hereinafter referred to as “Tan”. Technical Field

[0025] Embodiments of the present invention generally relate to communication system circuits, and more particularly to obtaining a phase-correct stable receiver clock signal through a high-speed multi-wire interface for inter-chip communication. Background Art

[0026] In modern digital systems, digital information processing must be performed in an efficient and reliable manner. In this context, digital information must be understood as information contained in discrete values ​​(i.e., non-continuous values). Digital information can be represented not only by bits and sets of bits, but also by numbers in a finite set.

[0027] To increase the total bandwidth, most chip-to-chip or device-to-device communication systems use multiple lines for communication. Each or a pair of these lines is called a channel or link, and multiple channels make up the communication bus between electronic components. At the physical circuit level, the bus in the chip-to-chip communication system is usually composed of packaged electrical conductors between the chip and the motherboard, packaged electrical conductors on the printed circuit board (PCB), or packaged electrical conductors in cables and connectors between PCBs. In addition, microstrip or strip PCB lines can also be used for high-frequency applications.

[0028] Common bus line signal transmission methods include single-ended signaling and differential signaling. In applications requiring high-speed communication, these methods can also be further optimized in terms of power consumption and pin utilization (especially these aspects in high-speed communication). The recently proposed vector signaling method can achieve a more optimized trade-off in terms of power consumption, pin utilization and noise robustness of the inter-chip communication system. This type of vector signaling system converts the digital information at the transmitter end into different representation spaces in the form of vector codewords, and selects different vector codewords according to the characteristics of the transmission channel and the design constraints of the communication system to make a better trade-off between power consumption, pin utilization and speed. This process is referred to as "encoding" in this application. The encoded codeword is sent from the transmitter to one or more receivers in the form of a set of signals. At the receiver end, the received signal corresponding to the codeword is converted back to the original digital information representation space. This process is referred to as "decoding" in this application.

[0029] Regardless of the encoding method, the signal received by the receiving device must be sampled at intervals (or its signal value must be recorded in other ways), and the sampling interval must be such that the sampled value can best represent the original transmitted value regardless of the delay, interference and noise conditions of the transmission channel. This clock data recovery (CDR) process must not only determine the appropriate sampling timing, but also may need to perform this determination step continuously to achieve dynamic compensation for different signal propagation conditions.

[0030] Many known CDR systems employ a phase-locked loop (PLL) or a delay-locked loop (DLL) to synthesize a local receive clock having a frequency and phase suitable for achieving accurate receive data sampling. Summary of the invention

[0031] In order to reliably detect data values ​​transmitted via a communication system, a receiver must be able to accurately measure the amplitude of the received signal value at carefully selected points in time. Currently, there are various known methods that can facilitate such reception measurements, including methods that receive one or more dedicated clock signals associated with the transmitted data stream, methods that extract embedded clock signals from the transmitted data stream, and methods that synthesize a local receive clock based on known properties of the transmitted data stream.

[0032] Generally speaking, the receiver-side implementation of such timing methods is called clock data recovery (CDR) and usually utilizes a phase-locked loop (PLL) or delay-locked loop (DLL) to synthesize a local receive clock with the desired frequency and phase characteristics.

[0033] In various PLL and DLL implementations, the relative phases of the received reference signal and the local clock signal (in some variant implementations, the relative frequencies thereof) are compared by a phase comparator to generate an error signal, which is then used to correct the phase and / or frequency of the local clock source to minimize the error. Since the feedback loop behavior will result in a fixed phase relationship (e.g., a phase offset of 0 or 90 degrees) between the reference signal and the local clock for a given PLL implementation, the phase offset is usually set to a target value (e.g., a phase offset of 45 degrees) different from the above value by introducing an additional fixed or variable phase adjustment amount to facilitate data detection at the receiver.

[0034] In the following method and system: receiving N local clock signal phases and M reference signal phases, where M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2; generating multiple partial phase error signals, each partial phase error signal is formed at least in part by comparing (i) a corresponding phase among the M reference signal phases with (ii) a corresponding phase among the N local clock signal phases; generating a composite phase error signal by adding the multiple partial phase error signals; and using the composite phase error signal to adjust the fixed phase of the local oscillator in a responsive manner.

[0035] In some embodiments, M=1, and the composite phase error signal is generated by adding N partial phase error signals. Alternatively, the plurality of partial phase error signals include M=N partial phase error signals, and a single partial phase error signal is generated using a given phase among the N local clock signal phases and a given phase among the M reference signal phases. In other alternative embodiments, the plurality of partial phase error signals include M×N partial phase error signals, and each of the N local clock signal phases is compared with each of the M reference signal phases.

[0036] In some embodiments, a corresponding weight value is applied to each of the plurality of partial phase error signals. In some embodiments, the weight value is selected according to an M×N matrix.

[0037] In some implementations, the M reference signal phases are received from a delay locked loop that processes an input reference signal.

[0038] In some embodiments, at least one of the N local clock signal phases is generated by a phase interpolator that processes a local oscillator signal and a phase offset signal. In some embodiments, the generation of at least one of the N local clock signal phases includes inserting four phases using four differential pairs within the phase interpolator, wherein each of the four phases is inserted according to a corresponding differential pair connected to an independently adjustable current source.

[0039] In some embodiments, at least one partial phase error signal is formed by a pair of flip-flops, wherein a given phase among the M reference signal phases clocks a first flip-flop in the pair of flip-flops, and a given phase among the N local clock signal phases clocks a second flip-flop.

[0040] In some embodiments, each partial phase error signal is an analog signal generated by a corresponding charge pump, which receives a corresponding charge pump control signal, and the corresponding charge pump control signal is generated based on a corresponding comparison between a corresponding phase among the M reference signal phases and a corresponding phase among the N local clock signal phases.

[0041] In the embodiments described in the present application, by combining the above-mentioned phase detection element with the above-mentioned phase adjustment element, the circuit node capacitance and circuit delay are reduced, thereby improving the loop stability and PLL locking characteristics, including reducing clock jitter and improving power supply noise suppression by increasing the loop locking bandwidth.

[0042] In other embodiments described in the present application, the received reference clock signal is converted into multiple reference clock phases by a DLL, thereby converting the phase comparison operation of the PLL into multiple comparisons between the reference clock phase and the local clock phase, and then the sum or weighted sum of the multiple comparison results is used as the error feedback signal of the PLL. In another embodiment described in the present application, multiple comparisons are made between a single received reference clock phase and multiple local clock phases, and the weighted sum of the multiple comparison results is used as the error feedback term of the PLL. In at least one such other embodiment, the weighted sum includes a two-dimensional time domain filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A block diagram of an implementation capable of encoding and sending five data bits and one clock over an eight-wire communication channel.

[0044] Figure 2 For a Figure 1 Block diagram of a transmitter-compatible receiver implementation.

[0045] Figure 3 For a Figure 2 Block diagram of an implementation of a clock recovery circuit used by a receiver.

[0046] Figure 4A , Figure 4B and Figure 4C Shown are three phase comparator implementations suitable for use in a phase-locked loop element of a clock recovery circuit.

[0047] Figure 5 The figure is a schematic diagram of an implementation method that integrates an XOR phase comparator and a clock phase interpolator.

[0048] Fig. 6A is a schematic diagram of a clocked data latch; Figure 6B A schematic diagram of another implementation of a clocked data latch with an integrated clock phase interpolator.

[0049] Fig. 7A and Figure 7B It is a schematic diagram of an implementation method that integrates a state machine phase comparator and a clock phase interpolator.

[0050] Figure 8 A schematic diagram of a charge pump implementation suitable for further integration with a phase comparator implementation.

[0051] Fig. 9 A block diagram of another embodiment of comparing multiple reference clock phases with multiple local clock phases.

[0052] Fig.10A block diagram of another embodiment of performing multiple comparisons between a single reference clock and multiple local clock phases.

[0053] Fig.11A is a weighted XOR phase comparator according to some embodiments.

[0054] Fig. 11B A block diagram of an implementation of a matrix phase comparison of M reference phases and N local clock phases.

[0055] Fig. 12A and Fig. 12B for Figure 5 An alternative block diagram of an integrated phase comparator and phase interpolator is shown.

[0056] Fig.13A is a timing diagram of a folded phase comparator according to some embodiments.

[0057] Fig. 13B is a timing diagram of reverse clipping effect according to some embodiments.

[0058] Fig.14A and Fig. 14B 2 are timing diagrams of an array XOR phase comparator and a single XOR phase comparator according to some embodiments, respectively.

[0059] Fig.15 is a flow chart of a method according to some embodiments. DETAILED DESCRIPTION

[0060] As described in Cronie 1, Cronie 2, Cronie 3, and Cronie 4, vector signaling codes can be used to form a very high bandwidth data communication link, for example, between two integrated circuit devices within a system. Figure 1 In the embodiment shown, vector signaling code symbols are sent via multiple data communication channels, which work together to send the codewords of the vector signaling code. Depending on the specific vector signaling code used, the number of channels that make up the communication link can be as few as two or as many as eight or more, and one or more clock signals can be sent on different communication channels, or the clock signal can be sent as a sub-channel component of the vector signaling code. Figure 1 In the illustrated embodiment, the communication link 120 is comprised of eight lines 125 that collectively transmit five data values ​​100 and a clock signal 105 between the transmitter 110 and the receiver 130 .

[0061] Each symbol (e.g., each symbol transmitted in any single communication channel) may use multiple signal levels (typically 3 or more levels). When operating at channel rates above 10 Gbps, deep pipelined or parallel signal processing is required, further complicating the receive process and rendering the known receive methods where the previously received value is the current received value inoperable.

[0062] The embodiments described in this application can also be applied to existing permutation and combination sorting methods that are not covered by the vector processing methods described in "Cronie 2", "Cronie 3", "Cronie 4" and / or "Tajalli 1". More generally, these embodiments can be applied to any communication or storage method that requires the coordination of multiple channels or channel elements to generate a coherent overall result.

[0063] Receiver Data Detection

[0064] In the following, various embodiments are described with reference to the typical high-speed receiver implementation in Stewart 1 as the background. This implementation is for illustrative purposes only and does not constitute a limitation.

[0065] like Figure 2 As shown, the exemplary data receiver includes eight identical continuous time linear equalization (CTLE) processing stages 210 for processing the previously Figure 1 The signals received by the eight lines shown as 120 are processed.

[0066] As described in Tajalli 1, Holden 1, and Ulrich 1, efficient detection of vector signaling codes can be achieved by linearly combining sets of input signals with multiple-input comparators (MICs) or mixers. For the 5b6w code used in the example receiver above, detection of the five data bits can be achieved by processing a weighted subset of the six received input data signals with five such mixers, without further decoding. Similarly, clock signal detection can be achieved by processing a combination of two received clock signals with an additional mixer. Figure 2 In the embodiment, the received equalized signal is processed by the set of six MIC mixers 220 to generate six detected signals MIC0 to MIC5.

[0067] Because of the high data rates involved, multiple parallel receive processing stages may be used in the exemplary receiver. In one embodiment, the five detected data signals MIC0-MIC4 are processed by four parallel receive data processing stages, each stage 230 including five data samplers and downstream buffers. The outputs of the four stages are then recombined into a receive data stream. Figure 2 In the illustrated case, this reassembly process is performed by multiplexer 240 .

[0068] Clock recovery circuitry (also known in the art as clock data recovery or CDR) supports the above sampling measurements by extracting timing information from the data line itself, or from a dedicated clock signal input, and using the extracted information to generate a clock signal to control the time interval used by the data line sampling device. The actual clock extraction operation may be performed by well-known circuits such as phase-locked loops (PLLs) or delay-locked loops (DLLs), which in turn may generate higher frequency internal clocks, multiple clock phases, etc. to support the operation of the receiver. Figure 2 In an embodiment, the detected clock signal is obtained by MIC5 and then processed 300 to extract a sampling clock with correct timing for the four data processing stages.

[0069] Phase-Locked Loop Overview

[0070] Phase-locked loops (PLLs) are well described in the literature. A typical PLL consists of a phase comparator that compares an external reference signal to an internal clock signal, a low-pass filter that generates a clock signal by smoothing the resulting error value, and a variable frequency clock source (typically a voltage-controlled oscillator (VCO)) that is controlled by the smoothed error value and generates the internal clock signal for processing by the phase comparator. In a well-known variation of the PLL design, a clock divider may also be provided between the VCO and the phase comparator to phase lock the higher frequency clock output to the lower frequency reference signal.

[0071] In an alternative embodiment, the variable frequency clock source is replaced by a variable delay element so that its output (optionally a plurality of tapped outputs) represents one or more successive time-delayed versions of the original input signal rather than successive oscillator cycles to be phase-compared with a reference input signal. For the purposes of this application, a delay locked loop (DLL) is considered to be functionally equivalent to a PLL in such applications, particularly in relation to these constituent elements of a phase comparator, a phase interpolator, and a charge pump.

[0072] There are many types of phase comparators known in the art. As a non-limiting example, Figure 4A The simple XOR (exclusive OR) gate shown can be used to compare two square wave signals. It can be seen by those skilled in the art that such a digital XOR output is a variable duty cycle waveform that, when low pass filtered to an analog error signal, can generate a proportional error signal centered at the center of its analog signal range when the two input signals have a 90 degree phase offset relationship.

[0073] Figure 4B The state machine phase comparator with a more complex structure is shown, which is composed of two edge-triggered latches, which are clocked by the reference clock signal and the internal clock signal respectively, wherein the first received clock edge causes one of the two output terminals "front" and "rear" to start generating an output signal, and once any of the two output terminals starts to output a signal, each latch is reset immediately to wait for the next comparison time interval. In other embodiments, a timing delay can be set in the reset path to achieve additional reset pulse timing control. Generally speaking, the two phase comparison outputs of "front" and "rear" are used as the "up" and "down" inputs of the charge pump, respectively, and the output of the charge pump is the above-mentioned analog error value. That is, the rising signal can turn on the first transistor circuit that charges the capacitor, thereby increasing the analog voltage; and the falling signal can turn on the second transistor circuit that discharges the capacitor, thereby reducing the voltage. Therefore, when the phase offset between the two input clock signals is 0 degrees, the analog error value will remain unchanged and the phase-locked loop will be in a stable locked state. There are many known equivalent state machine phase comparator implementations in the art, which can be equally applied in this application, but this does not mean to limit the present invention. Some state machine implementations may be more sensitive to both the phase difference and the frequency difference between the input signals, thereby helping to achieve the locked state of the PLL more quickly at startup.

[0074] like Figure 4C As shown, a single edge-clocked D flip-flop can also be used as a phase comparator. At each rising edge of the local clock (CkPLL), the D input samples the state of the reference input (CkRef), a square wave in this case. If its state is "high" (e.g., it has undergone a transition), the Q output is also "high", indicating that the reference signal is "ahead"; if its state is "low" (e.g., it has not undergone a transition), the Q output is also "low", indicating that the reference signal is "latter". This so-called binary (Bang-Bang) phase comparator provides less subtle differences in the error results than the above example, allowing for a higher level of filtering to achieve loop stability.

[0075] Those skilled in the art will appreciate that similar functional operations can be achieved regardless of the type of phase comparator used in the PLL design, so in general terms, the choice of phase comparator is not limiting. In addition, secondary design factors including lock time, stability, power consumption, etc. must also be taken into account during the design process.

[0076] Receiver Clock Recovery

[0077] Figure 3The illustrated receiver uses a PLL implementation. The PLL uses the received clock signal R5 as a phase-locked reference signal for its clock. In some embodiments, a logic level shifter 310 may be used as an interface between the signal level provided by the MIC for detection and the preferred phase comparator input level when appropriate. The phase comparator 320 generates an output value after comparing the reference clock with the local clock provided by the VCO. The output value provides an error value after low-pass filtering for subsequent correction of the operating frequency of the VCO 340. In some embodiments, the phase comparator 320 outputs a digital waveform, which needs to be converted into an analog error signal through implicit or explicit digital-to-analog conversion, or through an interface element such as a charge pump. In some embodiments, the conversion can be combined with the entire low-pass filtering operation or a portion thereof through a digital filtering action, and the combination is only used as a non-limiting example. The digital filtering action is illustrated as a charge pump switching action controlled by a digital control signal for generating an analog signal output.

[0078] In at least one embodiment, a ring oscillator 340 consisting of a series of identical gate devices forming a closed loop is used as the internal voltage controlled oscillator (VCO) timing source of the PLL. The frequency of the VCO can be changed by simulating and adjusting at least one of the gate propagation delay, gate rise and fall time, and gate switching threshold of the ring oscillator. This can be achieved by a switched capacitor bank, wherein, as a non-limiting example, capacitive elements are selectively combined in parallel and / or series by applying a digital control signal to change the RC time constant. In addition, the output switching rise and fall time can be changed by increasing or decreasing the current source used to drive the ring oscillator gate, thereby achieving adjustment of the effective delay. By sampling the output at equal intervals along the series of gates that make up the ring oscillator (i.e., sampling every same number of ring oscillator gates), four data phase sampling clocks can be obtained, which are respectively recorded as 0 degree clock, 90 degree clock, 180 degree clock, and 270 degree clock in this application.

[0079] In one embodiment, the ring oscillator is composed of eight identical groups of logic gates (i.e., a group of inverter circuits) so that the phase difference between each two groups is 45 degrees. In this embodiment, for example, the 0 degree, 90 degree, 180 degree and 270 degree outputs can be obtained from the second, fourth, sixth and eighth outputs respectively. Since many variations of such designs are known in the art, the number of components in the ring oscillator and the specific taps that provide specific outputs should not be understood as constituting any limitations. For example, the 0 degree tap can be in any position, because it can be appreciated by those skilled in the art that the PLL can achieve alignment of the ring oscillator phase with the external reference phase during normal operation regardless of the starting phase. Similarly, in other equivalent designs, the output clock phase may not have a square wave duty cycle, an example of which is to use an AND gate (AND gate) or an OR gate (OR gate) that obtains inputs from different tap positions. In the exemplary receiver, the VCO preferably operates at a multiple of the receive reference clock frequency, so a frequency divider 350 is also provided upstream of the phase comparator to divide the VCO output by a corresponding factor. In one embodiment, a binary (factor of 2) frequency divider 350 is used to obtain the correct sampling clock rate. In another embodiment, the frequency divider is not used, and the VCO output is directly provided to the phase interpolator.

[0080] Each of the four sampling clock phases is appropriately timed to sample received data for one of the four parallel processing stages. Specifically, internal clock ph000 is aligned to optimally trigger the data sampler in processing stage 0, internal clock ph090 is aligned to optimally trigger the data sampler in processing stage 1, internal clock ph180 is aligned to optimally trigger the data sampler in processing stage 2, and internal clock ph270 is aligned to optimally trigger the data sampler in processing stage 3.

[0081] In order to offset the overall phase of the locked PLL signal from the reference clock input phase, a local clock output provided to the phase comparator is obtained from a phase interpolator 360 whose output phase is controllably intermediate between its input clock phases. In this way, not only can the PLL be locked to its fixed phase relationship, but the internal clock signal provided by the ring oscillator 340 is also offset from the fixed phase by the amount of phase delay introduced by the phase interpolator 350 under the control of the signal phase offset correction function. Phase interpolators are known in the art, such as those described in Buchwald 1 and Tajalli 2.

[0082] In one embodiment, the phase interpolator 360 receives a plurality of local clock phases having a phase difference of 90 degrees from the ring oscillator 340. The phase interpolator can be controlled to select two adjacent clock input phases and then interpolate between them to generate an output having a selected phase offset between the two selected values. For the purpose of description, it can be assumed that the phase comparator used causes the PLL to lock so that the phase difference between the two phase comparator inputs is zero. Thus, in this example, when clock phases of 0 degrees and 90 degrees are applied as inputs in the phase interpolator, the phase of the PLL can be adjusted to lead the reference clock input by 0 to 90 degrees.

[0083] It is easy to understand that using two clocks of other degrees and / or other phase comparator designs can still achieve the same result with similar phase offset, but as mentioned above, the locked phase difference in this case is different from the above example. It can be seen that the specific selected phase clock and the specific phase comparator design described in this application are not limiting.

[0084] Phase Comparator with Interpolator

[0085] As communication channel data rates increase, circuit delays and effective loop response bandwidth limitations caused by intrinsic and parasitic circuit node capacitances make it increasingly difficult to maintain acceptable PLL lock range and accuracy. Figure 5 An embodiment that provides improved response characteristics suitable for such high speed operation is shown. Those skilled in the art will recognize that this embodiment is a CMOS design that provides symmetrical operation for positive and negative output excursions and integrates elements from both phase interpolator and phase comparator designs. This tight integration reduces node capacitance and facilitates the required high speed operation, and its balanced differential structure simplifies control of charge and discharge currents.

[0086] Consistent with conventional designs, the VCO of the PLL (or a clock divider driven by the VCO) provides a local oscillator input to phase interpolator elements 510 and 515 for collectively setting the effective local clock phase. As shown, there are four local oscillator phases that are offset by 90 degrees from each other, which is equivalent to two phases in an orthogonal relationship and their complementary signals, and are therefore labeled +I, +Q and -I, -Q, respectively, so that a full 360-degree phase adjustment, or "four-quadrant" phase adjustment, can be achieved. In other embodiments, the number of local oscillator phases can be reduced to two, or oscillator phases with a phase difference different from 90 degrees can be used, or the clock phase can be selected from a set of more than four inputs; as a non-limiting example, at least two clock phases to be inserted can be selected from a set of eight input clock phases.

[0087] In a first embodiment, the phase interpolator element 510 includes four mixing elements, each of which includes a pair of differential transistors and a controlled current source, and has a common differential output terminal driven by the four parallel mixing elements. Therefore, the configuration of the current source IA(i) controls the amount of local oscillator phase +I provided to the common output terminal ckp. Similarly, the current source IA(-i) controls the amount of complementary output phase -1 in the output, IA(q) controls the amount of phase +Q, and IA(-q) controls the amount of phase -Q. It is obvious to those skilled in the art that the four current sources can be configured to produce an output clock at the ckp terminal having any desired phase relationship relative to the PLL local clock input.

[0088] Similarly, the current sources IB(i), IB(-i), IB(q), and IB(-q) of the phase interpolator element 515 can be configured to obtain an output clock at the Ckn terminal having any desired phase relationship relative to the PLL local clock input. In some embodiments, CkPLLp and CkPLLn can be configured to have a complementary relationship to provide balanced complementary positive and negative current amplitudes to the phase comparator 520. However, non-complementary IA and IB values ​​can also be configured to obtain specific results. As a non-limiting example, in one embodiment, the IA and IB values ​​can be adjusted separately to obtain a higher resolution phase adjustment compared to an embodiment in which the IA and IB values ​​are maintained in full complement.

[0089] The second input of the phase comparator 520 is an external reference clock CkRef+ / CkRef-, which is used to generate a phase error output current VCOctl+NCOctl-. In an improved embodiment, the two external reference clocks have opposite polarities, but do not necessarily have complementary phases, so that the positive polarity comparison and the negative polarity comparison represent different phase comparisons. This improved embodiment can be combined with non-complementary IA and IB bias configurations to achieve independent local clock phase adjustments during the above-mentioned different phase comparison processes. That is, in one embodiment, the CkRef input at the top of the phase comparator 520 is a first phase selected from the reference clock phases available in the circuit, and the current IA is adjusted to provide a corresponding insertion phase offset relative to the selected first phase. At the same time, the CkRef input at the bottom of the phase comparator 520 is a second phase selected from the reference clock phases available in the circuit, and the current IB is adjusted to provide a corresponding insertion phase offset relative to the selected second phase. Among them, these two relative phase offsets are equal offsets.

[0090] The values ​​of the phase interpolator current sources may be configured by external control logic, including but not limited to, hardware configuration registers, control processor output registers, and hardware CDR adjustment logic.

[0091] Other Phase Comparator Implementations

[0092] Figure 5 The phase comparator 520 in the illustrated embodiment is Figure 4A The same XOR device is used to generate the phase error output VCOctl by mixing the local clock CkPLL with the external reference clock CkRef. Fig. 12A In other embodiments shown, a folded phase comparator 1220 is used, which is driven by the current generated by the combination of the current sink terminal Ifix2 and the phase interpolator 510 and the current source Ifix1 and the phase interpolator 515. Fig. 12A The folded phase comparator embodiment shown in FIG. 1 is further described in detail. Consistent with the above embodiment, the current sources IA(i), IA(-i), IA(q), and IA(-q) are configured to insert the PLL clocks i, -i, q, and -q into the interpolator outputs CkPLLp and CkPLLp in a desired manner. and the current sources IB(i), IB(-i), IB(q), and IB(-q) are configured to insert the PLL clocks i, -i, q, and -q into the interpolator outputs CkPLLn and CkPLLn in the desired manner. . The phase comparator 1220 is also driven by the received reference clocks CkRef+ and CkRef- to produce phase comparison results: phase error (+) and phase error (-). In some embodiments, the relative DC component of the inserted clock signal can be determined by monitoring the circuit node marked as "circuit balance feedback", and then the adjustment of the relative DC component can be achieved by adjusting the value of the configured current source in 510 and 515. In some embodiments, each current source IA and IB receives seven control bits. It should be noted that embodiments of the present invention are not limited to receiving seven control bits, and any number of control bits can be used, for example, based on the design constraints of the resolution of the phase interpolator. In some embodiments, the current sources IA and IB are equal (for example, for + / -i and + / -q, IA=IB). In such embodiments, the resolution of the phase interpolators 510 and 515 is 7 bits. In other embodiments, additional resolution can be achieved by shifting IB relative to IA, or by shifting IA relative to IB. In an exemplary embodiment, IA=IB+8, where 8 is the decimal shift amount of the control bit of each current source IB obtained by adding the control bit of each current source IA. In such an embodiment, the P-side phase interpolator 510 and the N-side phase interpolator 515 receive two different VCO phases, and the phase comparator collects information from different phases of the VCO. Since the phase interpolators 510 and 515 fuse the information from different phases of the VCO, the PLL has more detailed PLL phase information, and the bandwidth of the PLL is higher than that of a conventional PLL.

[0093] The implementation of "IA=IB+shift amount" is a special case of a matrix phase comparator with two partial phase comparators. The first partial phase comparator (N-side XOR comparator) compares the reference phase with a set of VCO feedback phases, while the second partial phase comparator (P-side XOR comparator) compares the reference clock phase with another set of VCO feedback phases. The implementation of the matrix phase comparator will be described in more detail below.

[0094] In some embodiments, the Fig. 12A The foldable structure shown. Fig. 12A and Figure 5The illustrated embodiment is similar, but differs in that the phase comparator 520 is replaced by a folded phase comparator 1220. As shown, the folded phase comparator 1220 includes current sources Ifix1 and Ifix2, which can be configured to provide a larger voltage margin to the PMOS phase interpolator current source IA and the NMOS phase interpolator current source IB. In addition, the phase comparator 1220 includes a pair of transistor branches connected to CkPLLp and CkPLLn. For illustrative purposes, it is assumed that the phase interpolators 510 and 515 only have IA(i) and IB(i), and these two current sources are turned on respectively to represent the VCO phase ph0000. When CkRef is offset by 90 degrees relative to ph0000, the folded phase comparator 1220 will be in a locked state. As Fig.13A As shown, during the first 180 degrees (1) of a cycle, for the previous 90 degrees (2), the PMOS phase interpolator 510 charges the (-) end of the phase error signal with a current Ip through transistor 1206. At the same time, the NMOS phase interpolator 515 discharges the (-) end of the phase error signal with a current In through transistor 1208. Similarly, during the next 90 degrees (3), the (+) end of the phase error signal is charged with a current Ip through transistor 1202, and the (+) end is discharged with a current In through transistor 1204. As shown in the figure, Ifix2 absorbs a fixed amount of current from the current provided by the PMOS phase interpolator 510, while Ifix1 provides a certain amount of current to the NMOS phase interpolator 515 to prevent the current source in the NMOS phase interpolator from absorbing excessive current from the phase error signal. This technology achieves a reverse clipping effect. It can be noted by those skilled in the art that when the amplitude of each current Ifix is ​​adjusted by an equal amount, the range of the phase error signal can be affected. In some implementations, increasing the amplitude of Ifix will reduce the amplitude range of the phase error signal, while reducing the amplitude of Ifix will increase the amplitude range of the phase error signal. This relationship is as follows: Fig. 13B shown.

[0095] Fig. 13B This is a timing diagram of the reverse clipping feature described above. Fig. 13B The amplitude of the current Ip at two Ifix2 values ​​A and B within the first 180 degrees (1) is shown, where A>B. As shown, in the case of Ifix2=A, the amplitude of Ip is smaller. When Ifix2=B, the amplitude of Ip is relatively higher. It can be noted by those skilled in the art that a similar effect can be produced in the case of In discharge of the folded phase comparator 1220.

[0096] In some embodiments, Fig. 12AAs shown, the last 180 degrees (4) can be used to implement circuit balance feedback. Under the circuit balance feedback phase (4), current charging can be performed through the PMOS phase interpolator 510, and current discharging can be performed through the NMOS phase interpolator 515. If there is an imbalance between the charge / discharge currents, the circuit balance feedback signal will be a non-zero signal, thereby indicating the imbalance. The cause of the imbalance is, for example, a mismatch between transistors. The circuit balance feedback signal can then be used to adjust Ifix1 or Ifix2 to achieve a balance in the charge / discharge current. After reaching balance, the balance feedback signal becomes zero. In some embodiments, the voltage of the charge pump circuit can be monitored. If they are equal, it means that the circuit has reached the correct balance state, that is, Ip=In. Fig. 12B for Fig. 12A Simplified schematic of a phase comparator circuit.

[0097] Alternatively, the phase comparator described in Tajalli 4 may be used as 520 or 1220 to achieve equivalent high signal margin phase detection in an implementation using a low power supply voltage. In addition, in this implementation, 520 may also include Figure 4A , Figure 4B and Figure 4C All variants shown may be substituted with other phase comparators.

[0098] As an example of such an alternative embodiment, Figure 4B The state machine phase / frequency detector shown can be used with Figure 5 The phase interpolator design is combined with

[0099] Fig. 6A A schematic diagram of a conventional CML clocked latch implementation is shown. The latch is composed of output Q and The clocked feedback latch of the two results is composed of the state of the two results determined by the clocked differential input D and initialization. Figure 6B The same circuit is shown, but the phase of the clock source is adjusted by a phase interpolator 615. The operating principle of the phase interpolator is described above. Figure 5 Description.

[0100] When the general Figure 6B The clocked latch circuit is replaced by Figure 4B Each D flip-flop instance is formed Fig. 7A and Figure 7BAlternative embodiment shown. The D flip-flop 710 is clocked by the receive clock CkRef, which is passed through the phase interpolator 715. As an example for explanation purposes, if the phase offset is not set (or when the desired offset is 0 degrees), the current source IA will be set to the "mixing" input CkRef at a ratio of 100%, and the other three current sources are set to zero current. The D flip-flop 720 is clocked by the local clock CkPLL, which is obtained by setting the current sources IB(i), IB(-i), IB(q) and IB(-q) of the phase interpolator 725, and this setting further controls the relative proportions and polarities of the combined I and Q clocks. In one embodiment, as Figure 3 As shown, I is obtained from ph000, -I is obtained from ph180, Q is obtained from ph090, and -Q is obtained from ph270. In addition, the reset function of flip-flops 710 and 720 is driven by a simple CML OR gate 730.

[0101] It should be noted that in this embodiment, most of the functions of the phase interpolator 715 are disabled, and its setting purpose is only to maintain the same parasitic load characteristics as the phase interpolator 725 in the working state to maximize the circuit symmetry and minimize side effects such as detection deviation and drift by maintaining balanced load characteristics.

[0102] Integrated phase comparator, interpolator and charge pump

[0103] As mentioned above, the phase comparator output of the PLL is generally used to drive a charge pump circuit (CPC), which outputs an analog error signal used to control the VCO. The above-mentioned low capacitance and high circuit speed improvements achieved by integrating the PLL phase comparator with the clock adjustment phase interpolator can be further extended by further integrating the charge pump components in the same manner.

[0104] In this integrated implementation, Fig. 7A and Figure 7B The charge pump control signals UPp, UPn, DOWNp and DOWNn provided in the embodiment shown are Figure 8 The charge pump implementation shown is used to generate the IOUT output for direct control. CPC and reference voltage V REF Can be configured to I OUT The range of scaling and adjustment can be performed. Those skilled in the art may note that Figure 8 Very high circuit symmetry can be achieved at V REPLICA and I OUT Precise tracking between signal generation.

[0105] Figure 8Schematic diagram of a charge pump circuit with better charge / discharge current balancing function according to some embodiments. Circuit 800 includes two charge pumps 802 and 804 connected in parallel: two differential pairs in charge pump 804 generate output currents, which represent phase error signals generated by rising and falling pulses; as described below, the two differential pairs of charge pump 802 are used to set the discharge current to be equal to the charge current. Specifically, the current source I CPC By using a current mirror circuit to provide a corresponding bias voltage V BP The charging current level is set in such a way as to drive the top current sources 806 and 808 of the two charge pumps, thereby CPC The same is provided to each charge pump 802, 804. When UPn is low and the field effect transistor (FET) 810 is turned on, the node 812 is charged by the field effect transistor 806, 810. CPC The amount of current discharged through the bottom FET 816 when DOWNp is at a high signal level should restore node 812 to V under equilibrium conditions (i.e., no phase error). REF If the discharge current is too low and the voltage V REPLICA Rising to V REF Above, the amplifier 820 will increase the bias voltage V on the discharge current field effect transistor 818. BN , to increase the amount of discharge current to the same as the charging current I CPC equal, and makes the voltage V on node 812 REPLICA Restore to V REF On the other hand, if V BN If the discharge current set on the field effect transistor 818 is too high, the voltage V REPLICA will become too low, and amplifier 820 will then reduce the bias voltage V on discharge field effect transistor 818 BN Return the charge pump current to balance.

[0106] Other implementations may also be achieved through other equivalent combinations of phase comparators, phase interpolators, and charge pump elements.

[0107] Input reference signal oversampling

[0108] The reason is, for example, Fig. 7A and 7BThe reason for using the phase interpolator in an asymmetric manner as shown is that the local clock and the reference clock source are of different nature. The former is obtained from a multi-phase clock source (such as an oscillator or a frequency divider), which itself can provide a multi-phase input for the phase interpolation element. The latter is generally a single-phase clock obtained from the same receiving clock source.

[0109] In the prior art, Tan describes a combined DLL / PLL structure in which the VCO of the PLL uses two identical voltage-controlled delay lines as input delay lines, which act on the reference clock input and are controlled by a single feedback error signal. Ng and Chang also describe using the front-end DLL as a frequency multiplier to generate a very high frequency clock.

[0110] However, when such a controlled delay line is tapped, if the controlled delay line is set so that the differential delay between each tap is proportional to the time between the edges of the receiving clock, the receiving clock passing through the delay line will produce a set of outputs with certain multi-phase clock characteristics. As a non-limiting example, the equally spaced outputs of a four-tap delay line with a total delay similar to the reference clock period will produce outputs with similar characteristics to the orthogonal phase-controlled clock signal. In this example, when each such output is phase-compared with the correctly selected local clock phase, a more accurate total clock error signal can be generated for the VCO of the PLL by combining the generated series of phase error results. Among them, each delayed form of the receiving clock allows the clock from the VCO to have an additional phase comparison opportunity, thereby enabling the controlled loop to achieve a higher update rate and increase the loop bandwidth of the PLL. In this way, jitter can be reduced and better noise immunity can be achieved. In other words, through this technology, the update rate of the loop can be increased, thereby enabling the circuit to track and correct the effects of noise and jitter at higher frequencies.

[0111] In order for the delay phase comparison to provide meaningful information to the PLL, the delay interval provided by the delay line must be coordinated with the time periods between the local clock phases. This control approach can provide the delay element with many aspects of the delay locked loop (DLL). Fig. 9 As can be seen from the block diagram, an external clock reference input is provided to the PLL implementation 300 by DLL 910. After the received clock signal R5 is provided to the tapped delay line 916, a series of received clock phases 918 are generated. The DLL control loop is provided by the phase comparator 912, wherein the phase comparator generates an error value by comparing the received clock with the delayed clock, and the error value is low-pass filtered 915 to generate a delay adjustment signal for controlling the timing of the delay line.

[0112] Thus, in PLL 300, the above simple phase comparison ( Figure 3 320 in the figure) is implemented by a multi-phase comparator 920. In at least one embodiment, the phase of each received reference clock signal on N lines (N is, for example, equal to 2, 4, 8, etc., and may also include odd numbers to generate other phases such as 60, 120, 180, 240, 300, etc.) 918 is compared by an XOR gate with a different clock phase among the N local clock signal phases on line 965 of the phase interpolator 360. Each XOR gate output represents a partial phase error signal that can be converted into an analog signal value, and as described above, all such analog partial phase error signals are summed by a summing circuit 935 to generate a composite phase error signal for controlling the ring oscillator 340. In another embodiment, the summing 935 is implemented by a weighted summing node similar to the above-mentioned MIC mixer, and different weight values ​​selected in the summing can achieve further control of the static and dynamic operating characteristics of the PLL. Alternatively, the above-mentioned summing operation can also be achieved by driving a corresponding transistor circuit with each XOR output to inject charge into or remove charge from a capacitive element. In addition, Fig. 9 The PLL 340 in may be arranged to provide the required phase offset, wherein each inserted phase has the same offset relative to the tapped delay line signal with which it is to be XOR compared.

[0113] In some system environments, such as when a communication protocol employs multiple clock signals, the multi-phase reference clock may be obtained directly from the receiver.

[0114] The additional feedback information provided by the above-mentioned multiple comparison operations can also be obtained without the above-mentioned delay locked loop front end. Fig.10In the illustrated embodiment, a single received reference signal 1018 is input into a multi-phase comparator 920, where the single received reference signal is compared with each of two or more phases of a local clock signal 965. In one embodiment, a partial phase error signal is formed by an XOR partial phase comparator by comparing the phase of the single received reference clock phase 918 with different phases of the local clock signal 965 from the phase interpolator 360. Each partial phase error signal can be converted into an analog signal value, and as described above, a composite phase error signal for controlling the ring oscillator 340 can be generated by summing all such analog partial phase error signals. In another embodiment, the summation 935 is implemented by a weighted summation node similar to the above-mentioned MIC mixer, and different weight values ​​selected in the summation can achieve further control of the static and dynamic operating characteristics of the PLL. Specifically, by adjusting the weight values, additional closed-loop poles and / or zeros can be generated in the time domain transfer function of the PLL, thereby achieving further loop stability control.

[0115] Fig.14A The comparison timing diagram of the reference signal CKREF and the four VCO phases (feedback from PLL):

[0116] XOR(CKREF,VCO'000)

[0117] XOR(CKREF,VCO'090)

[0118] XOR(CKREF,VCO'180)

[0119] XOR(CKREF,VCO'270)

[0120] like Fig.14A The figures shown are assumed to be equal in all weight values. However, this assumption is purely for illustrative purposes and should not be considered limiting in any way. Fig.14A It also includes summing the four XOR outputs. It can be seen that in the locked state, the integral of the bottom waveform is zero, so the PLL is correctly locked. For convenience, Fig. 14B A conventional phase comparator based on XOR operation is also shown, in which the reference phase is compared with only one VCO phase. In the locked state, the reference phase is 90 degrees out of phase with the VCO phase, and the output of the XOR operation is a rectangular waveform with an average value of zero. Thus, it can be seen that the two waveforms ( Fig. 14B A simple XOR operation and Fig.14AThe difference between the phase comparator and the phase comparator is that the average value for a given period is zero in both cases and the PLL is locked. The implementation using a partial phase comparator array has more transitions than the implementation using a single XOR phase comparator. Since each transition carries information about the edge, more transitions means that the phase comparator can collect more information from the VCO and CKREF.

[0121] It should be noted that in the array XOR implementation, some comparisons may need to be completed using XNOR (exclusive NOR gates). In this way, system stability can be ensured by carefully selecting XOR or XNOR for different phase comparisons.

[0122] In at least one embodiment, the weight value used in the summation is set to decrease in proportion to the timing difference between the comparison clock phase and the "normal lock" phase of the PLL. As a non-limiting example, when the normal lock phase of the PLL is ph090, the comparison weight between ph090 and the received reference signal is 1; the comparison weight between ph000 and ph180 (such as one tap offset relative to the normal lock phase) is 1 / 2; the comparison weight between the received reference signal and ph270 (two taps offset relative to the normal lock phase) is 1 / 4; and so on. These different weighted comparison results are added to form a composite signal, which, after low-pass filtering 330, becomes the error value of the VCO 340 used to control the PLL.

[0123] In at least one embodiment using multiple phase comparators, when equal phase comparator weights are used, it has been observed that the multiple phase comparisons produce deterministic jitter at a rate of 12.5 GHz. Although the amplitude of the jitter is extremely small and the jitter occurrence rate is much higher than the loop filter cutoff frequency, the deterministic jitter can still be significantly reduced by adjusting the weight values ​​described above. Among them, the weight value decreases in proportion to the distance between it and the main reference signal sample. In some embodiments, a discrete time domain filter is formed by using different weight values ​​in the comparator circuit. This feature can be used to simplify the design of the analog filter 330. For example, when the weight values ​​used are correct, discrete zero values ​​can be constructed in the time domain transfer function, thereby creating conditions for achieving loop robustness.

[0124] Consistent with the above examples, other implementations may be obtained through other equivalent combinations of phase comparators, phase interpolators, and charge pump elements.

[0125] Matrix Phase Comparison

[0126] The multi-phase comparison between the multiple phases of the received reference signal and the multiple phases of the local PLL clock can also be extended to a matrix phase comparator. An implementation method thereof is as follows: Fig. 11B As shown, each phase comparator 1110 in the matrix (in Fig. 11B An implementation of a partial phase comparator (which may be referred to as a partial phase comparator) is Fig.11A A single phase comparator 1110 is shown in FIG. For the sake of illustration, the partial phase comparators in the figure are arranged in a 4×4 matrix, however, this arrangement is for illustration only and does not constitute a limitation. In various embodiments, a rectangular, square or sparse matrix with any M and N dimensions is also used, and the elements of the matrix can be composed of any partial phase comparators described in this application, and any weighting factor calculation method described in this application can be optionally used. In this application, a sparse matrix refers to any embodiment in which the weight value of at least one of the elements is zero.

[0127] In a full matrix comparison, each of the M phases from the received reference signal is phase compared with each of the N phases from the local clock, which can be received from a PLL, or directly from a VCO or various other clock sources. For illustrative purposes, the N local clock phases are received from the PLL. Each resulting phase error signal is weighted by a preset or predetermined value, and all (M×N) weighted results are summed to produce a total error result. One of the phase comparators is, for example, Fig.11A As shown in 1110 , the comparator is composed of an XOR phase comparator 1112 , and the output of the XOR phase comparator is fed to a weighting factor 1118 .

[0128] Fig. 11B One embodiment of the full matrix phase comparator 1120 in the embodiment is composed of M×N instances of partial phase comparators 1110, each of which receives one of the M reference signal phases (referred to as CkRef0, CkRef1, CkRef2, CkRef3 in this application) and one of the N local clock phase input phases (referred to as CkPLL0, CkPLL1, CkPLL2, CkPLL3 in this application) and generates a weighted result (such as multiple partial phase error signals 1131, 1132, 1133, 1134). The weighted result is input into the summing function 935 to generate a composite phase error signal 1145.

[0129] It can be seen by those skilled in the art that the above Fig. 9The multi-phase comparator 920 in is equivalent to an example of a partial use of the present matrix comparator, that is, only the comparators on the matrix diagonal are instantiated. In terms of function, when the weight values ​​of the comparators on the complete matrix diagonal are set to non-zero values ​​and the weight values ​​of all other comparators are set to zero values, exactly the same result can be obtained. Therefore, through the selective configuration of the matrix weighting factor, the above-mentioned other functions including the simulation of phase offset and the introduction of loop time domain zero value can be realized in a similar manner.

[0130] Fig.15 15. A flow chart of a method 1500 according to some embodiments is shown. As shown, the method 1500 includes: in block 1502, receiving N local clock signal phases and M reference signal phases, where M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2. The method also includes: in block 1504, generating a plurality of partial phase error signals, each partial phase error signal being formed at least in part by comparing (i) a corresponding phase among the M reference signal phases with (ii) a corresponding phase among the N local clock signal phases. In block 1506, generating a composite phase error signal by adding the plurality of partial phase error signals, and then adjusting a fixed phase of a local oscillator 1508 with the composite phase error signal.

[0131] In some embodiments, M=1, and the composite phase error signal is generated by adding N partial phase error signals. Alternatively, the plurality of partial phase error signals include M=N partial phase error signals, and a single partial phase error signal is generated using a given phase among the N local clock signal phases and a given phase among the M reference signal phases. In other alternative embodiments, the plurality of partial phase error signals include M×N partial phase error signals, and each of the N local clock signal phases is compared with each of the M reference signal phases.

[0132] In some implementations, a corresponding weight value is applied to each partial phase error signal among the plurality of partial phase error signals.

[0133] In some implementations, the M reference signal phases are received from a delay locked loop that processes an input reference signal.

[0134] In some embodiments, at least one of the N local clock signal phases is generated by a phase interpolator that processes a local oscillator signal and a phase offset signal. In some embodiments, the generation of at least one of the N local clock signal phases includes inserting four phases through four differential pairs within the phase interpolator, each of the four phases being inserted according to a corresponding differential pair connected to an independently adjustable current source.

[0135] In some embodiments, at least one partial phase error signal is formed by a pair of flip-flops, wherein a given phase among the M reference signal phases clocks a first flip-flop in the pair of flip-flops, and a given phase among the N local clock signal phases clocks a second flip-flop.

[0136] In some embodiments, each partial phase error signal is an analog signal generated by a corresponding charge pump, which receives a corresponding charge pump control signal generated based on a corresponding comparison between a corresponding phase among the M reference signal phases and a corresponding phase among the N local clock signal phases.

[0137] Other Implementations

[0138] Transmitted via two dedicated clock lines and from Figure 2 The clock signal received at MIC5 in the example is received in the same manner as the clock signal transmitted as a vector signaling code subchannel carrying the same data and received, for example, from MIC4. This method of embedding the clock in the vector signaling code subchannel is described in Shokrollahi 2 and Holden 3. All clock embedding implementations described therein can be combined with the PLL and timing control mechanisms described in this application to produce beneficial effects, but this does not constitute any limitation.

[0139] Similarly, other known methods for clock signal transmission using data line edge transitions can also be combined with the PLL and timing control mechanism described in this application. Among them, the vector signaling code that is particularly suitable for combination is the vector signaling code that can ensure the transition density for a long time, such as the vector signaling code described in "Shokrollahi 1".

Claims

1. A method, characterized in that include: Acquiring multiple reference signal phases and acquiring multiple local oscillator signal phases; At least three partial phase error signals are formed, wherein each partial phase error signal is formed in the following manner: generating a variable duty cycle waveform based on an exclusive-OR (XOR) phase comparison between the reference signal phase and the local oscillator signal phase, wherein the duty cycle of the variable duty cycle waveform represents a phase error between the reference signal phase and the local oscillator signal phase; and providing the variable duty cycle waveform as a charge pump control signal to a corresponding charge pump to generate the partial phase error signal; injecting or deleting charge into a capacitive element according to the at least three partial phase error signals to sum the at least three partial phase error signals to generate a composite phase error signal; and The composite phase error signal is provided to an oscillator that generates the plurality of local oscillator signal phases.

2. The method according to claim 1, characterized in that The multiple reference signal phases include M phases, the multiple local oscillator signal phases include N phases, wherein the at least three partial phase error signals include M=N partial phase error signals, wherein N and M are integers greater than 2.

3. The method according to claim 1, characterized in that The plurality of reference signal phases comprises M phases, the plurality of local oscillator signal phases comprises N phases, and wherein the at least three partial phase error signals comprises M x N partial phase error signals.

4. The method according to claim 1, characterized in that Further comprising applying a weighting factor to each of the at least three partial phase error signals.

5. The method according to claim 4, characterized in that The at least three partial phase error signals have different weighting factors.

6. The method according to claim 1, characterized in that The local oscillator signal phase is obtained by a phase interpolator.

7. The method according to claim 1, characterized in that Further comprising low pass filtering the composite phase error signal.

8. The method according to claim 1, characterized in that The multiple reference signal phases are obtained through a reference clock signal transmitted via a sub-channel of a vector signaling code.

9. The method according to claim 1, characterized in that The multiple reference signal phases are acquired through data transitions.

10. The method according to claim 9, characterized in that The method further includes detecting the data transition at outputs of a plurality of multi-input comparators, wherein each of the multi-input comparators detects a data stream carried by a corresponding sub-channel vector of a plurality of mutually orthogonal sub-channel vectors.

11. A device, characterized in that: include: A multi-phase comparator, used to obtain multiple reference signal phases and multiple local oscillator signal phases, wherein the multi-phase comparator comprises: a plurality of partial phase comparators for forming at least three partial phase error signals, wherein each partial phase error signal is formed by generating a variable duty cycle waveform based on an exclusive-OR (XOR) phase comparison between the reference signal phase and the local oscillator signal phase, wherein a duty cycle of the variable duty cycle waveform represents a phase error between the reference signal phase and the local oscillator signal phase; and a plurality of charge pumps for receiving each of said variable duty cycle waveforms as charge pump control signals and generating said partial phase error signals in a responsive manner; a capacitive element for injecting or deleting charge into or from the capacitive element based on the at least three partial phase error signals to generate a composite phase error signal; and A local oscillator is configured to receive the composite phase error signal and responsively adjust a fixed phase of the local oscillator based on the composite phase error signal, wherein the local oscillator generates the plurality of local oscillator signal phases.

12. The device according to claim 11, characterized in that The multiple reference signal phases include M phases, the multiple local oscillator signal phases include N phases, wherein the at least three partial phase error signals include M=N partial phase error signals, wherein N and M are integers greater than 2.

13. The device according to claim 11, characterized in that The plurality of reference signal phases comprises M phases, the plurality of local oscillator signal phases comprises N phases, and wherein the at least three partial phase error signals comprises M x N partial phase error signals.

14. The device according to claim 11, characterized in that The partial phase comparator comprises a weighted XOR gate for further applying a weighting factor to each of the at least three partial phase error signals.

15. The device according to claim 14, characterized in that The at least three partial phase error signals have different weighting factors.

16. The device according to claim 11, characterized in that The local oscillator further includes a phase interpolator.

17. The device according to claim 11, characterized in that Further included is a low pass filter for low pass filtering the composite phase error signal.

18. The device according to claim 11, characterized in that The multiple reference signal phases are obtained through a reference clock signal transmitted via a sub-channel of a vector signaling code.

19. The device according to claim 11, characterized in that The plurality of reference signal phases are obtained by data transitions in a data stream generated by a plurality of multi-input comparators.

20. The device according to claim 19, characterized in that The plurality of multi-input comparators are used to detect data streams carried by each sub-channel of a plurality of mutually orthogonal sub-channels.

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