Low-noise column-parallel single-slope micro-light image sensor analog-to-digital converter

Abstract

The present invention relates to the field of CMOS integrated circuits. In order to shorten the quantization time of the CMS technology without increasing the noise under low illumination and without adding additional circuit modules and timing complexity, the present invention, a low-noise column-parallel single-slope low-light-level image sensor analog-to-digital converter, includes a comparator, a counter, a ramp generator, and an input voltage judgment module. The ramp generator controls switches through signals to respectively input positive / negative ramps into the comparator. The comparator generates a signal Comp_out. The input voltage judgment module determines whether the input voltage V pixel is at a lower level, controls the shape of the signal Comp_out through the Mode control signal Choose_ramp, so as to select whether the input to the comparator is a positive / negative ramp. At the same time, the signal Mode also controls the counter to change the counting method of the counter. The present invention is mainly applied to the occasions of CMOS integrated circuit design and manufacturing.

Description

Technical Field

[0001] The present invention relates to the field of CMOS integrated circuits, especially the field of low-noise analog-to-digital converters in image sensors. Specifically, it relates to a low-noise column-parallel single-slope low-light-level image sensor analog-to-digital converter. Background Art

[0002] As an important part of a complementary metal oxide semiconductor (CMOS) image sensor, the performance of an analog-to-digital converter (ADC) often directly determines the imaging quality of the image sensor. Currently, there are mainly three integration methods for ADCs, namely chip-level ADCs, column-parallel ADCs, and pixel-level ADCs.

[0003] For a single-slope ADC (SS ADC) to be applied in a low-noise scenario, correlated multiple sampling (CMS) technology is generally used to reduce noise. The more sampling times, the stronger the noise suppression ability, which can improve the imaging quality, but it will also linearly increase the conversion time. Thus, there is also an inevitable contradiction between the conversion time and the noise. Reducing the ADC conversion time while ensuring the noise performance of the single-slope ADC has become an increasingly important issue.

[0004] In summary, using CMS technology can reduce the readout noise, but it will also linearly increase the conversion time. Regarding this problem, existing technologies have certain limitations. The two-step SS ADC needs to temporarily store the voltage of the ramp generator in the analog domain or digital domain, requiring additional circuits; sufficient redundancy needs to be designed to avoid mislocking, increasing the design complexity. The conditional CMS technology needs to add redundant ramp generators, facing the problem of matching between ramp generators, and will also increase the power consumption of the SSADC to a certain extent. Therefore, it is very necessary to improve the speed of CMS without increasing the circuit scale and timing complexity.

[0005] The overall architecture diagram of the SS ADC is as Figure 1 shown. The SS ADC consists of a comparator, a counter, and a ramp generator. The comparator is used to compare the input voltage with the ramp voltage and measure the duration before the comparator switches, converting the input voltage into a digital code. The working process of the traditional CMS technology is as Figure 2As shown in the figure, the quantization process of the ADC is divided into a reset signal stage and a sampling signal stage. In these two stages, the reset signal and the exposure signal from the pixel or PGA are quantized respectively. In the CMS technology, the reset signal and the exposure signal output by the pixel are sampled multiple times and averaged to suppress the random noise in the CMOS image sensor. And the offset caused by factors such as fixed pattern noise, KT / C noise in the pixel, response delay of the comparator in the ADC, and clock delay of the counter is eliminated by subtracting the counting results of these two stages. Shot noise depends on the number of photoelectrons in the signal. Only under strong light is shot noise the key factor limiting the signal-to-noise ratio. Therefore, for a larger input signal, increasing the sampling times will not have an obvious effect on noise suppression, and traditional CMS technology will waste a certain amount of time. Summary of the Invention

[0006] To overcome the deficiencies of the prior art and aiming at the disadvantage of slow quantization speed of traditional CMS technology, the present invention aims to propose an SS ADC that adjusts the input ramp range and sampling times according to the light intensity. The positive / negative ramp is selected according to the magnitude of the input light intensity to change the number of CMS. While not increasing the noise under low illumination, the quantization time of the CMS technology can be shortened without adding additional circuit modules and timing complexity. For this purpose, the technical solution adopted by the present invention is a low-noise column-parallel single-slope low-light-level image sensor analog-to-digital converter, including a comparator, a counter, a ramp generator, and an input voltage judgment module. The ramp generator generates positive and negative two-phase outputs V ramp+ 、V ramp- , and through the signal Choose_ramp and its inverted signal to control the switch, the positive / negative ramp is respectively input into the comparator. The comparator compares the ramp signal with the pixel output signal V pixel to generate a signal Comp_out. The input voltage judgment module determines whether the input voltage V pixel is at a lower level to generate a signal Mode. The shape of the signal Choose_ramp is controlled by Mode, so as to select the positive / negative ramp input into the comparator. At the same time, the signal Mode also controls the counter to change the counting method of the counter.

[0007] The quantization process is divided into a reset signal stage, a ramp selection stage, and a sampling signal stage. Among them, the reset signal stage is used to quantize the reset signal from the pixel; the ramp selection stage is used to judge the magnitude of the input light intensity to determine the ramp input method and sampling times; the sampling signal stage is used to quantize the exposure signal of the pixel.

[0008] In the ramp selection stage, the ramp voltage is set near V top / 2, V top is the highest voltage of the ramp, with a magnitude of V ref , when Vpixel >V ref When, it can be determined that the ADC input voltage is small and the sensor is at a low illuminance; when V pixel <V ref When, it can be determined that the ADC input voltage is large and the sensor is at a high illuminance. Among them, the signal Mode is used to reflect whether the input voltage is at a high level and the number of SS ADC samplings; the signal Choose_ramp is used to select the positive / negative ramp. When it is at a high level, the positive ramp is selected, and when it is at a low level, the negative ramp is selected;

[0009] V pixel <V ref When, the number of samplings is 2. During the ramp selection stage, the comparator does not flip. The signal Mode is always at a low level, and the signal Choose_ramp is always at a high level, which means that the ramp signal input to the comparator is always the positive ramp V ramp+ , through the pre-judgment in the ramp selection stage, a CMS operation with M = 2 will be performed in the sampling signal stage. However, during the reset signal stage, the counter has sampled the reset signal four times, and only the results of the first two samplings are required. The processing method for this situation is as follows: when the second quantization in the reset signal stage is completed, the result of the counter at this time is latched through the signal Latch. After determining that the number of samplings is 2 in the ramp selection stage, the latched count result is returned to each counter through the signal Return, so that the counter returns to the state after the end of the second sampling in the reset signal stage. Therefore, the count result of the counter will become the result of sampling the signal twice in the reset signal stage;

[0010] V pixel >V ref When, the number of samplings is 4. During the ramp selection stage, the comparator flips upward, and this rising edge triggers the signal Mode to become high level. The signal Choose_ramp is generated by the signal Mode. The ramp in the sampling signal stage is the differential ramp V ramp+ and V ramp- constituted. The positive and negative ramps are selected through the signal Choose_ramp: when Choose_ramp is at a high level, the positive ramp V ramp+ is input, and when Choose_ramp is at a low level, the negative ramp V ramp- is selected, and finally the signal V ramp is input to the comparator. At this time, the number of samplings is 4, so all the count results in the reset signal stage are valid, the high level of the signal Return does not occur, and the signal latched by the signal Latch for the first time does not work;

[0011] For the voltage V ref , it is set slightly lower than V topLevel of / 2, V top is the highest voltage of the ramp. At the end of the quantization period, the results of multiple samplings are averaged. When the signal Mode is high, the counted value is the result of 4 samplings; when the signal Mode is low, the counted value is the result of 2 samplings. The counted value is divided by the number of samplings respectively to obtain the final quantization result.

[0012] The specific structure of the counter is that each counter is composed of a bit-width inverter (BWI) module, a D flip-flop, and a latch. The BWI module is used to take the opposite of the counting result after the end of the reset signal stage. At the beginning of the ADC conversion cycle, the output of the BWI module is controlled to change from "0" to "1", generating a rising edge at the input of the D flip-flop of each counter, making the counter start counting from -1. When the counter is counting, the BWI module acts as an inverter. After the reset signal stage, the BWI module outputs signals "0" and "1" again respectively, and the generated rising edge is transmitted to the corresponding D flip-flop, taking the opposite of the counting result of each counter, achieving the effect of taking the opposite of the counting result.

[0013] A latch needs to be connected behind each counter. At the end of the conversion cycle, the latch is controlled by the signal Latch to latch the results of the 11-bit counter for convenient reading of the subsequent counting results. In addition, the latch also plays a role of temporary storage. After the second sampling in the reset signal stage, the signal Latch generates a high level for a period of time to control the latch to latch the counting results of each counter. When the signal Return is high, the latched results Q and Q' are sent to the set and reset ports of the counter respectively. When the latched result is "1", the counter of this bit is set, and the counter output result is "1"; when the latched result is "0", the counter of this bit is reset, and the counter output result is "0". Through this operation, the pre-latched result is sent to the counter, which works for the case where the number of samplings is 2.

[0014] The features and beneficial effects of the present invention are:

[0015] The present invention uses a current-steering digital-to-analog converter (DAC) as a ramp generator, and makes full use of its output differential characteristics. According to the magnitude of the input light intensity, a positive / negative ramp is selected to change the number of CMS. It can achieve the effect of four samplings only in the time required for two samplings by the traditional CMS technology. While not increasing the noise under low illumination, it can shorten the quantization time of the traditional CMS technology without adding additional circuit modules and timing complexity. Description of the Drawings

[0016] Figure 1 Overall architecture diagram of traditional single-slope ADC.

[0017] Figure 2 Timing diagram of traditional CMS technology.

[0018] Figure 3 SS ADC architecture adopting voltage-adaptive CMS technology.

[0019] Figure 4 Voltage-adaptive CMS technology V pixel <V ref case.

[0020] Figure 5 Voltage-adaptive CMS technology V pixel >V ref case.

[0021] Figure 6 Comparator architecture.

[0022] Figure 7 Counter architecture. Specific implementation manner

[0023] A low-noise single-slope ADC adopting CMS technology and its working mode applied to the field of image sensors according to the present invention, and its connection manner is as Figure 3 shown, and it is composed of a comparator, a counter, a ramp generator and an input voltage judgment module. The ramp generator generates positive and negative two-phase outputs V ramp+ , V ramp- , and controls the switch through the signal Choose_ramp and its inverted signal, respectively, so that the positive / negative ramp is input into the comparator. The comparator compares the ramp signal and the pixel output signal V pixel , and generates the signal Comp_out. The input voltage judgment module judges the signal Comp_out to determine whether the input voltage V pixel is at a lower level, generates the signal Mode, controls the shape of the signal Choose_ramp through Mode, and thus selects the positive / negative ramp input into the comparator. At the same time, the signal Mode also controls the counter and changes the counting mode of the counter.

[0024] The basic principle and working timing are as Figure 4 , 5 shown: The quantization process of the SS ADC is divided into a reset signal stage, a ramp selection stage and a sampling signal stage, corresponding to stages 1, 2, and 3 in the figure respectively. Among them, the reset signal stage is used to quantize the reset signal from the pixel; the ramp selection stage is used to judge the magnitude of the input light intensity, so as to determine the ramp input mode and the number of sampling times; the sampling signal stage is used to quantize the exposure signal of the pixel.

[0025] Set the ramp voltage near V top / 2 (V top is the highest voltage of the ramp), with a magnitude of V ref , and make a judgment in stage 2. When V pixel >V ref , it can be determined that the ADC input voltage is small and the sensor is in a lower illuminance; when V pixel <V ref , it can be determined that the ADC input voltage is large and the sensor is in a higher illuminance. The working processes of these two situations are shown in Figure 4 and Figure 5 respectively. Among them, the signal Mode is used to reflect whether the input voltage is at a high level and the number of SS ADC sampling times; the signal Choose_ramp is used to select the positive / negative ramp. When it is at a high level, the positive ramp is selected, and when it is at a low level, the negative ramp is selected.

[0026] When V pixel <V ref , the working process of the SS ADC is shown in Figure 4 . The number of samplings is 2. In the ramp selection stage, the comparator does not flip, the signal Mode is always at a low level, and the signal Choose_ramp is always at a high level, which means that the ramp signal input to the comparator is always the positive ramp V ramp+ . Through the preliminary judgment in the ramp selection stage, a CMS operation with M = 2 will be performed in the sampling signal stage. However, in the reset signal stage, the counter has sampled the reset signal four times, and only the results of the first two samplings are required. The processing method for this situation is as follows: When the second quantization in the reset signal stage is completed, the result of the counter at this time is latched through the signal Latch. After determining that the number of samplings is 2 in the ramp selection stage, the latched count result is returned to each counter through the signal Return, so that the counter returns to the state after the end of the second sampling in the reset signal stage. Therefore, in stage 2, the counting result of the counter will become the result of sampling the reset signal twice in the reset signal stage.

[0027] When V pixel >V ref , the working process of the SS ADC is shown in Figure 5 . The number of samplings is 4. In the ramp selection stage, the comparator flips upward, and this rising edge triggers the signal Mode to become high level. The signal Choose_ramp is generated by the signal Mode. The ramp in the sampling signal stage is composed of the differential ramps V ramp+ and V ramp- generated by the ramp generator. The positive and negative ramps are selected through the signal Choose_ramp: when Choose_ramp is at a high level, the positive ramp Vramp+ When Choose_ramp is at a low level, the reverse ramp V is selected. ramp- The final signal V will be obtained. ramp It is input into the comparator. At this time, the number of sampling times is 4. Therefore, all the counting results in the reset signal stage are valid. The high level of the signal Return is not generated, and the signal latched for the first time by the signal Latch has no effect.

[0028] For the voltage V ref , it can be set at a level slightly lower than V top / 2, and V top is the highest voltage of the ramp. At the end of the quantization period, the results of multiple samplings are averaged. When the signal Mode is at a high level, the count value is the result of 4 samplings; when the signal Mode is at a low level, the count value is the result of 2 samplings. The count value is divided by the number of sampling times respectively to obtain the final quantization result.

[0029] The comparator amplifies the differential signal for comparing the voltage magnitudes of the positive and negative input terminals and outputs in the form of "0" or "1". To increase the gain of the comparator, a two-stage differential amplifier is selected. The comparator architecture is as Figure 6 shown.

[0030] The specific structure of the counter is as Figure 7 shown. Each counter consists of a Bit Width Inverter (BWI) module, a D flip-flop, and a latch. Among them, the BWI module is used to take the opposite of the counting result after the end of the reset signal stage. The architecture of the BWI module is as Figure 7 shown in the upper left. At the beginning of the ADC conversion cycle, the output of the BWI module is controlled to change from "0" to "1", generating a rising edge at the input of the D flip-flop of each counter, causing the counter to start counting from -1. When the counter is counting, the BWI module acts as an inverter. After the reset signal stage, the BWI module outputs the signals "0" and "1" again respectively, and the generated rising edge is passed into the corresponding D flip-flop, taking the opposite of the counting result of each counter, achieving the effect of taking the opposite of the counting result.

[0031] A latch needs to be connected behind each counter. At the end of the conversion cycle, it is controlled by the signal Latch Figure 7The latch in it latches the result of the 11-bit counter to facilitate the reading of the subsequent counting result. In addition, the latch also plays a role of temporary storage in this design. After the second sampling is completed in the reset signal stage, the signal Latch generates a high level for a period of time to control the latch and latch the counting result of each bit of the counter. When the signal Return is high, the latched results Q and Q' are respectively sent to the set and reset ports of the counter. When the latched result is "1", the corresponding bit of the counter is set and the counter output result is "1"; when the latched result is "0", the corresponding bit of the counter is reset and the counter output result is "0". Through this operation, the pre-latched result is sent to the counter, which works for the case where the number of samplings is 2.

[0032] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A low-noise column-parallel single-slope micro-light image sensor analog-to-digital converter, characterized in that, It includes a comparator, a counter, a ramp generator and an input voltage judgment module. The ramp generator generates positive and negative two-phase outputs V ramp+ , V ramp- . By using the signal Choose_ramp and its inverted signal to control the switch, the positive / negative ramp is respectively input into the comparator. The comparator compares the ramp signal with the pixel output signal V pixel to generate the signal Comp_out. Through the judgment of the signal Comp_out by the input voltage judgment module, it is determined whether the input voltage V pixel is at a lower level, and the signal Mode is generated. The shape of the signal Choose_ramp is controlled by Mode, so as to select the positive / negative ramp input into the comparator. At the same time, the signal Mode also controls the counter to change the counting method of the counter. Among them: Set the ramp voltage to V during the ramp selection phase top / 2, V top is the highest voltage of the ramp, with a magnitude of V ref , when V pixel >V ref When, it can be determined that the ADC input voltage is small and the sensor is in a lower illuminance; when V pixel <V ref When, it can be determined that the ADC input voltage is large and the sensor is in a higher illuminance. Among them, the signal Mode is used to reflect whether the input voltage is at a high level and the number of SS ADC samplings; the signal Choose_ramp is used to select the positive / negative ramp. When it is at a high level, the positive ramp is selected, and when it is at a low level, the negative ramp is selected; V pixel <V ref When pixel , the number of sampling times is 2. During the ramp selection phase, the comparator does not flip, the signal Mode is always at a low level, and the signal Choose_ramp is always at a high level, which means that the ramp signal input to the comparator is always a positive ramp. V ramp+ , through the preliminary judgment in the ramp selection stage, CMS operation with M = 2 will be performed in the sampling signal stage. However, in the reset signal stage, the counter has sampled the reset signal four times, and only the results of the first two samplings are required. The processing method for this situation is as follows: when the second quantization in the reset signal stage is completed, the result of the counter at this time is latched through the signal Latch. After determining that the number of samplings is 2 in the ramp selection stage, the latched counting result is returned to each counter through the signal Return, so that the counter returns to the state after the end of the second sampling in the reset signal stage. Therefore, the counting result of the counter will become the result of sampling the signal twice in the reset signal stage; V pixel >V ref When it is V, the number of sampling times is 4. During the ramp selection phase, the comparator flips upward, and this rising edge triggers the signal Mode to become high level. The signal Choose_ramp is generated under the control of the signal Mode. The ramp in the sampling signal phase is a differential ramp V ramp+ and V ramp- constituted. The positive and negative ramps are selected through the signal Choose_ramp: when Choose_ramp is at high level, the input is the positive ramp V ramp+ , when Choose_ramp is at low level, the reverse ramp V ramp- is selected, and the final signal V ramp is input to the comparator. At this time, the number of sampling times is 4, so all the counting results in the reset signal phase are valid. The high level of the signal Return is not generated, and the signal latched for the first time by the signal Latch has no effect; For voltage V ref , set it at a level lower than V top / 2, where V top is the highest voltage of the ramp. At the end of the quantization period, the results of multiple samplings are averaged. When the signal Mode is high, the counted value is the result of 4 samplings; when the signal Mode is low, the counted value is the result of 2 samplings. Divide the counted value by the number of samplings respectively to obtain the final quantization result.

2. The low-noise column-parallel single-slope type low-light-level image sensor analog-to-digital converter according to claim 1, characterized in that, The quantization process is divided into a reset signal stage, a ramp selection stage, and a sampling signal stage. The reset signal stage is used to quantize the reset signal from the pixel; the ramp selection stage is used to determine the magnitude of the input light intensity, so as to determine the ramp input mode and the number of samplings; the sampling signal stage is used to quantize the exposure signal of the pixel.

3. The low-noise column-parallel single-slope micro-light image sensor analog-to-digital converter according to claim 1, characterized in that the counter The specific structure is that each counter consists of a bit-width inverter (BWI) module, a D flip-flop, and a latch. The BWI module is used to take the opposite of the counting result after the reset signal stage ends. At the beginning of the ADC conversion cycle, it controls the output of the BWI module to change from "0" to "1", generating a rising edge at the input of the D flip-flop of each counter, causing the counter to start counting from -1. When the counter is counting, the BWI module acts as an inverter. After the reset signal stage, the BWI module outputs signals "0" and "1" again respectively, and the generated rising edge is passed into the D flip-flop of the corresponding bit, taking the opposite of the counting result of each counter, achieving the effect of taking the opposite of the counting result. A latch needs to be connected behind each counter. At the end of the conversion cycle, the latch is controlled by the signal Latch to latch the result of the 11-bit counter for convenient reading of the subsequent counting result; in addition, the latch also plays a role of temporary storage. After the second sampling in the reset signal stage, the signal Latch generates a high level for a period of time to control the latch, latching the counting result of each counter. When the signal Return is high, the latched results Q and Q' are sent to the set and reset ports of the counter respectively. When the latched result is "1", the counter of this bit is set, and the counter output result is "1"; when the latched result is "0", the counter of this bit is reset, and the counter output result is "0". Through this operation, the previously latched result is sent to the counter, which is effective for the case where the number of samplings is 2.

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