Mitigating reliability issues in low voltage reference buffers driven by high voltage circuits

Abstract

Certain aspects of the present disclosure provide a circuit that connects an output of a voltage reference circuit powered by a relatively high voltage to an input of a voltage buffer that is configured to generate a voltage lower than the high voltage. The connection circuit prevents the high voltage from reaching the input of the voltage buffer. An example electronic circuit generally includes: a voltage reference circuit configured to be powered by a relatively high voltage, a buffer circuit configured to generate a relatively low voltage compared to the relatively high voltage, and a circuit coupled between the output of the voltage reference circuit and the input of the buffer circuit, the circuit configured to prevent the higher voltage from reaching the input of the buffer circuit.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. Non-Provisional Application No. 16 / 773,645, filed on January 27, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly, to techniques and apparatus for mitigating reliability issues in driving low voltage buffer circuits with high voltage reference circuits. Background Art

[0004] A loudspeaker is a transducer that generates pressure waves and thus sound in response to an input electrical signal. The loudspeaker input signal may be generated by an audio amplifier that receives a relatively low voltage analog audio signal and generates an amplified signal (with a relatively higher voltage) to drive the loudspeaker. A dynamic loudspeaker typically consists of a lightweight diaphragm (cone) connected to a rigid basket (frame) via a flexible suspension (often called a strut) that constrains a voice coil to move axially through a cylindrical magnetic gap. When an input electrical signal is applied to the voice coil, the current in the coil generates a magnetic field, forming a linear electric motor. By varying the electrical signal from the audio amplifier, the mechanical force generated by the interaction between the magnet and the voice coil is modulated and causes the cone to move back and forth, generating pressure waves that are interpreted as sound.

[0005] An electronic device implemented with a speaker may include circuits for sensing various characteristics of an analog signal driving the speaker. An analog-to-digital converter (ADC) may be used to convert such an analog signal into a digital signal, typically for performing signal processing in the digital domain. Several types of ADCs are available, each with different advantages and disadvantages. For example, a successive approximation register (SAR) ADC may provide an area and power efficient architecture for low to medium precision analog-to-digital conversion applications. A SAR ADC may use a digital-to-analog converter (DAC) and a comparator to approximate a digital value corresponding to an analog input. Another ADC known as a flash ADC may provide faster conversion speeds, but at the expense of exponentially increased power consumption and area consumption. The ADC may be implemented using a reference voltage that is compared to the input analog signal. In some cases, the ADC may include a reference buffer circuit for buffering the reference voltage. Summary of the invention

[0006] Certain aspects of the present disclosure are generally directed to mitigating reliability issues in buffer circuits that utilize relatively higher voltage reference circuits to drive relatively lower voltages.

[0007] Certain aspects of the present disclosure provide an electronic circuit. The electronic circuit generally includes: a voltage reference circuit configured to be powered by a relatively high voltage, a buffer circuit configured to generate a relatively low voltage compared to the relatively high voltage, and a circuit coupled between an output of the voltage reference circuit and an input of the buffer circuit, the circuit being configured to prevent the high voltage from reaching the input of the buffer circuit.

[0008] Certain aspects of the present disclosure provide a method for driving a buffer circuit. The method generally includes: powering a voltage reference circuit from a relatively high voltage; generating a relatively low voltage compared to the relatively high voltage using the buffer circuit, the low voltage being based on a voltage reference value output from the voltage reference circuit; and preventing the high voltage from reaching an input of the buffer circuit.

[0009] Certain aspects of the present disclosure provide an electronic circuit. The electronic circuit generally includes: a voltage reference circuit configured to be powered by a relatively high voltage, a buffer circuit configured to generate a relatively low voltage compared to the relatively high voltage, a first switch coupled between an output of the voltage reference circuit and an input of the buffer circuit; and a second switch coupled between the input of the buffer circuit and a reference potential node of the electronic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order that the manner in which the above-mentioned features of the present disclosure may be understood in detail, a more particular description briefly summarized above may be obtained by reference to the various aspects, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered limiting of its scope, as the description may admit of other equally effective aspects.

[0011] Figure 1 An example audio amplifier system in accordance with certain aspects of the present disclosure is illustrated.

[0012] Figure 2A is a block diagram of an example electronic circuit including a voltage reference circuit and a buffer circuit, wherein a protection circuit is coupled between the voltage reference circuit and the buffer circuit, according to certain aspects of the present disclosure.

[0013] Figure 2B is an illustration of operation during a calibration mode according to certain aspects of the present disclosure. Figure 2A Example timing diagram for the example circuit.

[0014] Figure 2C is an illustration of operation during a trimming mode according to certain aspects of the present disclosure. Figure 2A Example timing diagram for the example circuit.

[0015] Figure 2DAccording to certain aspects of the present disclosure, there is an Figure 2A A block diagram of an example electronic circuit for a switch of a protection circuit.

[0016] Figure 3 is a flow chart of example operations for driving a buffer circuit according to certain aspects of the present disclosure.

[0017] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0018] Certain aspects of the present disclosure provide a circuit that connects the output of a voltage reference circuit powered by a relatively high voltage to the input of a voltage buffer that is configured to generate a voltage lower than the high voltage. The connection circuit prevents the high voltage from reaching the input of the voltage buffer.

[0019] Various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided to make the present disclosure thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether it is implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or implementation method. In addition, the scope of the present disclosure is intended to cover such a device or method: it uses other structures, functions, or structures and functions other than or in addition to the various aspects of the present disclosure set forth herein to practice. It should be understood that any aspect of the disclosure disclosed herein can be embodied by one or more elements of the claims.

[0020] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B, or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected with" may also be used herein to mean that element A and element B (as well as any components electrically connected between element A and element B) are electrically connected using wires, traces, or other conductive materials.

[0022] Example Audio Application with Speaker Protection

[0023] Figure 1 An example audio amplifier system 100 is illustrated in accordance with certain aspects of the present disclosure. As illustrated, a digital signal processor (DSP) 102 may receive and process an audio signal 114 (e.g., a digital audio signal) by, for example, applying a digital filter intended to improve audio quality. A digital-to-analog converter (DAC) 108 may be used to convert the filtered digital signal 118 (or a further processed version thereof) produced by the DSP 102 into an analog signal 120. In certain aspects, the DAC may be implemented as part of the DSP 102 or the amplifier 110. In certain aspects, the amplifier 110 may be used to amplify the analog signal 120 to generate an amplified signal 122. The amplified signal 122 may drive a speaker 112 to produce an acoustic output 124 (e.g., a sound wave).

[0024] High output volume in mobile devices is becoming increasingly important in next generation mobile devices. Higher volume directly translates into higher output power. Higher volume may be difficult to achieve using the relatively low voltage provided by lithium-ion batteries. Therefore, an on-chip boost switcher can be used to boost the battery voltage to a higher level, which powers a speaker power amplifier (e.g., amplifier 110). Due to the high power efficiency associated with class D amplifiers, amplifier 110 can be implemented as a class D amplifier. The efficiency of the class D amplifier can be further improved by implementing the class D amplifier in an H-bridge configuration.

[0025] In some aspects, a current-voltage (IV)-sensing path can be used to sense speaker current and voltage and provide an estimate of speaker resistance, which in turn can be used to predict the temperature of the speaker coil. For example, the current sensing circuit 140 can be used to sense the drive current of the speaker 112 and provide a digital representation of the current to the DSP 102. The current sensing circuit 140 can include a voltage reference circuit that drives a reference buffer circuit for an analog-to-digital converter (ADC), the ADC being configured to convert the sensed analog current signal into a digital signal representing the sensed current. For example, the ADC can be implemented as a successive approximation register (SAR) ADC. The voltage reference circuit and the reference buffer circuit can be implemented as described below.

[0026] Example Reference Circuit with Protection

[0027] Figure 2A is a block diagram of an example electronic circuit 200 according to certain aspects of the present disclosure. The electronic circuit 200 may be included in any of a variety of suitable systems having a reference buffer circuit driven by a voltage reference circuit, including in a current sensing circuit 140 of an audio amplifier system, as described above with respect to Figure 1 As described. Figure 2A As shown in FIG. 2 , the electronic circuit 200 includes a voltage reference circuit 202 , a protection circuit 204 , and a buffer circuit 206 .

[0028] Voltage reference circuit 202 may be a temperature compensated and calibrated reference circuit configured to generate a voltage referenced as “V REFCAL "The voltage reference circuit 202 may include a first transistor Q1, a second transistor Q2, a sensing resistor R sense and a switched capacitor current source and a current mirror in circuit block 210. The first transistor Q1 and the second transistor Q2 may be implemented as p-type metal oxide semiconductor (PMOS) transistors. The source of the first transistor Q1 may be coupled to a relatively high voltage rail (labeled as “Vdd_high”), the source of the second transistor Q2 may be coupled to the drain of the first transistor Q1, and the drain of the second transistor Q2 may be coupled to a sense resistor R sense The first terminal of the sense resistor can have a nominal resistance value at a given temperature (e.g., 80 kΩ at 55°C). The circuit block 210 can receive an input signal on the input node 201 and generate an output signal sent to the gates of the first and second transistors Q1 and Q2. As shown, the switched capacitor current source and current mirror in the circuit block 210 can receive power from Vdd_high, and the circuit block 210 and the sense resistor R sense The second terminal of each of the voltage reference circuits 202 may be coupled to a reference potential node (e.g., electrical ground). The voltage reference circuit 202 may further include a switch S1 coupled between Vdd_high and the gate of the first transistor Q1, wherein the switch S1 is controlled by a control signal labeled “Cal Ref ENABLE”, which may be generated by and received from a calibrated reference finite state machine 212 (labeled “Cal Ref FSM”).

[0029] During operation, the voltage reference circuit 202 may receive an input signal at the input node 201. The input signal may be a digital code (e.g., a 6-bit digital code) that may be received from a calibration loop during a calibration mode, or it may be received from a storage device (e.g., an electronic fuse) during a normal operating mode (such as after power-on or after reset). Based on the digital code, the switched capacitor current source and the current mirror in the circuit block 210 may output control signals for the gates of the first and second transistors Q1, Q2 for modulating the reference current I ref . Flows through the sensing resistor R sense The reference current I ref Generate reference voltage V REFCAL For example, V REFCALIt can have a nominal value of approximately 1.25V at 55°C and can track the sense resistor R sense When the switch S1 is open (Cal Ref ENABLE is deactivated), the voltage reference circuit 202 is enabled, and when the switch S1 is closed (Cal Ref ENABLE is activated), the voltage reference circuit 202 is disabled.

[0030] The buffer circuit 206 may include a first amplifier 205 and a second amplifier 207. The first and second amplifiers 205, 207 may both receive power from a relatively low voltage rail (labeled as "Vdd_low"). The output of the first amplifier 205 may be fed back to the negative terminal of the first amplifier so that the first amplifier is configured as a voltage buffer. The output of the first amplifier 205 may be coupled to a first amplifier 207, a feedback resistor R f and resistor R 1 , R 2 and R 3 The amplifier circuit may have (R 3 / (R 2 +R 3 ))((R f +R 1 ) / R 1 ) to generate a buffered differential signal pair, VREFP / VREFN.

[0031] As described above, the voltage reference circuit 202 can receive power from a relatively high voltage rail (labeled as “Vdd_high”) (e.g., to provide sufficient headroom for the first and second transistors Q1, Q2), while the buffer circuit 206 can receive power from a relatively low voltage rail (labeled as “Vdd_low”). For example, Vdd_high can be around 3.0V, and Vdd_low can be around 1.8V. During the calibration mode, for example, the output (Vdd_high) of the voltage reference circuit 202 REFCAL ) can cycle through the entire Vdd_high range (e.g., 0 to 3V) and sometimes exceed the Vdd_low voltage (e.g., 1.8V), causing reliability issues for the buffer circuit 206 before settling to a final value (e.g., 1.25V). In addition, during normal operating mode (also referred to as "trimming mode"), when using an external register or other storage device to set V REFCAL When Vdd_high is set to zero, the digital code input to the voltage reference circuit 202 may correspond to any value between ground and Vdd_high, which may also exceed Vdd_low.

[0032] Thus, certain aspects of the present disclosure include a protection circuit 204 between the output of the voltage reference circuit 202 and the input of the buffer circuit 206. The protection circuit 204 may include a switch S2 and a switch S3. The switch S2 may have a first terminal coupled to the output of the voltage reference circuit 202 and a second terminal coupled to the input of the buffer circuit 206. In other words, the switch S2 may be coupled in series between the voltage reference circuit 202 and the buffer circuit 206. The switch S3 may have a first terminal coupled to the input of the buffer circuit 206 and a second terminal of the switch S2. The switch S3 may also have a second terminal coupled to a reference potential node (e.g., electrical ground) for the electronic circuit 200. The operation of the switch S2 may be controlled by a control signal labeled "Short SW ENABLE", and the operation of the switch S3 may be controlled by a control signal labeled "Short to GNDENABLE". One or both of the control signals Short SW ENABLE and Short to GNDENABLE may be generated by and received from Cal Ref FSM 212. Utilizing switches S2 and S3 and control logic, protection circuit 204 prevents buffer circuit 206 from seeing a relatively high voltage (e.g., >1.8V) from voltage reference circuit 202, as described below.

[0033] For certain aspects, the protection circuit 204 may also include a clamp circuit 208 coupled between the input of the buffer circuit 206 and the reference potential node. For example, the clamp circuit 208 may include two series-connected diodes, as shown. For other aspects, the clamp circuit 208 may include more than two series-connected diodes.

[0034] Figure 2B is an illustration of operation during a calibration mode according to certain aspects of the present disclosure. Figure 2A An example timing diagram 260 of the example circuit 200 is shown. A calibration mode (eg, a SAR ADC calibration mode) may be used to determine a digital code (eg, a 6-bit digital code) for setting a desired reference voltage V REFCAL The ADC can set these calibration bits during calibration mode.

[0035] After or upon entering calibration mode, Cal RefENABLE transitions from logic low (e.g., 0V) to logic high (e.g., 3V), thereby opening switch S1 according to negative logic (active low). In addition, Short SW ENABLE is logic low and Short to GND ENABLE is logic high, such that switch S2 is open and switch S3 is closed at this time. In this way, the input of buffer circuit 206 is shorted to ground and disconnected from the output of voltage reference circuit 202 during calibration mode, so that buffer circuit 206 is not subjected to voltages exceeding Vdd_low. ADC calibration then occurs, and as a result of the calibration, reference voltage V REFCAL should stabilize to a nominal value (e.g., 1.25V). After a preset number of clock cycles, Short SW ENABLE transitions from logic low to logic high, and Short to GND ENABLE transitions from logic high to logic low, causing switch S2 to close and switch S3 to open. The preset number of clock cycles can be selected so that the reference voltage V REFCAL At the end of this period, it should have stabilized. In this way, during calibration mode, as V REFCAL The buffer circuit 206 is never exposed to the relatively high voltage. For some aspects, Short SW ENABLE can transition from logic low to logic high slightly before Short to GND ENABLE transitions from logic high to logic low (e.g., one clock cycle before). When exiting the calibration mode, Cal Ref ENABLE can return to logic low, thereby opening switch S1 and allowing the electronic circuit 200 to return to a normal operating mode, e.g., returning V set by the calibration mode to 0. REFCAL Applied to the buffer circuit 206 .

[0036] Figure 2C is an illustration of operation during a fine tuning mode according to certain aspects of the present disclosure. Figure 2A The trimming mode may occur after powering up a device having the electronic circuit 200 or after a reset of the device or circuit 200. During the trimming mode, a pre-stored bit (eg, from an electronic fuse) may be input to the voltage reference circuit 202.

[0037] After or upon entering the trim mode, Cal Ref ENABLE transitions from a logic low (e.g., 0V) to a logic high (e.g., 3V), thereby opening switch S1 according to negative logic. In addition, Short SW ENABLE is logic low and Short to GND ENABLE is logic high, such that switch S2 is open and switch S3 is closed at this time. In this way, the input of buffer circuit 206 is shorted to ground and disconnected from the output of voltage reference circuit 202 during trim mode, so that the buffer circuit is not subjected to voltages exceeding Vdd_low. Circuit block 210 then controls transistors Q1 and Q2 to set the reference voltage V based on the received digital code. REFCAL , the reference voltage should stabilize to the selected value. After a predetermined stabilization time (which can be set by a preset number of clock cycles), Short SW ENABLE transitions from logic low to logic high, and Short to GND ENABLE transitions from logic high to logic low, causing switch S2 to close and switch S3 to open. The predetermined stabilization time (e.g., 100 μs) can be selected so that the reference voltage V REFCAL At the end of this time, the V REFCAL In this way, during the fine-tuning mode, as V REFCAL To stabilize to the selected value, the buffer circuit 206 is never exposed to the relatively high voltage. For some aspects, Short SW ENABLE can transition from logic low to logic high slightly before Short to GNDENABLE transitions from logic high to logic low (e.g., one clock cycle earlier). For example, when exiting the trim mode, Cal Ref ENABLE can return to logic low, thereby opening the switch S1 and allowing the electronic circuit 200 to return to the normal operating mode.

[0038] For some aspects, the clamp circuit 208 can be selectively disconnected from the input of the buffer circuit 206 during certain modes. In this case, Figure 2D As shown in , a switch S4 may be added between the clamp circuit 208 and the input of the buffer circuit 206. For example, the switch S4 may be opened or closed during the calibration mode, but should be closed during the trimming mode.

[0039] Example Operation for Voltage Reference Generation

[0040] Figure 3 is a flow chart of example operations 300 for driving a buffer circuit when generating a voltage reference in accordance with certain aspects of the present disclosure. Operations 300 may be performed by, for example, Figure 2A or Figure 2D The present invention is performed by an electronic circuit such as the electronic circuit 200.

[0041] Operations 300 may begin at block 302, where an electronic circuit powers a voltage reference circuit (e.g., voltage reference circuit 202) from a relatively high voltage (e.g., Vdd_high). At block 304, a buffer circuit (e.g., buffer circuit 206) may generate a relatively low voltage compared to the relatively high voltage. The low voltage may be based on a voltage reference value (e.g., Vdd_high) output from the voltage reference circuit. REFCAL ). At block 306, the electronic circuit may prevent the higher voltage from reaching the input of the buffer circuit.

[0042] According to certain aspects, preventing at block 306 may involve: opening a first switch (e.g., switch S1) coupled between the output of the voltage reference circuit and the input of the buffer circuit; closing a second switch (e.g., switch S2) coupled between the input of the buffer circuit and a reference potential node (e.g., electrical ground); adjusting a voltage reference value output from the voltage reference circuit; after the adjustment, closing the first switch; and after the adjustment, opening the second switch.

[0043] According to certain aspects, the first switch is opened during the calibration mode and the second switch is closed during the calibration mode. For certain aspects, the first switch is closed a predetermined number of clock cycles from the time when the calibration mode is enabled. In this case, the second switch may be opened within one clock cycle at or after the predetermined number of clock cycles from the time when the calibration mode is enabled.

[0044] According to certain aspects, the first switch is open during the trim mode and the second switch is closed during the trim mode. For certain aspects, the first switch is closed a predetermined number of clock cycles from the time when the trim mode is enabled. In this case, the second switch is open within one clock cycle at or after the predetermined number of clock cycles from the time when the trim mode is enabled.

[0045] According to certain aspects, operations 300 also entail selectively clamping a voltage at an input of the buffer circuit.

[0046] According to certain aspects, a voltage reference circuit includes a temperature compensated and calibrated voltage reference circuit.

[0047] The various operations of the above method can be performed by any suitable component capable of performing the corresponding function. The component may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. Generally, in the case of operations illustrated in the accompanying drawings, those operations may have corresponding corresponding parts-plus-function components with similar numbers.

[0048] As used herein, the term "determine" encompasses a variety of actions. For example, "determine" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, database, or other data structure), ascertaining, and the like. Furthermore, "determine" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Furthermore, "determine" may include resolving, selecting, choosing, establishing, and the like.

[0049] As used herein, a phrase referring to “at least one” of a list item refers to any combination of those items, including single members. As an example, “at least one of a, b, or c” is intended to encompass: a; b; c; a and b; a and c; b and c, and a and b and c, as well as any combination with multiple of the same elements (e.g., a and a; a and a and a; a and a and b; a and a and c; a and b and b; a and c and c; b and b; b and b and b; b and b and c; c and c and c and c or any other ordering of a, b, and c).

[0050] The method disclosed herein includes one or more steps or actions for implementing the described method. Without departing from the scope of the claims, the method steps and / or actions can be interchangeable with each other. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions can be modified without departing from the scope of the claims.

[0051] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An electronic circuit comprising: a voltage reference circuit configured to be powered by a first voltage and to generate a reference voltage at an output of the voltage reference circuit; a buffer circuit configured to be powered by a second voltage and to generate a buffer signal, wherein the second voltage is lower than the first voltage; as well as a protection circuit coupled between the output of the voltage reference circuit and the input of the buffer circuit, wherein the protection circuit includes a first switch coupled between the output of the voltage reference circuit and the input of the buffer circuit, the protection circuit being configured to, during at least one of a trimming mode or a calibration mode, open the first switch to prevent the reference voltage higher than the second voltage from reaching the input of the buffer circuit. 2 . The electronic circuit of claim 1 , wherein the protection circuit further comprises a second switch coupled between the input of the buffer circuit and a reference potential node.

3. The electronic circuit of claim 2, further comprising a clamp circuit coupled between the input of the buffer circuit and the reference potential node. 4 . The electronic circuit of claim 3 , further comprising a third switch coupled between the clamp circuit and the input of the buffer circuit. 5 . The electronic circuit of claim 4 , wherein the third switch is configured to be closed during the trimming mode for the voltage reference circuit. 6 . The electronic circuit of claim 2 , wherein the first switch is configured to be open during the calibration mode and is configured to be closed a predetermined number of clock cycles from a time when the calibration mode is enabled.

7. The electronic circuit of claim 6 , wherein the second switch is configured to be closed during the calibration mode, and is configured to be opened at the predetermined number of clock cycles from the time when the calibration mode is enabled, or to be opened within one clock cycle after the predetermined number of clock cycles from the time when the calibration mode is enabled.

8. The electronic circuit of claim 2, wherein the first switch is initially configured to be open during a normal operation mode after power-up or reset of the electronic circuit, and is configured to be closed for a predetermined number of clock cycles starting from the power-up or the reset.

9. The electronic circuit of claim 8, wherein the second switch is initially configured to be closed during the normal operation mode after the power-on or the reset, and is configured to be opened at the start of the power-on or the reset, or to be opened within one clock cycle after the start of the power-on or the reset.

10. The electronic circuit of claim 1, further comprising a clamp circuit coupled between the input of the buffer circuit and a reference potential node.

11. The electronic circuit of claim 1 , wherein the buffer circuit comprises a voltage reference buffer for an analog-to-digital converter.

12. The electronic circuit of claim 1, wherein the voltage reference circuit is a temperature compensated and calibrated voltage reference circuit.

13. A method for driving a buffer circuit, comprising: powering a voltage reference circuit from a first voltage; generating a reference voltage at an output of the voltage reference circuit; powering the buffer circuit from a second voltage, wherein the second voltage is lower than the first voltage; generating a buffered signal based on the reference voltage output from the voltage reference circuit using the buffer circuit; as well as During at least one of a trim mode or a calibration mode, a first switch coupled between the output of the voltage reference circuit and an input of the buffer circuit is opened to prevent the reference voltage higher than the second voltage from reaching the input of the buffer circuit.

14. The method of claim 13 , wherein preventing the reference voltage higher than the second voltage from reaching the input of the buffer circuit comprises: disconnecting the first switch coupled between the output of the voltage reference circuit and the input of the buffer circuit; closing a second switch coupled between the input of the buffer circuit and a reference potential node; adjusting the reference voltage output from the voltage reference circuit so that the reference voltage is stabilized to a reference value; After the adjusting, closing the first switch; as well as After the adjusting, the second switch is opened.

15. The method according to claim 14, wherein: said first switch being open during said calibration mode; said second switch being closed during said calibration mode; the first switch being closed a predetermined number of clock cycles from a time when the calibration mode is enabled; as well as The second switch is opened at the predetermined number of clock cycles from the time when the calibration mode is enabled, or is opened within one clock cycle after the predetermined number of clock cycles from the time when the calibration mode is enabled.

16. The method of claim 14, wherein: The first switch is open during the fine-tuning mode; the second switch is closed during the fine tuning mode; the first switch being closed a predetermined number of clock cycles from a time when the trim mode is enabled; as well as The second switch is opened at the predetermined number of clock cycles from the time when the fine adjustment mode is enabled, or is opened within one clock cycle after the predetermined number of clock cycles from the time when the fine adjustment mode is enabled.

17. The method of claim 13, further comprising selectively clamping a voltage at the input of the buffer circuit.

18. An electronic circuit comprising: a voltage reference circuit configured to be powered by a first voltage and to generate a reference voltage at an output of the voltage reference circuit; a buffer circuit configured to be powered by a second voltage and to generate a buffer signal, wherein the second voltage is lower than the first voltage; a first switch coupled between an output of the voltage reference circuit and an input of the buffer circuit; as well as a second switch coupled between the input of the buffer circuit and a reference potential node for the electronic circuit, the second switch being controlled by a control signal, wherein the control signal is generated by a finite state machine, The first switch is configured to open the first switch during at least one of a trimming mode or a calibration mode to prevent the reference voltage higher than the second voltage from reaching the input of the buffer circuit.

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