Dynamic pixel modulation

Abstract

A system for generating a voltage and supplying the voltage to a pixel array includes a plurality of display pixels forming a pixel array, each pixel including a pixel circuit for driving the pixel and the pixel circuit including a plurality of data latches. A row formatter stores a plurality of bits representing image data for a row of pixels. A row controller writes a subset of a plurality of bits representing image data for the row of pixels into the plurality of data latches. A waveform generator generates a reference pulse represented by a set of reference bits. The number of reference bits is equal to the number of bits stored in the data latch of each pixel circuit. Each pixel circuit compares each reference bit with a corresponding bit stored in the data latch of each pixel circuit, and generates a voltage at an electrode of the pixel based on the comparison.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 957,684, filed on January 6, 2020. The entire contents of this U.S. Provisional Application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to systems for modulating the polarization and phase of light reflected from a display, such as a digital display and a microdisplay, such as a liquid crystal on silicon (LCOS) display device and a micro-LED display device. More specifically, the present disclosure relates to systems and methods for providing and operating a digital microdisplay system. Background Art

[0004] LCOS displays are generally of two types, characterized primarily by the type of circuitry underlying each display pixel, namely analog and digital. These conventional display types are described below one at a time and are also described in conjunction with prior art.

[0005] Analog pixel circuit

[0006] In analog displays, the circuit under each pixel is mainly only a storage capacitor. In operation, an analog voltage source is sequentially connected to the storage capacitor in each pixel to store analog voltages in the capacitor in each pixel. These stored voltages are connected to the pixel electrodes of the corresponding pixels. The variable voltages on these pixel electrodes determine the response of the liquid crystal (LC) directly above each of these pixels. Therefore, they ultimately determine (for amplitude displays) the amount of polarization change of the light reflected from the pixel, or (for phase displays) the amount of phase shift applied to the light reflected from the pixel. The variable voltage is an analog quantity, so the polarization or phase shift modulation generated in the LC also changes as a variable analog quantity. This makes the reproduction of grayscale images direct for such a display. As pixel size becomes smaller and smaller, the construction of analog displays becomes more and more difficult, because very small pixels mean very small pixel capacitors, and these small capacitors cannot keep accurate charges long enough for successful display operations, because leakage currents can discharge charges.

[0007] The analog pixel circuit may also include a single pixel capacitor and a transistor that can be used to connect it to an internal analog data source. In use, each pixel is connected to the internal data source long enough to charge the capacitor to the voltage on the data source. The transistor is then turned off and charging for another pixel begins. This operation must be repeated for each pixel in the display during each frame.

[0008] There are two limitations to this approach. First, once the capacitor is charged to the desired voltage, it must maintain that voltage for the rest of the frame. Such capacitors always have some leakage both through the insulation in and around the capacitor and through the charge control transistor. For large capacitors with a large amount of stored charge, this leakage may cause the voltage to change very slowly, and the voltage change can therefore be ignored. However, for capacitors small enough to fit under a small pixel, even a small amount of leakage will cause the voltage on the capacitor to discharge rapidly. This voltage change or discharge during a frame is called "droop" and causes voltage errors over time during the frame. These voltage errors translate directly into amplitude or phase errors. For capacitors small enough to fit in a small pixel, it is difficult to prevent this leakage-induced droop from completely discharging the pixel capacitor during a frame. Note that leakage in ICs tends to increase exponentially as the die temperature increases, making the dilemma worse. Therefore, analog circuits are not well suited for very small microdisplays.

[0009] The second limitation of this approach is that it takes time to charge each pixel capacitor to its correct value. Since this is essentially a serial process (one at a time), it takes a relatively long time to charge all the capacitors of the entire array - usually the entire frame time. This imposes many other limitations on display performance. Specifically, it prevents the use of other technologies that are otherwise required to make such a display work well, such as Vcom switching or lighting gating, because there is no suitable time point for these things to happen. To help shorten the charging time, analog designs typically use multiple analog data sources so that multiple pixels can be charged at the same time, and designs using up to 12 data sources running in parallel are often encountered. Even so, it is still challenging to write high-resolution displays with 2 million or more pixels in the frame time. The fact that the display data is written throughout the frame time creates limitations.

[0010] Digital Displays and Pixel Circuits

[0011] Digital LCOS displays are a more recent development. They contain digital memory inside each pixel which can only store a "1" or "0" state. This means that the pixel electrode can only be set to two possible voltages corresponding to the LC state as fully "on" or fully "off". On the other hand, this 1 or 0 state can be written to the pixel very quickly and will not "lose" due to leakage.

[0012] Digital LCOS displays typically achieve grayscale by writing a rapid series of 1s and 0s to each pixel, which causes the LC to alternate between these fully on and fully off states. These changes occur much faster than the eye can respond, so the eye averages the duty cycle of these "off" and "on" conditions into an equivalent grayscale. In use, digital LCOS displays typically use some variation of duty cycle modulation (DCM) or pulse width modulation (PWM) encoding to write "bit planes" of 1s and 0s multiple times during each frame to achieve the desired equivalent grayscale value. Digital pixel designs can be made very small (3μm pitch or less) and do not suffer from leakage problems. However, they often require more complex pixel circuits with more transistors. In addition, they also require very high external data rates to write a large number of bit planes per frame. In addition, averaging via human eye responses is not suitable for phase mode displays because voltage errors at the pixel correspond to position errors in the apparent position of the pixel, which the eye cannot average. Therefore, using digital LCOS displays for phase mode displays has not been very successful in the past.

[0013] Existing digital pixel displays operate as "bit plane devices". This means that for any write operation, the array control logic must write a "1" or "0" value to every pixel data latch in the entire array (the 1 or 0 for each pixel in the display is called a "bit plane"). This write bit plane (writing data to each pixel in the display) operation typically takes 100μs or more. This time limit for each bit plane constrains the algorithm used to trick the eye into thinking it is seeing grayscale by sending a series of on and off pulses of different duty cycles. Specifically, this means that the shortest voltage pulse that can exist on the pixel electrode is equal to the bit plane time. This can make high bit depth difficult because the bit plane time is actually the least significant bit (LSB) time. For example, in an 8-bit system, the most significant bit (MSB) is 127 times longer than the LSB time, and it takes 256 LSB times to display all possible grayscale values. For example, 256 times 100μm is 25.6ms, which is longer than a 60HZ frame. There is also the problem that the bit plane time of about 100 us is close to the minimum LC response time of several hundred μs.

[0014] Therefore, the speed at which the LC responds to any of these pulses depends on the pulse that occurred immediately before. This creates a nonlinear dependency on the pulse history of the pixel that is difficult to correct. Therefore, most digital pixel displays use pulse width modulation (PWM) techniques. In these techniques, there is a single pulse whose width varies from 0 (for an off pixel) to being on for the full frame time (for a fully on pixel). PWM designs are essentially monotonic, however, they require a large number of bit planes during a frame. For example, a PWM algorithm for 8-bit grayscale requires 256 bit planes per color during a frame. Moreover, most of these bit planes are sending redundant data. In other words, most of the time these bit planes write 0 to pixels that are already off, or write 1 to pixels that are already on. Supporting this is essentially a waste of power because it requires a lot of write activity during the frame. For example, a current HD display requires more than 40Gb / s of input data per color to keep it operating. It is also very important to transfer this much data from one chip to another, requiring a sophisticated wide-bandwidth data link. Such displays have difficulty providing good performance at higher bit depths.

[0015] The second problem is that PWM implemented this way cannot be used for phase modulation, because a single pulse consisting of a relatively long on period followed by a relatively long off period will cause the LC to alternate between two completely different phase values. At best, this will produce a distorted image. For phase modulation, the 1 bit planes and 0 bit planes are sent alternately so that the liquid crystal is always halfway between on and off. The duty cycle between these on and off bit planes determines the "degree of on" of the LC, and therefore the amount of phase shift. As mentioned earlier, the bit plane update time determines the shortest amount of time the LC spends at a constant voltage, and therefore the degree to which the LC state undershoots or overshoots the desired value. This constant undershoot and overshoot causes "phase ripple", which leads to undesirable image blur and lack of contrast.

[0016] Embodiments of the present disclosure improve these problems by providing a pixel array architecture and a pixel circuit that achieves the advantages of analog pixel design (effectively continuously variable pixel voltage) by using digital circuits, and is intended to avoid the shortcomings of both existing analog design and existing digital design in microdisplay applications. Such embodiments are suitable for various display applications including microdisplays. Among them, an important problem solved by the embodiments of this article is to achieve a design pixel circuit that is simple enough (with a small enough number of transistors) to be installed under each pixel in the display while still achieving the functions required for small pixel display applications. Here, "small pixel display" refers to a pixel array with a pixel pitch of 4 microns (μm) or less. Summary of the invention

[0017] According to a first embodiment of the present disclosure, there is provided a system for generating a voltage supplied to a pixel array, the pixel array being, for example, a liquid crystal display (e.g., a liquid crystal on silicon (LCOS) display or pixel array) or an LED display (e.g., a micro-LED display), the system comprising: a plurality of display pixels forming the pixel array, each display pixel comprising a pixel circuit for driving the pixel; a row formatter configured to store a plurality of bits of image data representing a row of display pixels for the pixel array (e.g., in a memory, etc.); a row controller configured to write a subset of the plurality of bits representing the image data for the pixels of the row into a plurality of data latches of the pixel circuit; a waveform generator for generating a reference pulse represented by a set of reference bits, and wherein the number of reference bits is equal to or corresponds to the number of bits stored in the latch of each pixel circuit; and wherein the pixel circuit is configured to compare each reference bit with a corresponding bit stored in the latch of each pixel circuit, and to generate a voltage at an electrode of each pixel based on the comparison.

[0018] The voltage supplied to the pixel electrode modulates the polarization, reflectivity, amplitude and / or phase of light reflected from the display pixel.

[0019] In an embodiment, the present disclosure may modulate each pixel independently and locally, and thus not use a bit plane. In a dynamic pixel modulation (hereinafter referred to as "DPM") display according to an embodiment of the present disclosure, image data may be stored directly in the display pixel (e.g., via a pixel circuit), and each display pixel may include circuitry to use the stored data value to control a voltage waveform on its pixel electrode (e.g., when the display is an LCOS display, it is a reflective device such as a mirror, and when the display is a micro-LED display, it is an LED or micro-LED (or an electrode coupled thereto), the voltage waveform being a binary weighted representation of the stored value, corresponding to a desired grayscale or phase value. This waveform at each pixel electrode may be much higher frequency than can be achieved by any bit plane display. It may be at least an order of magnitude faster than the speed at which the LC can respond, so the LC will instead react to the RMS value of the waveform. The resulting phase ripple may also be at least an order of magnitude smaller, and in some or most cases negligible.

[0020] Alternatively, the pixel data can be stored in an SRAM latch for each pixel. This is digital storage and is completely static. This means there is no droop and the data remains unchanged until it is rewritten and the resulting amplitude or phase shift does not change. Furthermore, the digital data can be written to the SRAM latch very quickly so the entire array can be written in a fraction of the frame time - typically less than 100 μm. Thus, embodiments of the present disclosure are not limited by existing analog microdisplays.

[0021] The process of writing image data to the pixel array may occur only once at the beginning of the imaging process. Thereafter, each pixel is responsible for the process of converting that image data into an appropriate pixel electrode voltage waveform.

[0022] Embodiments of the present disclosure are capable of efficiently processing data and allow for the management of amplitude and / or phase modulation of each pixel based on the loaded values. Embodiments of the present disclosure provide a system and method for handling this conversion, and such a system and method are both highly flexible and extremely efficient. This is achieved through actual circuitry under each pixel, which may include a digital logic circuit or network (e.g., and / or circuits or networks) connected to multiple digital latch circuits, such as 9 latch circuits, which implement complex logic functions with a minimum number of transistors, so that the transistors can be installed in the available die area under small pixels, such as 3μm×3μm pixels. Finally, embodiments of the present disclosure provide a fully integrated high bit depth, low phase ripple digital phase display that does not require an external driver chip.

[0023] In an embodiment, the number of bits stored in the latch of each pixel circuit can be 4 to 10 bits. It will be appreciated by those of ordinary skill in the art that the number of bits can vary. It is feasible to store 8-bit pixel data directly in the circuit at such a small pixel (<4 μm), and can be achieved by working at a geometric node (28nm or 22nm) that has not been used for LCOS microdisplays before. It will be appreciated by those of ordinary skill in the art that the number of bits stored in the latch can vary. The number of bits stored in the pixel can be sufficient to define the grayscale value for the entire color subframe.

[0024] In an embodiment, the waveform generator can be connected to each pixel via a global modulation bus (G bus). The width of the G bus can be equal to the number of bits stored in the latch of each pixel circuit. The waveform generator can be configured to periodically send out a word (e.g., 16 bits) of memory content on the G bus in sequence to generate multiple voltage pulses equal to the width of the G bus on different G bus lines.

[0025] In another embodiment, the voltage pulses on a G-bus line may be split across several G-bus lines.This flexibility is an important advantage of embodiments of the present disclosure and allows the precise behavior of the DPM modulation to be varied or adjusted almost infinitely.

[0026] The duration of each voltage pulse on the G bus line can also be programmed via a command written to the display from the software on the host or source, and the duration of the voltage pulse can be significantly shorter than the response time of the liquid crystal (LC) in the array. In one embodiment, the duration of the longest voltage pulse applied to the pixel electrode can be significantly less than the LC response time. It is understood that the software on the host or source can be provided as a computer program, which, when running on a computer, configures the computer to include any device of the circuit, controller, sensor, filter or device disclosed herein, or executes the command disclosed herein. The computer program can be a software implementation, and the computer can be considered to be any appropriate hardware, as a non-limiting example, including a digital signal processor, a microcontroller and an implementation in a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM). The software implementation can be an assembler. The computer program can be provided on a computer-readable medium, which can be a physical computer-readable medium, such as a disk or a storage device.

[0027] The relatively short duration of the voltage pulse means that all bits stored in the latch of the pixel circuit can be compared with their corresponding bits stored in the waveform generator in a period shorter than the LC response time. This comparison can be repeated multiple times during a display frame or during a subframe.

[0028] In one embodiment, when the Gset output from the waveform generator is applied to the output latch, if the corresponding bit from the logic function output is equal to "1", then the output latch is input with a bit "1", otherwise, the output latch is input with a bit "0". The start or initiation of the Gset output coincides with the start of each voltage pulse on the G bus line. The output of the output latch is input to the level shifter.

[0029] The output of the level shifter is a voltage level that has a high voltage when the output of the circuit is bit "1" and a low voltage when the output of the circuit is bit "0", wherein the voltage generated by the level shifter is applied to the electrode of each pixel in the pixel array.

[0030] The entire operating mode therefore has a very high frequency duty cycle voltage modulation of the pixel electrode local to each pixel. Since all of these on / off events at the pixel electrode may occur much faster than the LC can respond, the LC responds with a root mean square (RMS) voltage equivalent to such a sequence if the entire pulse sequence is executed quickly enough.

[0031] In one embodiment, there may be no time overlap between voltage pulses on different G-bus lines. This allows modulation to be performed by comparing individual bits of pixel data in each pixel to the G-bus (containing the same number of bits) one bit at a time. This has a significant advantage: modifying the waveform on the G-bus allows the modulation algorithm to be completely changed.

[0032] In one embodiment, the system may also include a display loader configured to write values ​​representing multiple bits of image data for a row of display pixels into the row formatter and / or configured to write values ​​representing a subset of the multiple bits of image data for the row of pixels into multiple data latches of each pixel circuit.

[0033] In a system according to an embodiment of the present disclosure, a plurality of bits representing image data for a row of display pixels may be loaded from a cache system or other storage system (eg, a storage system including a memory device).

[0034] In another embodiment, the duration of each voltage pulse may be equal to the number of wave step clock cycles corresponding to the wave step value stored in the waveform increment memory. Each wave step value stored in the waveform increment memory may represent a different desired grayscale value. This enables the display to have a programmable response. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present disclosure is illustrated and described herein with reference to the various drawings, wherein like reference numerals are used to refer to like system components where appropriate, and wherein:

[0036] Figure 1 It is a display system of the prior art;

[0037] Figure 2 is a diagram of a DPM-a 2112x2112 pixel display according to an embodiment of the present disclosure;

[0038] Figure 3 is a flow chart of DPM operation according to an embodiment of the present disclosure;

[0039] Figure 4 is a partial array diagram according to an embodiment of the present disclosure;

[0040] Figure 5are row formatter details according to an implementation of the present disclosure;

[0041] Figure 6a and 6b A schematic diagram (6a) and a layout diagram (6b) of a pixel data latch according to an embodiment of the present disclosure are shown;

[0042] Figure 7 is an optimized layout of 8 pixel data latches according to an embodiment of the present disclosure;

[0043] Figure 8 are waveform generator details according to an embodiment of the present disclosure;

[0044] Fig. 9 is a logical diagram of a DPM pixel according to an embodiment of the present disclosure;

[0045] Fig.10 is a schematic diagram of a pixel according to an embodiment of the present disclosure;

[0046] Fig.11 is an example of a simple G-bus waveform according to an embodiment of the present disclosure;

[0047] Fig.12 is used Fig.11 A pixel electrode waveform of a G bus waveform for a data pattern "10101010";

[0048] Fig.13 is a pixel logic diagram for another embodiment of the present disclosure;

[0049] Fig.14 is a block diagram of a waveform generator for another embodiment of the present disclosure;

[0050] Fig.15 is an example Gamma curve implemented by embodiments of the present disclosure;

[0051] Fig.16 is used for Fig.14 a description of the contents of a waveform generator memory of a waveform generator; and

[0052] Fig.17 is a G-bus waveform diagram for another embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] Figure 1A simplified block diagram of a typical conventional display system 100 is shown. Such known displays rely on a controller (usually in a separate driver IC) 110 to write "bit planes" to a pixel array 120 located within a display circuit 130. The display circuit 130 also includes a column scanner 140 that stores and provides bit plane data 145 to the pixel array 120, and a row scanner 150 that provides control signals 155 to enable the data 145 to be written into the array 120. Each bit plane write will write either a "1" or a "0" into each pixel in the display 120. Any time it is desired to change the state of any pixel in any possible Gray code, an entire new bit plane needs to be written into the array 120. This has several disadvantages.

[0054] First, writing to the bit plane requires a lot of time. For example, an HD display with >2 million pixels typically requires 50μs to 100μs to write to the bit plane. This time sets a lower limit on how frequently a pixel can change state, and therefore determines the shortest pulse that can occur on the pixel electrode. Secondly, such a display 100 is very inefficient in array write activity. Most of the time, these bit plane writes will write "1" into a pixel memory (such as a static random access memory or SRAM) that is already in the 1 state, and write "0" into the SRAM that is already in the 0 state. These redundant writes are useless and waste power. In addition, they are inherent in the characteristics of the bit plane display 100 and cannot be eliminated without adding a lot of additional complexity to the pixel 120 and the array drive circuit system.

[0055] Third, feeding all of this bit-plane data 145 to the display 100 requires a large amount of data bandwidth, much of which is effectively wasted due to the redundancy described above. For example, sending a continuous sequence of bit-planes to a 1920x1080 HD display (using 100 μs bit-plane time) requires over 20 Gb / s. Supporting this data stream to the display requires extreme interface technologies (wide parallel buses or multiple SERDES links) and the attendant high power consumption that these imply. This also places demands on the driver IC 110 which is difficult to support and consumes a lot of power in the chip as well.

[0056] Figure 2 A block diagram of an LCoS display device 200 according to an embodiment of the present disclosure is shown. Figure 2The components include, but are not limited to, control registers 210; cache system 220; display loader 230; row formatter 240; row controller (Ctrl) 250; waveform generator 260; command FIFO file 270; and 2k x 2k pixel array 280 (grey block on the right). Other parts of the diagram may vary from one embodiment to another without significantly affecting the basic features of the embodiments of the present disclosure.

[0057] Figure 2 2 is a storage system 220 such as a cache system or storage system. In an embodiment of the present disclosure, the storage system includes a storage device such as a memory device. The cache or storage system 220 contains image data, organized as a working copy of an image or multiple images for three (3) color caches of red 290, green 300 and blue 310 data, each having an 8-bit depth. The image data includes multiple bits. It should be understood by those of ordinary skill in the art that the colors can vary. If the display is to be operated as a monochrome display, only one of these colors will actually be used. The data in these caches 220 is written during the previous frame using any image interface suitable for the particular display.

[0058] Before actual display operations can begin, the external control device 315 (CPU 316 or other data source or host) must write 330 values ​​to the "control registers" 210 to control the operation of the display. The control values ​​can be stored in a memory 317 on the external device 315. These control values ​​can include some or all of the following: image size in X, Y pixels; image offset from the left / top edge (if any); horizontal and / or vertical image flip (if necessary); line strobe settings and hold timing adjustments; timing resolution of the waveform generator 260; number of waveform generator pulses per subframe; and other mode control settings. The external control device 315 also needs to fill the command FIFO 270 with a series of internal commands. Some of these commands define the exact waveform and timing of the waveform generator 260. For example, the duration of each voltage pulse on the G bus can also be programmed via commands written to the display from software on the host or source. In one embodiment, there can be no time overlap between voltage pulses on different G bus lines.

[0059] Steering Figure 3 As shown in the flowchart 400 provided in FIG. 1 , once the control register is written, the display 280 waits for a "frame start" event at step 410. Typically, this will be decoded by a communication interface such as a MIPI interface. Figure 2 The color sequential device shown will actually have 3 or more color subframes. In this case, Figure 3The flowchart shown in FIG. 1 is applicable to each of these color subframes.

[0060] Figure 4 A simplified diagram of a "pixel array" 280 is shown in accordance with one embodiment of the present disclosure. The array 280 is simply a rectangular matrix of individual pixels. One of ordinary skill in the art will appreciate that the shape of the pixel array can vary. In one embodiment of the present disclosure, the pixels include a regular array of pixel circuits 285 connected to row and column lines. In an embodiment of the present disclosure, each individual pixel circuit 285 has a "pixel electrode" or LED 630 (see FIG. 1 ) connected to its output. Fig. 9 ), the pixel electrode 630 may be a square metal plate directly above the pixel circuit 285. In one embodiment of the present disclosure, the pixel electrode may be a reflective device such as a metal mirror device. In one embodiment of the present disclosure, the electrode may be an LED or an electrode coupled to an LED. In one embodiment of the present disclosure, an electric field that controls the behavior of the liquid crystal is formed between these pixel electrodes 630 and a Vcom electrode (not shown), which is a continuous transparent conductive film on the opposite side of the liquid crystal. The liquid crystal may be a liquid crystal on silicon array (LCoS) including a liquid crystal stacked between two substrates. For the purpose of describing embodiments of the present invention, an LCOS display is a reference. However, embodiments of the present disclosure may be combined with other types of displays such as LED displays such as micro-LED displays or used with other types of displays such as LED displays such as micro-LED displays. In addition, any reference to a display is also a reference to a micro-display.

[0061] The array 280 is arranged so that individual rows of pixel circuits 285 can be written in one operation by activating the "L_x" and "Ln_x" row strobe pairs for the row inputs or data inputs, where the "_x" simply indicates which row is being driven. Note that in Figure 4In , all inputs or outputs (G[7:0], L, Ln, Gset, UPDATE, RRead, D[7:0], GXOR, and DATAOUT) are appended with similar "_x" symbols. This is used to indicate which row or column each voltage is associated with. In an actual implementation, some of these inputs / outputs will be buffered versions of the original signals to prevent the circuit load from becoming too high. For example, in the first column, the D[7:0]_0 voltage drives the input to the 2112 pixel circuits in the first column. This is already a fairly heavy electrical load, and in an embodiment of the present disclosure, D[7:0]_0, D[7:0]_1, D[7:0]_2,... are driven from non-inverting buffers connected to the "main" D[7:0]. For clarity, the "_x" symbols and these buffering issues will be omitted in the rest of the description. In addition, Figure 4 Inputs "RRead_x" and outputs "DATAOUT_x" are shown. These are internal test inputs / outputs used for on-chip testing. It will be appreciated by one of ordinary skill in the art that the number of pixels, the number of pixel circuits, and the size of each pixel may vary in embodiments of the present disclosure.

[0062] Return to reference Figure 3 400, once the row controller or "display loader" 230 receives a frame start signal 410 from the data source (via the parser 275 and the command FIFO 270, using the time base 276), the display loader 230 begins writing 420 the appropriate data into the "row formatter" 240 during the next 16 clocks. A simplified diagram of the row formatter 240 is shown in FIG. Figure 5 As shown. Arrow 245 represents 16 writes of 1024 bits each arriving from display loader 230. Row formatter 240 handles image flipping and offsetting, and routes the data to row buffer registers 255 internal to row formatter 240. Filling the 2048 active image columns with 64 additional "steering" data columns is also performed. It will be appreciated by those of ordinary skill in the art that the number of steering columns may vary. Row buffer 255 has 2112 individual 8-bit outputs 265 forming an 8-bit "column-row" array. As shown in FIG. Figure 4 As shown, these outputs 265 of the row buffer 255 are connected to the display columns of the array 280. Once the row buffer 255 is filled, the display loader 230 (via the "row control" block 250) validates 430 the first "L / Ln" row strobe data pair for the first row. It will be appreciated by those of ordinary skill in the art that the number of bits can vary, the data can be represented by voltages, and the number of bit outputs can vary.

[0063] For each pixel in the row, the L / Ln voltage pairs enable the 8-bit data latch 500 in the pixel to capture (or latch) data from the associated column. In one embodiment of the present disclosure, there may be four to ten latches, including four latches and ten latches. However, it will be appreciated by those skilled in the art that the number of latches may vary. This strobing of the L / Ln voltage pairs remains valid for several clocks (the exact number may be programmed via a field in a control register) to give all data latches in the first row of pixel circuits time to capture data. Once these several clocks are completed, the L / Ln pairs fail. Figure 6a A schematic diagram of a pixel data latch 500 (for 1 bit) is shown, and Figure 6b is a simplified view of how pixel data latch 500 appears when arranged on the silicon or backplane of a display. Figure 7 A 4×2 (w / h and V mirrored) array 550 of 8 of these latches 500 is shown, which are used in each pixel. This illustrates that latch designs can be arranged very compactly. The pixel data latch 500 schematic is a variation of a standard "6T" SRAM. It is modified to include an "unload" transistor that allows ordinary logic signals to simply set or clear the latch when the "L" and "Ln" latch enables are valid. A complementary pair of inputs L and Ln is used instead of a single-ended input because this makes the pixel transistor level design simpler. However, in an embodiment of the present disclosure, a single-ended input can be used by adding additional inverting logic.

[0064] The display loader 230 then begins writing 440 the appropriate data into the row buffer 255 of the "row formatter" 240 again and validates 450 the next "L / Ln" row strobe pair for the next row. Figure 3 At step 460 in the display device 200, the display device 200 checks whether the last row has been reached. If the last row has not been reached, steps 440 to 460 are repeated until all 2112 rows in the array 280 have been written. At this stage, all pixels in the array 280 now contain image data. This entire process may take about 50 to 100 μs.

[0065] At this point in time, all the data required for the current frame (or color subframe in the case of a color sequential display) has been loaded into the pixel data latches and the actual display process can begin. From this point until the start of the next frame or subframe, the data interface and cache memory are not used, and all display data required to define the image resides in the pixel's static RAM pixel data latch 500.

[0066] The process is now Figure 3The simplified block diagram of the waveform generator 260 is shown in the block 470 of "Send Start Command to Waveform Generator". Figure 8 As shown. The waveform generator 260 receives commands 274 from the command FIFO 270. Additionally, the waveform generator 260 includes a waveform generator time base 266, which is a logic block that processes a clock to generate another clock and optionally generates a start / stop signal and sends these digital signals 267 to drive a loadable / clearable address counter 268 and a waveform generator memory 272. At step 260, the waveform memory address in the memory 272 is set to "0". The function of the waveform generator 260 is to drive a pulse pattern (represented by G[7:0]) onto an 8-bit "G bus" 262, which in turn is connected to each pixel in the display 280, and drives a "Gset" signal that is also routed to each pixel in the display 280. The G bus 262 works with the logic in each pixel to convert the pixel data stored in the pixel data latch 500 into a waveform presented on the pixel electrode 630 or presented to the pixel 281. The G bus signal is used to sequentially gate versions of the various bits of the pixel data latch 500 onto the pixel electrode 630, with the amount of time each gate is gated onto the pixel electrode 630 being determined by the timing of the G bus signal. The Gset signal is a latch enable signal for the pixel output latch. The actual waveform on the G bus 262 is programmable, and must actually be programmed at the start of operation. Determining this waveform is a complex process involving simulation of LC behavior. However, there are some general rules that these waveforms must follow for the DPM to work correctly: 1) At any time, only one of the 8 G bus signals can be true ("1"); 2) In each "sub-cycle" or "sub-frame", there must be at least 1 pulse on each line of the G bus; and 3) There must be a Gset pulse that coincides with the start of each pulse on any of the 8 lines of the G bus.

[0067] To understand how this works, it helps to look more closely at the logic in the pixel and the smallest G-bus waveform. Fig. 9 Pixel block diagram 600 showing pixel logic is shown. Pixel logic 600 is designed to be implemented with very few transistors. Fig. 9As can be seen, there are rows of 8 AND gates 610 and an OR gate 620 to collect the outputs from the AND gates 610. Normal "standard cell" AND gates or OR gates typically require about 8 to 10 transistors each, and a standard cell D latch such as a pixel data latch may require 20 or more transistors. However, in an implementation of a latch according to an embodiment of the present disclosure, only 8 transistors are used, and a single FET is used as the AND gate. This can be done in some cases, and the design is carefully designed to make it possible. Fig. 9 , it can be seen that the output of the OR gate 620 is fed into another AND gate 640 together with the Gset from the waveform generator 260. The same Gset is also fed directly to the output latch 650 together with the output of the AND gate 640. In some embodiments, the output of the latch 650 is fed into the XOR gate 660 together with the associated GXOR signal. The signal GXOR and the associated XOR gate are optional features and are not required in all implementations. Their purpose is to invert the waveform entering the level shifter 670. This is an advantage in non-color sequential applications, in which it is often necessary to replay an inverted version of the image in order to achieve DC balance and avoid image retention. By including this XOR function 660, the image can be inverted without the need to reload the image. For color sequential applications, this capability is of no value. Displays designed for such applications will typically omit this gate and the associated control signals. Finally, the output of the XOR gate (or latch 640) is directed to the pixel electrode 630.

[0068] Fig.10 Shows Fig. 9 A transistor level pixel schematic 700 of the pixel logic of FIG. 600 is shown. The dashed rectangle shows a FET as the equivalent of an AND gate 610, and the OR gate 620 is replaced with a common connection indicating the function as a "wired-OR" structure. Again, wired-OR connections or wired-OR connections are circuit features well known to digital design practitioners, and their use in this case saves a large number of transistors. It is estimated that if standard cell logic were used to implement this pixel design, more than 250 transistors would be required, but this version requires about 95 transistors (excluding level shifters using larger high voltage transistors). It has been shown that the entire circuit system including a suitable level shifter 670 can be arranged in a small pixel area such as a 3um x 3um pixel using a 28nm process geometry.

[0069] Fig.10One version of the pixel electrode level shifter 670 is shown, but other level shifting designs can be used with embodiments of the present disclosure without changing their effectiveness. Additionally, there are other modifications that can be made to the design that will not invalidate it. For example, PFET transistors can be used instead of NFET transistors, the Q output and Qn output of the data latch 500 can be swapped, signals can be replaced by their inverted versions, non-differential versions of the row strobe (L / Ln) can be used, etc. As previously mentioned, the signal GXOR and the associated XOR gate 660 are optional features of embodiments of the present disclosure.

[0070] Fig.11 A simple G bus waveform 800 is shown. As can be seen, the G bus signal is a binary weighted pulse with the MSB on G[7] and the LSB on G[0]. Looking at the beginning of waveform 800, assume the data pattern in the pixel is 170 in decimal, which is represented in binary as "10101010" (this data pattern is stored on the "8-bit latch" 550 in the pixel during the data loading operation). Fig.11 shows that G[7] is true for the first half of the 32 μs subframe (this is Figure 3 4, where waveform generator 260 outputs a pulse for G[7]. At step 490, a comparison is made between G[7] and D[7] to see if their corresponding bits match. Fig. 9 It is shown that if G[7] is "1", and if D[7] is also "1" (which is the same as 170 in decimal), this will cause the output of the topmost AND gate to be "1". This 1 will pass through OR gate 620 and end up at the input of output latch 650 (step 491), but only if the Gset signal is also set to true. This will set output latch 650, whose output passes through level shifter 670 and ends up at pixel electrode 630. The result is that pixel electrode 630 will be high for the first half of the frame.

[0071] At the end of the G[7] pulse, Fig.11 A new pulse is shown starting on G[6]. However, the bit from data latch 550 for D[6] is a "0". Since G[6] and D[6] are ANDed together, the output of the AND gate will be a 0, and this 0 will end up at the input of output latch 650 ( Figure 3492 in step 492). If the Gset pulse occurs at the beginning of the G[6] pulse, this will cause the output latch 650 to be cleared to the low state, and based on the G bus timing, this will mean that the voltage at the pixel electrode 630 will be low for the next 1 / 4 frame. At the end of the G[6] pulse, there is a new pulse on G[5], and since D[5] is also "1", the G[5] pulse will eventually cause the output latch to be set again, and the pixel electrode 630 will be high again - this time for the next 1 / 8 sub-cycle. This operation is repeated sequentially for G[4], G[3], G[2], G[1], and G[0].

[0072] Therefore, after each pulse, the display device 200 checks whether the previous pulse is the last pulse stored in the waveform memory 272 ( Figure 3 495 in step 497). If not, the waveform memory address in the memory 272 is incremented by one (step 496), and steps 480 to 495 are repeated. Otherwise, the Gset signal is a pulse of the waveform at step 497 ending with "0". At this time, a voltage waveform is generated on the pixel electrode 630 based on the data value of "10101010", and the pulses are high-low-high-low-high-low-high-low alternating, and the entire sequence takes 32 μs in this example.

[0073] Fig.12 The resulting voltage waveform 900 of the above process is shown. The exact values ​​for "high" and "low" depend on the level shifter 670 and the external Vpix supply (external Vpix supply not shown).

[0074] Fig.11 and Fig.12 A 32 μs period is shown for each bit of data on data latch 550. This is referred to herein as a "sub-cycle" or "color subframe," and 32 μs is a practical minimum subframe duration. In some applications, an image frame or color subframe lasts much longer than 32 μs, so the process may be repeated as many times as necessary to fill a frame or subframe. Fig.12An indication of this can be seen in , where the end of the previous subframe and the beginning of the next subframe can be seen. The total time given by the number of segments in a subframe multiplied by the number of repetitions of the subframe must be equal to or less than the length of the waveform memory. Note also that the waveform generator 260 has a programmable time base. If desired, different time base values ​​can be used as needed to make the subframes proportionally longer or shorter. Finally, it can be advantageously noted that: 1) there is no requirement in this system other than only requiring 1 pulse per G-bus line; and 2) the G-bus pulses are not required to be arranged in any particular order. For example, the MSB can be divided into, say, 4 segments, each of which is 1 / 4 of the normal duration, and these segments can be scattered among other pulses. This flexibility is an important advantage of embodiments of the present disclosure and allows for almost unlimited adjustment of the precise behavior of the DPM modulation. It is contemplated that a number of different waveform generator modes according to embodiments herein can be designed according to the needs of specific customers and / or display applications. These can be included in the system software according to embodiments of the present disclosure and can be loaded during the system startup process.

[0075] The action of the circuit system of an embodiment of the present disclosure results in a binary weighted waveform at the pixel electrode 630 or pixel 281 being repeated a fixed number of times during a frame. How this affects the LC state depends on the waveform timing. Liquid crystals commonly used in microdisplays like this have rise and fall times in the range of 400μs to 2ms. For voltage pulses at the pixel electrode equal to or longer than, say, about 100μs, the LC may begin to respond to the voltage pulse by at least starting to change state during the pulse. For example, for a drive waveform consisting of medium-length pulses like this, it becomes difficult to predict the response. The LC sees the pulse as long enough to approach a steady-state condition and attempts to fully respond to the pulse, becoming fully turned on or fully turned off. Typically, the pulse is not long enough to allow a full response before the next pulse begins. As a result, the LC exhibits a "history effect" in which the LC's response to any given pulse sequence depends on the history of the recent previous pulses. This is almost impossible to correct, and therefore this type of display must use PWM technology - PWM technology is more resistant to errors due to history effects.

[0076] For example, when the output is viewed using a fast-response photosensor, the LC transmission will change rapidly between mostly "on" and mostly "off" when displaying a mid-grey. (As mentioned earlier, "fast" in this context means having rise / fall times in the range of 400μs to 2ms). The eye can average out these rapid changes and give an acceptable appearance of continuous tone grey, although obtaining a smoothly varying grey ramp can be difficult due to the non-linear consequences of the history effect. However, this does not work at all when attempting to operate in phase mode, as the phase error actually affects detail at the location of image features, and the eye cannot average this out.

[0077] However, if the pulse length becomes much shorter, the situation changes significantly, and this is why DPM has a big advantage. Implementations of the present disclosure are not limited to bit plane timing, and therefore the individual pulses in a DPM subframe can be as short as needed. In an implementation, DPM has a complete subframe as short as 32μs, and a single pulse as short as 125ns. LC cannot respond to the individual pulses in such a sequence in any substantial way. Instead, the LC or pixel 281 will respond to the RMS equivalent of the voltage on the pixel electrode 630. This is both a quantitative difference and a qualitative difference. In a conventional digital display, the eye averages the optical appearance of a series of LED-generated light pulses or LC-generated light pulses into an equivalent grayscale. In contrast, in a DPM digital display according to an implementation of the present disclosure, the liquid crystal averages a series of voltage pulses into an equivalent grayscale. The LC display responds to a series of simulated DPM-type voltage pulses in exactly the same way as the LC display responds to an RMS equivalent DC voltage.

[0078] The advantage of amplitude mode displays lies primarily in the ease with which true 8-bit operation can be achieved without resorting to dithering (because amplitude mode displays can generate shorter pulses than in bit-plane displays). The advantage of phase mode displays is even more significant. The phase smoothness (or amount of phase ripple) for prior art digital displays depends on the length of the bit-plane, which is generally stated to be 50μs to 100μs. This bit-plane timing causes significant alternating overshoot and undershoot (typically 2-5%) in prior art phase mode displays, which is very objectionable and conflicts with obtaining a clear phase mode image. Because a DPM phase mode display according to an embodiment of the present disclosure does not have this minimum bit-plane duration requirement, a DPM phase mode display can easily generate phase shifts with a peak ripple amount that is at least an order of magnitude (10x) less than that of a comparable non-DPM display.

[0079] Fig.12The dashed line 910 is included. This is an indication to the liquid crystal of what this pulse sequence will look like. This is so because the longest pulse in the sequence is 16 μs, which is about 1 / 30 of the normal LC rise or fall time. Because these pulses are much shorter than what the LC can respond to, the LC responds to the RMS equivalent voltage of the entire sequence - symbolized by the dashed line 910.

[0080] exist Fig.13 In another embodiment of the pixel 1000 shown, the AND / OR tree is replaced by a more complex logic function 1010, such as XOR / OR, forming a comparison function between the value stored in the pixel memory 1020 and the value on the G bus 262. As previously described, a GSET signal is provided that generates a pulse at each change in the G bus value to update the final latch 1030 coupled to the final pixel driver or level shifter 1040. In one embodiment, the G bus 262 can contain a multi-bit binary counting pattern that increases or decreases the value at certain programmed time points, and the logic function 1010 will cause the logic result Y to be true only when the G bus value matches the value stored in the pixel memory 1020. Combined with the initial set or reset, this combination produces: a pulse width modulation (PWM) function, where the pulse width generated on the pixel electrode 630 is controlled by both the pixel memory content and the timing; and a sequence of values ​​on the G bus 262.

[0081] In embodiment 2000, Figure 8 The waveform generator is Fig.14 The waveform generator 2000 instead generates increasing or decreasing multi-bit values ​​on the G bus 262. As previously described, the waveform generator 2000 receives commands 2010 from the command FIFO 270 and includes a waveform generator time base 2020 and a waveform increment memory 2030. Once the direction is selected, an initial value (usually 0 or a maximum count such as 255 for an 8-bit value) is loaded into the up / down counter 2040 that drives the G bus 262. The output of the up / down counter 2040 is also used as an address to fetch a data value from the waveform increment memory 2030 and load that value into the down counter 2050. The waveform generator time base 2020 provides a step clock signal 2060 (a periodic clock waveform) that advances both counters 2040, 2050. When the down counter 2050 reaches 0, an advance signal 2070 is sent to the up / down counter 2040, allowing the up / down counter 2040 to decrement or increment. Incrementing and decrementing the up / down counter 2040 after a programmable number of cycles stored in the waveform increment memory 2030 enables a programmable response of the display. As discussed below Fig.17 As shown, one color subframe may include many increments / decrements. Fig.15An ideal gamma curve 3000 is compared to a linear level 3010. Here, an 8-bit grayscale is expanded to a 16-bit linear brightness level according to the exponential Gamma (in this example, Gamma = 2.2). For example, a grayscale level of 50 may correspond to a normalized intensity of 3%, corresponding to a pulse width of 487 wave step clock cycles, and a grayscale level of 200 may correspond to a normalized intensity level of 58%, corresponding to a pulse width of 9421 wave step clock cycles.

[0082] Fig.16 2030. In this example, it is desired to map the grayscale values ​​corresponding to the values ​​stored in each pixel memory to pulses having a width equal to the number of wave step clock periods or wave step clock signal clock periods. Fig.14 Given the structure of waveform generator 2000, it is only necessary to store the differences between the desired duration values ​​in waveform increment memory 2030 as shown in the waveform increment column.

[0083] Fig.17 Shown by Fig.14 A sequence of values ​​on the G bus 262 generated by the waveform generator 2000 of FIG. 4000 is shown, showing the counter 4010 and the corresponding pixel output 4020 representing about 16,000 steps of one color subframe 4030. The top 4040 presents a down-counting sequence, while the bottom presents an up-counting sequence 4050. Larger values, such as 255, can be programmed to last for a longer period of time on the bus 262, while smaller values ​​can be programmed to last for a shorter period of time. Displays according to the principles and embodiments described herein have unique characteristics that cannot be obtained using any other technology, especially in the field of phase modulation. The embodiments of this article include small pixel phase microdisplays capable of close to zero phase ripple, high efficiency, high contrast, and 8-bit phase modulation depth. Because no external driver chip is required, and because small pixels (3um to 4um) are possible, the overall display size is smaller than existing display plus driver solutions. The combination of high bit depth, high optical efficiency and contrast, and small physical size makes it a natural fit for emerging augmented reality applications, other head-mounted display applications, and compact head-up vehicle displays using amplitude mode.

[0084] The phase modulation capability of the embodiments herein is also a significant advantage. The combination of high bit depth (8 bits), high speed, very low phase ripple, and small pixels is suitable for devices with wide diffraction angles and requiring small pixels, such as holographic display applications. Therefore, when optical efficiency and wide diffraction angles are required, the embodiments provided herein with a size of about 3 μm are ideal.

[0085] The subject matter described herein may be implemented in digital electronic circuits or in computer software, firmware or hardware, including the structural devices disclosed in this specification and their structural equivalents or in a combination thereof. The subject matter described herein may be implemented as one or more computer program products, for example, tangibly implemented in an information carrier (e.g., in a machine-readable storage device) or implemented in one or more computer programs in a propagated signal, for execution by a data processing device (e.g., a programmable processor, a computer or multiple computers) or to control the operation of a data processing device (e.g., a programmable processor, a computer or multiple computers). Computer programs (also referred to as programs, software, software applications or codes) may be written in any form of programming language, including compiled languages ​​or interpreted languages, and may be deployed in any form, including as independent programs or as modules, components, subroutines or other units suitable for use in a computing environment. A computer program does not necessarily correspond to a file. A program may be stored in a portion of a file that stores other programs or data, a program may be stored in a single file dedicated to the program being discussed, or a program may be stored in multiple coordinated files (e.g., files storing portions of one or more modules, subroutines or codes). A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.

[0086] The processes and logic flows described in this specification, including the method steps of the subject matter described herein, can be performed by one or more programmable processors executing one or more computer programs to perform the functions of the subject matter described herein by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuits such as FPGAs (field programmable gate arrays) or ASICs (application-specific integrated circuits), and the apparatus of the subject matter described herein can be implemented as special purpose logic circuits such as FPGAs (field programmable gate arrays) or ASICs (application-specific integrated circuits).

[0087] By way of example, processors suitable for executing computer programs include both general-purpose microprocessors and special-purpose microprocessors and any one or more processors of any kind of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include or be operably coupled to one or more mass storage devices for storing data, to receive data from or transfer data to or to the one or more mass storage devices, or to perform both of the above, the one or more mass storage devices being, for example, magnetic disks, magneto-optical disks, or optical disks. Information carriers suitable for implementing computer program instructions and data include all forms of non-volatile memory, including by way of example: semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices); magnetic disks (e.g., internal hard disks or removable disks); magneto-optical disks; and optical disks (e.g., CD and DVD disks). The processor and memory may be supplemented by or incorporated into a dedicated logic circuit.

[0088] The subject matter described herein can be implemented in a computing system that includes a back-end component (e.g., a data server), a middleware component (e.g., an application server), or a front-end component (e.g., a client computer mobile device, a wearable device with a graphical user interface or a web browser through which a user can interact with an implementation of the subject matter described herein), or any combination of such back-end components, middleware components, and front-end components. The components of the system can be interconnected by any form or medium of digital data communication, such as a communication network. Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs") such as the Internet.

[0089] It should be understood that the disclosed subject matter is not limited to the details of construction in its application and is not limited to the arrangement of the parts set forth in the following description or shown in the accompanying drawings. The disclosed subject matter can be other embodiments and can be practiced and executed in various ways. In addition, it should be understood that the wording and terminology adopted herein are for descriptive purposes and should not be considered as limiting. Therefore, those skilled in the art will recognize that the conception on which the present disclosure is based can be easily used as the basis for designing other structures, methods and systems for several purposes for performing the disclosed subject matter. Therefore, it is important that the claims should be deemed to include such equivalent constructions in the case where such equivalent constructions do not depart from the spirit and scope of the disclosed subject matter.

[0090] While the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it should be understood that the present disclosure is made by way of example only and that many changes may be made to the details of the implementation of the disclosed subject matter without departing from the spirit and scope of the disclosed subject matter, which is limited only by the appended claims.

Claims

1. A system for generating a voltage and supplying the voltage to a pixel array, the system comprising: a plurality of display pixels forming the pixel array, each display pixel comprising a pixel circuit for driving the pixel and the pixel circuit comprising a plurality of data latches and an output latch, the pixel array being a liquid crystal on silicon array comprising a liquid crystal material stacked between two substrates; a row formatter configured to store a plurality of bits representing image data for a row of display pixels of the pixel array; a row controller configured to write a subset of the plurality of bits representing image data for display pixels of the row into the plurality of data latches of the pixel circuits; a waveform generator for generating a reference pulse represented by a set of reference bits, and wherein the number of the set of reference bits is equal to or corresponds to the number of bits stored in the data latch of each pixel circuit, the waveform generator being connected to each pixel via a global modulation bus, the width of the global modulation bus being equal to the number of bits stored in the latch of each pixel circuit, the waveform generator being configured to periodically and sequentially issue a word of memory content on the global modulation bus to generate a plurality of voltage pulses equal to the width of the global modulation bus on different global modulation bus lines of the global modulation bus, and wherein: A voltage pulse on a global modulation bus line of the global modulation bus can be divided across several global modulation bus lines; The duration of each voltage pulse on each line of the global modulation bus is programmable; and The duration of the voltage pulse is significantly shorter than the liquid crystal response time; Wherein, the pixel circuit is configured as follows: comparing each reference bit with a corresponding bit stored in the data latch of each pixel circuit and generating a voltage at an electrode of each pixel based on the comparison, all bits stored in the data latch of the pixel circuit being compared with their corresponding bits stored in the waveform generator within a time period shorter than a response time of the liquid crystal; When the Gset signal output from the waveform generator is applied to the output latch, if the corresponding bit in the data latch is equal to "1", bit "1" is input to the output latch, otherwise, bit "0" is input to the output latch.

2. The system according to claim 1, wherein: A voltage supplied to the pixel electrode modulates at least one of polarization, reflectivity, amplitude, and phase of light reflected from the display pixel.

3. The system according to claim 1, wherein: The number of bits stored in the data latch of each pixel circuit is 4 bits to 10 bits.

4. The system according to claim 1, wherein: The initiation of the Gset signal coincides with the start of each voltage pulse on the global modulation bus line.

5. The system according to claim 4, wherein: The output of the output latch is input to a level shifter.

6. The system according to claim 5, wherein: The pixel array is an LCOS array, and wherein the output of the level shifter is a voltage having a high voltage when the output of the output latch of the pixel circuit is bit "1" and having a low voltage when the output of the output latch of the pixel circuit is bit "0", wherein the voltage on the output of the level shifter is applied to an electrode of each pixel in the LCOS array.

7. The system according to claim 6, wherein: There is no time overlap between the voltage pulses on different global modulation bus lines.

8. The system of claim 1 , further comprising a display loader configured to write values ​​of the plurality of bits representing image data for a row of display pixels into the row formatter and / or configured to write values ​​of the subset of the plurality of bits representing image data for the row of pixels into the plurality of data latches of each pixel circuit.

9. The system according to claim 1, wherein: The plurality of bits representing image data for a row of display pixels are loaded from a memory system.

10. The system according to claim 9, wherein: A logic function is used to compare all bits stored in the data latch of each pixel circuit to their corresponding reference bits within a period of time shorter than the liquid crystal response time.

11. The system according to claim 10, wherein: The duration of each voltage pulse is equal to the number of wave step clock cycles corresponding to the wave step value stored in the waveform increment memory.

12. The system according to claim 11, wherein: Each waveform step value stored in the waveform increment memory represents a different desired grayscale value.

13. The system of claim 2, wherein: The voltage supplied to the pixel electrode modulates the polarization of light reflected from the display pixel.

14. The system of claim 2, wherein: The voltage supplied to the pixel electrode modulates a reflectivity of light reflected from the display pixel.

15. The system of claim 2, wherein: The voltage supplied to the pixel electrode modulates the amplitude of light reflected from the display pixel.

16. The system of claim 2, wherein: The voltage supplied to the pixel electrode modulates the phase of light reflected from the display pixel.

17. The system of claim 8, wherein: The display loader is configured to write into the row formatter a value representing a plurality of bits of image data for a row of display pixels.

18. The system according to claim 8, wherein: The display loader is configured to write values ​​of the subset of the plurality of bits representing image data for pixels of the row into the plurality of data latches of each pixel circuit.

19. The system of claim 1, wherein: There is no temporal overlap between the voltage pulses on different global modulation bus lines.

20. The system of claim 1, wherein: The duration of each voltage pulse is equal to the number of wave step clock cycles corresponding to the wave step value stored in the waveform increment memory.

Images