Clockless asynchronous circuit, data synchronous output method, device and medium

Abstract

This invention discloses a clockless asynchronous circuit, a method, device, and medium for synchronous data output. By adding several signal values ​​to the existing 0 and 1 signal values ​​and outputting these signal values ​​through a clockless asynchronous circuit, the effect of transmitting multiple signal values ​​on a single data line is achieved. Through the clockless asynchronous circuit, the input module converts the initial signal value and outputs a first operation signal for logical operations by the internal module. This enables the internal module to output a first operation result based on the first operation signal, and the output module to output a second operation result based on the first operation result, which is used by the asynchronous circuit to determine whether to output data. This achieves the effect of data clock synchronization while avoiding the power loss of the asynchronous circuit caused by clock signals or clock recovery circuits.

Description

Technical Field

[0001] The present invention relates to the field of clock synchronization technology, and in particular to a clockless asynchronous circuit, a method for synchronous data output, a hardware interface device and a computer-readable storage medium. Background Art

[0002] Due to the basic failure of Moore's Law, the clock synchronization problem of the chip and the power consumption problem caused by clock synchronization have become a major problem in designing and developing chips. In order to achieve the effect of clock synchronization and avoid the power consumption problem caused by clock synchronization, signal values ​​are generally transmitted through two data lines and some additional coding bits. However, this method has the problems of too many data lines and reduced transmission efficiency, and the addition of additional coding bits cannot effectively replace clock synchronization, so there is still a need for a clock recovery circuit. Summary of the invention

[0003] The main purpose of the present invention is to propose a clock-free asynchronous circuit, a method for synchronous data output, a hardware interface device and a computer-readable storage medium, aiming to solve the existing methods for solving the clock synchronization problems of chips and the power consumption caused by clock synchronization. The methods have many data lines and reduced transmission efficiency, and the addition of additional coding bits cannot effectively replace clock synchronization, and thus there is still a technical problem of requiring a clock recovery circuit.

[0004] To achieve the above object, the present invention provides a clock-free asynchronous circuit, the clock-free asynchronous circuit comprising a conversion circuit;

[0005] The conversion circuit is used to access the initial signal value and output the initial signal value after performing a logic operation, so that the transmission device determines whether to transmit data based on the initial signal value after the logic operation.

[0006] Optionally, the conversion circuit includes an input module, an internal module and an output module;

[0007] The output end of the input module is connected to the input end of the output module through the internal module.

[0008] Optionally, the input module includes an inputA terminal, an inputB terminal, an inputC terminal, a first PMOS transistor, a first NMOS transistor, a first resistor and a second resistor;

[0009] The inputA terminal is connected to the gates of the first PMOS tube and the first NMOS tube respectively, the drain of the first PMOS tube is connected to the positive electrode of the first DC power supply, the drain of the first NMOS tube is connected to the positive electrode of the first DC power supply, the source of the first NMOS tube is connected to the same potential, the inputB terminal is connected to the source of the first PMOS tube, and the inputC terminal is connected to the drain of the first NMOS tube;

[0010] One end of the first resistor is connected to the source of the first PMOS tube, and the other end of the first resistor is connected to an equipotential;

[0011] One end of the second resistor is connected between the drain of the first NMOS tube and the positive electrode of the first DC power supply.

[0012] Optionally, the output module includes an outputA terminal, an outputB terminal, an outputC terminal, a second PMOS transistor, a second NMOS transistor and a third resistor;

[0013] The outputA terminal is connected to the gate of the second PMOS tube, the outputB terminal is connected to the gate of the second NMOS tube, one end of the third resistor is connected to the source of the second PMOS tube, the other end of the third resistor is connected to the drain of the second NMOS tube, the drain of the second PMOS tube is connected to the second direct current, and the outputC terminal is connected between the second PMOS tube and the third resistor.

[0014] Optionally, the clock-free asynchronous circuit further includes a communication data line;

[0015] The communication data line is used for the output module to send a confirmation signal to the input module.

[0016] The present invention also provides a method for synchronously outputting data, the method comprising the following steps:

[0017] When an initial signal value is received through an input module in the conversion circuit, a first signal value to be operated is generated based on the input module, and the signal value to be operated is sent to an internal module of the conversion circuit for logic operation to obtain a first operation result;

[0018] Outputting the first operation result to the output module of the conversion circuit, generating a second operation result based on the output module, and determining whether the second operation result meets a preset output condition;

[0019] If the second operation result meets the preset output condition, the data is output synchronously.

[0020] Optionally, after the step of determining whether the second operation result meets a preset output condition, the method further includes:

[0021] If the second operation result does not meet the preset output condition, the data is not output.

[0022] Optionally, after the step of outputting the first operation result to the output module of the conversion circuit, the method further includes:

[0023] A confirmation signal is generated through the communication data line and sent to the input module.

[0024] In addition, to achieve the above-mentioned purpose, the present invention also provides a hardware interface device, which includes a clock-free asynchronous circuit, a memory, a processor, and a computer program stored in the memory and executable on the processor, and the computer program implements the steps of the above-mentioned data synchronous output method when executed by the processor.

[0025] In addition, to achieve the above-mentioned purpose, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned method for synchronous data output are implemented.

[0026] The technical solution of the present invention realizes the transmission of multiple signal values ​​on one signal line by constructing a clock-free asynchronous circuit with a conversion circuit. Through the logical operation inside the conversion circuit, the reduction in effective transmission efficiency caused by adding additional coding bits is avoided. At the same time, the logical operation of the conversion circuit can realize the synchronous output of data based on the response mechanism without the need for a clock recovery circuit or a clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0028] Figure 1 It is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiment of the present invention;

[0029] Figure 2 It is a schematic diagram of the modules inside the conversion circuit of the present invention;

[0030] Figure 3 It is a schematic diagram of the input circuit of the clockless asynchronous circuit;

[0031] Figure 4 It is a schematic diagram of the output circuit of the clockless asynchronous circuit;

[0032] Figure 5 A schematic diagram of a flow chart of an embodiment of a method for synchronously outputting data according to the present invention;

[0033] Figure 6 It is a schematic diagram of a hardware interface circuit based on a clockless asynchronous circuit;

[0034] Figure 7 It is a structural diagram of the communication data line.

[0035] Description of Figure Numbers:

[0036] Label name 10 Input Module 20 Internal modules 30 Output Module PQ1-PQ2 PMOS tube NQ1-NQ2 NMOS tube R1-R3 resistance V1-V2 DC Power Supply

[0037] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0038] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0039] The main solution of the embodiment of the present invention is: by adding several signal values ​​to the original signal value of 0 and signal value of 1, the conversion circuit performs a logical operation on the initial signal value and outputs a second operation result of the signal value of 0 and the signal value of 1, and then forcibly outputs a second operation result of the idle value. Based on the judgment of the signal value contained in the second operation result, if the second operation result does not contain the idle value, the asynchronous circuit considers that data can be sent at this time, thereby realizing synchronous data transmission without the need for a clock signal or a clock recovery circuit.

[0040] In the prior art, due to the characteristics of asynchronous circuits, asynchronous circuits need to be equipped with clock signals or clock recovery circuits to achieve synchronous data transmission. However, the clock signals or clock recovery circuits cause serious power consumption in asynchronous circuits.

[0041] The present invention provides a solution, which realizes the transmission of multiple signal values ​​on one signal line by building a clock-free asynchronous circuit with a conversion circuit. Through the logical operation of the conversion circuit, the reduction in effective transmission efficiency caused by adding additional coding bits is avoided. At the same time, the logical operation of the conversion circuit can realize clock synchronization based on a response mechanism without the need for a clock recovery circuit.

[0042] like Figure 1 As shown, Figure 1 It is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiment of the present invention.

[0043] The data synchronization output device in the embodiment of the present invention may be a PC, or may be a portable terminal device with a display function, such as a tablet computer or a portable computer.

[0044] like Figure 1 As shown, the terminal may include: a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may optionally be a storage device independent of the aforementioned processor 1001. The terminal is placed on the nasal acoustic reflectometer.

[0045] Optionally, the data synchronization output device may also include a camera, an RF (Radio Frequency) circuit, a sensor, an audio circuit, a WiFi module, and the like. Among them, sensors such as light sensors, motion sensors, and other sensors. Specifically, the light sensor may include an ambient light sensor and a proximity sensor, wherein the ambient light sensor may adjust the brightness of the display screen according to the brightness of the ambient light, and the proximity sensor may turn off the display screen and / or backlight when the mobile terminal is moved to the ear. As a type of motion sensor, the gravity acceleration sensor can detect the magnitude of acceleration in each direction (generally three axes), and can detect the magnitude and direction of gravity when stationary. It can be used for applications that identify the posture of the mobile terminal (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tapping), etc.; of course, the mobile terminal can also be equipped with other sensors such as gyroscopes, barometers, hygrometers, thermometers, infrared sensors, etc., which will not be repeated here.

[0046] Those skilled in the art will understand that Figure 1 The structure of the data synchronization output device shown in the figure does not constitute a limitation on the data synchronization output device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0047] like Figure 1 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module and a computer program.

[0048] exist Figure 1 In the terminal shown, the network interface 1004 is mainly used to connect to the backend server and communicate data with the backend server; the user interface 1003 is mainly used to connect to the client (user end) and communicate data with the client; and the processor 1001 can be used to call the computer program stored in the memory 1005 and perform the following operations:

[0049] When an initial signal value is received through an input module in the conversion circuit, a first signal value to be operated is generated based on the input module, and the signal value to be operated is sent to an internal module of the conversion circuit for logic operation to obtain a first operation result;

[0050] Outputting the first operation result to the output module of the conversion circuit, generating a second operation result based on the output module, and determining whether the second operation result meets a preset output condition;

[0051] If the second operation result meets the preset output condition, the data is output synchronously.

[0052] Further, the processor 1001 may call the computer program stored in the memory 1005 and perform the following operations:

[0053] The step of controlling the spark generator to perform periodic discharge based on the FPGA controller includes: applying a preset DC voltage to the control end of the spark generator based on the FPGA controller to control the discharge electrode of the spark generator to perform periodic discharge.

[0054] Further, the processor 1001 may call the computer program stored in the memory 1005 and perform the following operations:

[0055] After the step of determining whether the second operation result meets the preset output condition, if the second operation result does not meet the preset output condition, no data is output.

[0056] Further, the processor 1001 may call the computer program stored in the memory 1005 and perform the following operations:

[0057] After the step of outputting the first operation result to the output module of the conversion circuit, a confirmation signal is generated through a communication data line, and the confirmation signal is sent to the input module.

[0058] Reference Figure 2 , an embodiment of the present invention provides a clock-free asynchronous circuit, the clock-free asynchronous circuit includes a conversion circuit;

[0059] The conversion circuit is used to access the initial signal value and output the initial signal value after performing a logic operation, so that the transmission device determines whether to transmit data based on the initial signal value after the logic operation.

[0060] Further, the conversion circuit includes an input module 10, an internal module 20 and an output module 30;

[0061] The output end of the input module 10 is connected to the input end of the output module 30 through the internal module 20 .

[0062] It should be noted that the signal values ​​transmitted by traditional digital circuits are all based on 0, 1 signal values. In order to ensure the clock synchronization of the transmission of 0, 1 signal values, a clock is added to the traditional digital circuit to achieve the clock synchronization effect. In order to avoid the power consumption caused by the clock and ensure the clock synchronization effect of the signal value transmission, the present invention adds several signal values ​​on the basis of the existing 0, 1 signal value.

[0063] In this embodiment, taking the addition of a signal value based on the existing 0 and 1 signal values ​​as an example, the clock-free asynchronous circuit in this embodiment contains three signal values, namely 0, 1 and i signal values, wherein the meanings of 0 and 1 signal values ​​are the same as those in traditional digital circuits, and the i signal value is used as a judgment value (or an idle value). When the signal value output by the input module 10 is the i signal value, the output circuit 30 considers that the logical operation of the 0 and 1 signal values ​​in the internal module 20 is not ready yet, and the output module 30 does not perform output calculations on the previously received 0 and 1 signal values. Only when it is detected that the i signal value becomes 0 or 1 signal value, the output module 30 determines that the logical operation of the previous 0 and 1 signal values ​​in the internal module 20 is ready, and the output module 20 performs a synchronous output operation on the previously received 0 and 1 signal values, thereby achieving the beneficial effect of clock synchronization.

[0064] Furthermore, the input module 10 includes an inputA terminal, an inputB terminal, an inputC terminal, a first PMOS transistor PQ1, a first NMOS transistor NQ1, a first resistor R1 and a second resistor R2;

[0065] The inputA terminal is connected to the gates of the first PMOS (Positive channel-Metal-Oxide-Semiconductor, P-type metal oxide semiconductor) tube PQ1 and the first NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) tube NQ1 respectively, the drain of the first PMOS tube PQ1 is connected to the positive electrode of the first DC power supply V1, the drain of the first NMOS tube NQ1 is connected to the positive electrode of the first DC power supply V1, the source of the first NMOS tube NQ1 is connected to the same potential, the inputB terminal is connected to the source of the first PMOS tube PQ1, and the inputC terminal is connected to the drain of the first NMOS tube NQ1; one end of the first resistor R1 is connected to the source of the first PMOS tube PQ1, and the other end of the first resistor R1 is connected to the same potential; one end of the second resistor R2 is connected between the drain of the first NMOS tube NQ1 and the positive electrode of the first DC power supply V1.

[0066] Specifically, according to Figure 3 The input module shown in the figure has different outputs for the PMOS and NMOS transistors based on the same initial input signal value. Figure 4 The input module shown in the figure is converted to obtain a set of signal values ​​to be operated (i.e., input0 and input1 in 3). The specific truth table of the input module is shown in Table 1:

[0067] Table 1

[0068] input input0 input1 0 1 1 1 0 0 i 0 1

[0069] 1. When the initial signal value input connected to the inputA terminal is a signal value of 0, the signal value of 0 flows to the first PMOS transistor PQ1 and the first NMOS transistor NQ1 respectively through the same data line. Based on the different conduction properties of the PMOS transistor and the NMOS transistor, the signal value of 0 passes through the first PMOS transistor PQ1, so that the first PMOS transistor PQ1 is turned on, and the first DC power supply V1 outputs a signal value of 1 to the inputB terminal through the first PMOS transistor PQ1. At the same time, the signal value of 0 passes through the first NMOS transistor NQ1, so that the first NMOS transistor NQ1 is turned off, and the first DC power supply V1 directly outputs a signal value of 1 to the inputC terminal through the second resistor R2.

[0070] 2. When the initial signal value input connected to the inputA terminal is a signal value of 1, the signal value of 1 flows to the first PMOS transistor PQ1 and the first NMOS transistor NQ1 respectively through the same data line. Based on the different conduction properties of the PMOS transistor and the NMOS transistor, the signal value of 1 passes through the first PMOS transistor PQ1, so that the first PMOS transistor PQ1 is cut off, and the inputB terminal directly outputs a signal value of 0. At the same time, the signal value of 1 passes through the first NMOS transistor, so that the first NMOS transistor NQ1 is turned on, and the first DC power supply V1 flows directly into the ground through the first NMOS transistor NQ1, so that the inputC terminal directly outputs a signal value of 0.

[0071] 3. When the initial signal value input connected to the inputA terminal is the i signal value, the i signal value flows to the first PMOS transistor PQ1 and the first NMOS transistor NQ1 respectively through the same data line, so that the first PMOS transistor PQ1 and the first NMOS transistor NQ1 are in the cut-off state at the same time. Therefore, at this time, the inputB terminal directly outputs a 0 signal value, and the first DC power supply V1 directly outputs a 1 signal value to the inputC terminal through the second resistor R2.

[0072] Among them, the signal values ​​of inputB and inputC constitute the signal values ​​to be calculated and output to the internal module for logical operation.

[0073] Further, the output module includes an outputA terminal, an outputB terminal, an outputC terminal, a second PMOS transistor PQ2, a second NMOS transistor NQ2 and a third resistor R3;

[0074] The outputA terminal is connected to the gate of the second PMOS tube PQ2, the outputB terminal is connected to the gate of the second NMOS tube NQ2, one end of the third resistor R3 is connected to the source of the second PMOS tube PQ2, the other end of the third resistor R3 is connected to the drain of the second NMOS tube NQ2, the drain of the second PMOS tube PQ2 is connected to the second direct current, and the outputC terminal is connected between the second PMOS tube PQ2 and the third resistor R3.

[0075] Specifically, according to Figure 4 The output module shown in FIG. 1 converts the three signal values ​​into the output logic of the PMOS tube and the NMOS tube according to the first operation result (i.e., output0 and output1) output by the internal module. Figure 4 The output module shown in FIG. 1 is converted to obtain the second operation result (i.e. Figure 4 The specific truth table of the output module is shown in Table 2:

[0076] Table 2

[0077] output0 output1 output 0 0 1 1 1 0 1 0 i

[0078] 1. When the signal values ​​received by the outputA terminal and the outputB terminal based on the first operation result are both 0 signal values, the outputA terminal inputs the 0 signal value into the second PMOS tube PQ2, so that the second PMOS tube PQ2 is turned on, and the outputB terminal inputs the 0 signal value into the second NMOS tube NQ2, so that the second NMOS tube NQ2 is turned off, so that the second DC power supply V2 outputs a 1 signal value to the outputC terminal via the second PMOS tube PQ2.

[0079] 2. When the signal values ​​received by the outputA terminal and the outputB terminal based on the first operation result are both 1 signal value, the outputA terminal inputs the 1 signal value into the second PMOS tube PQ2, so that the second PMOS tube PQ2 is turned off, and the outputB terminal inputs the 1 signal value into the second NMOS tube NQ2, so that the second NMOS tube NQ2 is turned on. Because the second DC power supply V2 directly forms a branch with the second NMOS tube NQ2 through the second PMOS tube PQ2, when the second PMOS tube PQ2 is turned off, the outputC terminal directly outputs a 0 signal value.

[0080] 3. When the signal values ​​received by the outputA terminal and the outputB terminal based on the first operation result are respectively the signal value of 1 and the signal value of 0, the outputA terminal inputs the signal value of 1 into the second PMOS tube PQ2, so that the second PMOS tube PQ2 is turned off, and the outputB terminal inputs the signal value of 0 into the second NMOS tube NQ2, so that the second NMOS tube NQ2 is turned off. Because the second PMOS tube PQ2 and the second NMOS tube NQ2 are both in the cut-off state at this time, the outputC terminal outputs the signal value i at this time.

[0081] It should be noted that the initial signal value received by the input module is transmitted based on the 0 signal value, 1 signal value, and i signal value. Assuming that the initial signal value received by inputA for the first time is the 0 signal value, the initial signal value received for the second time is the 1 signal value. After the 0 signal value and the 1 signal value are cycled, the initial signal value will return to the i signal value, and the i signal value will be output to the input module.

[0082] Further, refer to Figure 6 and Figure 7 , the clock-free asynchronous circuit also includes a communication data line;

[0083] The communication data line is used for the output module 30 to send a confirmation signal to the input module 10 .

[0084] In this embodiment, in order to notify the input module 10 that the reception is completed, a communication data line is connected between the input module 10 and the output module 30, so that when the output module 30 receives the first operation result output by the internal module 20, the communication data line can generate a confirmation signal and send the confirmation signal to the input module 10, thereby realizing a full-duplex communication mode. While notifying the input module 10, it can also avoid interference with the signal value transmitted between the input module 10 and the output module 30, and has a higher data transmission speed.

[0085] and Figure 6 A hardware interface circuit constructed based on the above clockless asynchronous circuit, wherein the sender end is an input module 10, and the receiver end is an output module 30, wherein a clockless asynchronous circuit may include multiple hardware interface circuits. Figure 7 It is a communication data line connected between the output module 30 and the input module 10. The Ack (confirmation signal) terminal is located at the output module 30 for generating a confirmation signal, and the ACK detect (confirmation signal detection) terminal is located at the input module 10 for receiving a confirmation signal.

[0086] Reference Figure 5 An embodiment of the present invention further provides a method for synchronously outputting data, the method for synchronously outputting data comprising:

[0087] Step S10, when an initial signal value is received through an input module in the conversion circuit, a first signal value to be operated is generated based on the input module, and the signal value to be operated is sent to an internal module of the conversion circuit for logic operation to obtain a first operation result;

[0088] Step S20, outputting the first operation result to the output module of the conversion circuit, generating a second operation result based on the output module, and determining whether the second operation result meets a preset output condition;

[0089] Step S30: if the second operation result meets the preset output condition, the data is output synchronously.

[0090] It should be noted that the initial signal value is not limited to one, it can be several. Similarly, the first signal value to be calculated and the first calculation result are also the same. However, there can be only one second calculation result, because the role of the second calculation result is to use the asynchronous circuit to determine whether to transmit data at this time. If there are several second calculation results, it will cause the asynchronous circuit to have confusion in judgment and cause data issuance errors.

[0091] For example, assuming that the initial signal value received by the input module includes a signal value of 0 and a signal value of 1, the input module at this time will generate a signal value to be calculated based on the initial signal value, which includes a group of signal values ​​of 1 and 1 and a group of signal values ​​of 0 and 0. After outputting the signal value to be calculated to the internal module, assuming that after the logical operation based on the internal module, the first operation result including the signal value of 0 and the signal value of 1 is output.

[0092] After the internal module completes the logic operation and obtains the first operation result, it will output the first operation result to the output module, and output the second operation result based on the PMOS tube and NMOS tube in the output module to determine whether the asynchronous circuit at this time triggers the preset output condition, wherein the preset output condition is whether the second operation result is an i signal value, and if the second operation result is a 0 signal value or a 1 signal value. It is considered that the data in the internal module is fully prepared at this time, and the data output at this time will not result in incomplete data. At this time, the asynchronous circuit will output the data synchronously, so as to achieve the effect of realizing the clock synchronization of the asynchronous circuit without any clock signal or clock recovery circuit.

[0093] Optionally, after the step of determining whether the second operation result meets a preset output condition in step S20, the method further includes:

[0094] Step S21: if the second operation result does not meet the preset output condition, then the data is not output.

[0095] If the second operation result is the i signal value, it is considered that the data in the internal module is not ready at this time. Sending the data at this time will result in incomplete data. The data is not output at this time to avoid a decrease in data accuracy.

[0096] Optionally, after the step of outputting the first operation result to the output module of the conversion circuit in step S20, the method further includes:

[0097] Step S22, generating a confirmation signal through the communication data line, and sending the confirmation signal to the input module.

[0098] Among them, the second result to be calculated can be understood as the next first result to be calculated. By connecting a communication data line, such as an Ack line, between the input module and the output module, after the output module receives the first calculation result output by the internal module, in order to reflect timeliness, it is necessary to notify the input module to achieve the effect of fast data transmission. Therefore, by connecting a communication data line between the input module and the output module, when the output module receives the first calculation result, the communication data line synchronously generates and sends a confirmation signal value to the input module, so that the input module quickly outputs the next result to be calculated.

[0099] In this embodiment, by constructing a conversion circuit inside the asynchronous circuit, the asynchronous circuit can achieve clock synchronization without any clock signal or clock recovery circuit. The input module converts the initial signal value and outputs a first signal to be operated for the internal module to perform logic operation, so that the internal module can output a first operation result based on the first signal to be operated, and the output module can output a second operation result for the asynchronous circuit to determine whether to output data based on the first operation result. That is, the effect of clock synchronization of data is achieved, and the power consumption of the asynchronous circuit caused by the clock signal or clock recovery circuit is avoided.

[0100] In addition, an embodiment of the present invention also proposes a hardware interface device, which includes a clock-free asynchronous circuit, a memory, a processor, and a computer program stored in the memory and executable on the processor, and the computer program implements the steps of the above-mentioned data synchronous output method when executed by the processor.

[0101] In addition, the present invention also proposes a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned method for synchronous data output are implemented.

[0102] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0103] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0104] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0105] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A clockless asynchronous circuit, characterized in that: The clockless asynchronous circuit includes a conversion circuit; The conversion circuit is used to access the initial signal value and output the initial signal value after performing a logic operation, so that the transmission device determines whether to transmit data based on the initial signal value after the logic operation; The conversion circuit includes an input module and an output module; The input module includes an inputA terminal, an inputB terminal, an inputC terminal, a first PMOS transistor, a first NMOS transistor, a first resistor and a second resistor; The inputA terminal is connected to the gates of the first PMOS tube and the first NMOS tube respectively, the drain of the first PMOS tube is connected to the positive electrode of the first DC power supply, the drain of the first NMOS tube is connected to the positive electrode of the first DC power supply, the source of the first NMOS tube is connected to the same potential, the inputB terminal is connected to the source of the first PMOS tube, the inputC terminal is connected to the drain of the first NMOS tube, one end of the first resistor is connected to the source of the first PMOS tube, the other end of the first resistor is connected to the same potential, and one end of the second resistor is connected between the drain of the first NMOS tube and the positive electrode of the first DC power supply; When the initial signal value connected to the inputA terminal is a signal value of 0, the inputB terminal outputs a signal value of 1 and the inputC terminal outputs a signal value of 1, or when the initial signal value connected to the inputA terminal is a signal value of 1, the inputB terminal outputs a signal value of 0 and the inputC terminal outputs a signal value of 0, or when the initial signal value connected to the inputA terminal is a signal value of i, the inputB terminal outputs a signal value of 0 and the inputC terminal outputs a signal value of 1, wherein the signal values ​​of the inputB terminal and the inputC terminal constitute the signal values ​​to be calculated and are output to the internal module for logical calculation, and a first calculation result is output; The output module includes an outputA terminal, an outputB terminal, an outputC terminal, a second PMOS transistor, a second NMOS transistor and a third resistor; The outputA terminal is connected to the gate of the second PMOS tube, the outputB terminal is connected to the gate of the second NMOS tube, one end of the third resistor is connected to the source of the second PMOS tube, the other end of the third resistor is connected to the drain of the second NMOS tube, the drain of the second PMOS tube is connected to the second direct current, and the outputC terminal is connected between the second PMOS tube and the third resistor; When the signal values ​​received by the outputA terminal and the outputB terminal based on the first operation result are both 0 signal values, the outputC terminal outputs a 1 signal value, or when the signal values ​​received by the outputA terminal and the outputB terminal based on the first operation result are both 1 signal values, the outputC terminal outputs a 0 signal value, and when the signal values ​​received by the outputA terminal and the outputB terminal based on the first operation result are respectively 1 signal values ​​and 0 signal values, the outputC terminal outputs a i signal value, wherein the outputC terminal outputs a second operation result; By adding several signal values ​​to the original signal value of 0 and signal value of 1, after the conversion circuit performs a logical operation on the initial signal value and outputs the second operation result of the signal value of 0 and signal value of 1, the second operation result in which the second operation result is an idle value is output, and based on the judgment of the signal value included in the second operation result, if the second operation result does not contain the idle value, the asynchronous circuit considers that data is being sent at this time, wherein the idle value is the i value.

2. The clock-free asynchronous circuit according to claim 1, characterized in that: The conversion circuit also includes an internal module; The output end of the input module is connected to the input end of the output module through the internal module.

3. The clock-free asynchronous circuit according to claim 1, characterized in that: The clock-free asynchronous circuit also includes a communication data line; The communication data line is used for the output module to send a confirmation signal to the input module.

4. A method for synchronous data output, characterized in that: The method for synchronously outputting data is applied to the clock-free asynchronous circuit according to any one of claims 1 to 3, and the method for synchronously outputting data comprises the following steps: When an initial signal value is received through an input module in the conversion circuit, a first signal value to be operated is generated based on the input module, and the signal value to be operated is sent to an internal module of the conversion circuit for logic operation to obtain a first operation result; Outputting the first operation result to the output module of the conversion circuit, generating a second operation result based on the output module, and determining whether the second operation result meets a preset output condition; If the second operation result meets the preset output condition, the data is output synchronously.

5. The method for synchronously outputting data according to claim 4, characterized in that: After the step of determining whether the second operation result meets the preset output condition, the method further includes: If the second operation result does not meet the preset output condition, the data is not output.

6. The method for synchronously outputting data according to claim 4, characterized in that: After the step of outputting the first operation result to the output module of the conversion circuit, the method further includes: A confirmation signal is generated through the communication data line and sent to the input module.

7. A hardware interface device, characterized in that: The hardware interface device comprises a clock-free asynchronous circuit as described in any one of claims 1 to 3, a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the method for synchronous data output as described in any one of claims 4 to 6 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for synchronous data output according to any one of claims 4 to 6 are implemented.

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