Implementation Method, Device, Equipment and Medium of an Encryption and Decryption Algorithm

Abstract

The present invention discloses a method, apparatus, device and medium for implementing an encryption and decryption algorithm. The method includes: configuring an FPGA program library and a software encryption and decryption algorithm corresponding to the hardware encryption and decryption algorithm in the FPGA program library, and initializing and configuring the hardware encryption and decryption algorithms in each FPGA based on the FPGA program library; in response to receiving an encryption and decryption request, determining whether the target algorithm in the encryption and decryption request is the hardware encryption and decryption algorithm in the FPGA; selecting to implement the target algorithm by the corresponding FPGA based on the judgment result, or updating the algorithm in the corresponding FPGA and temporarily implementing the target algorithm by the corresponding software encryption and decryption algorithm when the algorithm in the FPGA is updated. Through the solution of the present invention, the efficiency loss caused by the inability of the FPGA to work during the switching of the encryption and decryption algorithms is compensated, and the computing efficiency of the encryption and decryption algorithm is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a method, device, equipment and medium for implementing encryption and decryption algorithms. Background Art

[0002] With the development of technology, especially the development of cloud computing and intelligence, the communication data between data centers and various devices not only shows an explosive growth in scale, but also the protection of sensitive information therein becomes increasingly important. And due to device limitations and different application fields, there are a variety of encryption and decryption algorithms for protecting sensitive information. Encryption and decryption of data are essentially mathematical calculations, which consume computing resources. From this perspective, the implementation of encryption and decryption can be divided into software implementation (i.e., by instructing to call the general computing resources on the CPU) and using the computing resources built by dedicated hardware circuits. Obviously, the software implementation method has relatively low efficiency and requires CPU resources, which will affect other work of the CPU when the encryption and decryption calculation amount is too large; while the dedicated hardware circuit method has obvious advantages in computing efficiency, but the problem is that it generally does not have universality, that is, it is difficult for the same set of hardware circuits to accelerate multiple encryption and decryption algorithms. Summary of the Invention

[0003] In view of this, the present invention proposes a method, device, equipment and medium for implementing encryption and decryption algorithms, which can implement a flexible configuration scheme for multiple encryption and decryption algorithms; and when the algorithm needs to be updated, it can realize the dynamic switching between the hardware encryption algorithm and the software encryption algorithm, and while downloading and updating the program in the corresponding FPGA, the software temporarily takes over its work, thereby effectively avoiding a significant reduction in efficiency caused by algorithm switching. Thus, while taking into account the universality and flexibility of the product, the efficiency of parallel execution of multiple encryption and decryption algorithms is improved.

[0004] Based on the above purpose, on the one hand, an embodiment of the present invention provides a method for implementing an encryption and decryption algorithm, which specifically includes the following steps:

[0005] Configure the FPGA program library and the software encryption and decryption algorithms corresponding to the hardware encryption and decryption algorithms in the FPGA program library, and initialize and configure the hardware encryption and decryption algorithms in each FPGA based on the FPGA program library;

[0006] In response to receiving the encryption and decryption request, determine whether the target algorithm in the encryption and decryption request is the hardware encryption and decryption algorithm in the FPGA;

[0007] Based on the judgment result, select to implement the target algorithm by the corresponding FPGA or update the algorithm in the corresponding FPGA, and when the algorithm in the FPGA is updated, temporarily implement the target algorithm by the corresponding software encryption and decryption algorithm.

[0008] In some embodiments, selecting to implement the target algorithm by the corresponding FPGA based on the judgment result, or updating the algorithm in the corresponding FPGA, and temporarily implementing the target algorithm by the corresponding software encryption and decryption algorithm when updating the algorithm in the FPGA includes:

[0009] In response to the target algorithm in the encryption and decryption request being the hardware encryption and decryption algorithm in the FPGA, implementing the target algorithm based on the corresponding FPGA;

[0010] In response to the target algorithm in the encryption and decryption request not being the hardware encryption and decryption algorithm in the FPGA, determining whether there is an unused FPGA within a first preset time;

[0011] In response to there being an unused FPGA within the first preset time, comparing the complexities of the hardware encryption and decryption algorithms in all the unused FPGAs, and obtaining the unused FPGA corresponding to the hardware encryption and decryption algorithm with the lowest complexity;

[0012] Temporarily implementing the target algorithm by the corresponding software encryption and decryption algorithm, and downloading the corresponding hardware encryption and decryption algorithm from the FPGA program library to update the corresponding unused FPGA;

[0013] After the download and update of the corresponding hardware encryption and decryption algorithm are completed, transferring the target algorithm to be implemented in the corresponding unused FPGA.

[0014] In some embodiments, after the step of determining whether there is an unused FPGA within a first preset time, the method further includes:

[0015] In response to there being no unused FPGA within the first preset time, comparing the complexity of the hardware encryption and decryption algorithm in all FPGAs with the complexity of the target algorithm;

[0016] In response to the complexity of the target algorithm being the lowest, implementing the target algorithm based on the corresponding software encryption and decryption algorithm;

[0017] In response to the complexity of the target algorithm not being the lowest, temporarily implementing the data encryption and decryption operation corresponding to the target algorithm by the corresponding software encryption and decryption algorithm, and downloading the corresponding hardware encryption and decryption algorithm from the FPGA program library to update the corresponding unused FPGA;

[0018] After the download and update of the corresponding hardware encryption and decryption algorithm are completed, transferring the target algorithm to be implemented in the corresponding unused FPGA.

[0019] In some embodiments, the method further includes:

[0020] Determine whether the running time of the software encryption algorithm exceeds a second preset time;

[0021] In response to the running time of the software encryption algorithm exceeding the second preset time, determine whether there is an unused FPGA within a third preset time;

[0022] In response to there being an unused FPGA within the third preset time, compare the complexity of the hardware encryption and decryption algorithms in all the unused FPGAs;

[0023] Update the hardware encryption and decryption algorithm with the lowest complexity in the corresponding FPGA to the hardware encryption and decryption algorithm corresponding to the software encryption algorithm whose running time exceeds the second preset time.

[0024] In some embodiments, the FPGA includes: a timing register configured to record the time when the FPGA last transmitted data to the CPU.

[0025] In some embodiments, the method further includes:

[0026] After the FPGA is reset or sends data to the CPU, set the value of the timing register corresponding to the FPGA to 0, and increment the value of the corresponding timing register by 1 in each clock cycle;

[0027] Determining whether there is an unused FPGA within a first preset time includes:

[0028] Determine whether the values of the timing registers of all FPGAs reach a threshold;

[0029] In response to the value of the timing register of the FPGA reaching the threshold, determine that the FPGA has not been used within the first preset time;

[0030] Determining whether there is an unused FPGA within a third preset time includes:

[0031] Periodically scan the timing registers of all FPGAs and determine whether the values of the timing registers of the FPGAs reach a threshold;

[0032] In response to the value of the timing register of the FPGA reaching the threshold, determine that the FPGA has not been used within the third preset time.

[0033] In some embodiments, configuring the FPGA library includes: configuring a local FPGA library and a cloud FPGA library;

[0034] Configuring a software encryption and decryption algorithm corresponding to the hardware encryption and decryption algorithm in the FPGA library includes: locally configuring the software encryption and decryption algorithm corresponding to the hardware encryption and decryption algorithm in the FPGA library.

[0035] Another aspect of the embodiments of the present invention further provides an apparatus for implementing an encryption and decryption algorithm, including:

[0036] A configuration module configured to configure an FPGA library and a software encryption and decryption algorithm corresponding to the hardware encryption and decryption algorithm in the FPGA library, and initialize and configure the hardware encryption and decryption algorithms in each FPGA based on the FPGA library;

[0037] A judgment module configured to, in response to receiving the encryption and decryption request, judge whether the target algorithm in the encryption and decryption request is the hardware encryption and decryption algorithm in the FPGA;

[0038] An implementation module configured to select, based on the judgment result, to implement the target algorithm by the corresponding FPGA or update the algorithm in the corresponding FPGA, and temporarily implement the target algorithm by the corresponding software encryption and decryption algorithm when the algorithm in the FPGA is updated.

[0039] Yet another aspect of the embodiments of the present invention further provides a computer device, including: at least one processor; and a memory storing a computer program that can run on the processor, and when the computer program is executed by the processor, the steps of the above method are implemented.

[0040] Still another aspect of the embodiments of the present invention further provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above method.

[0041] The present invention has at least the following beneficial technical effects: By configuring an FPGA library and a software encryption and decryption algorithm corresponding to the hardware encryption and decryption algorithm in the FPGA library, and initializing and configuring the hardware encryption and decryption algorithms in each FPGA based on the FPGA library; in response to receiving an encryption and decryption request, judging whether the target algorithm in the encryption and decryption request is the hardware encryption and decryption algorithm in the FPGA; based on the judgment result, selecting to implement the target algorithm by the corresponding FPGA or update the algorithm in the corresponding FPGA, and temporarily implementing the target algorithm by the corresponding software encryption and decryption algorithm when the algorithm in the FPGA is updated. Through the solution of the present invention, the efficiency loss caused by the inability of the FPGA to work during the switching of the encryption and decryption algorithms is compensated, and the computing efficiency of the encryption and decryption algorithms is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these drawings.

[0043] Figure 1 It is a flowchart of an embodiment of the implementation method of the encryption and decryption algorithm provided by the present invention;

[0044] Figure 2 It is a schematic structural diagram of an embodiment of the interconnection between the CPU and the FPGA provided by the present invention;

[0045] Figure 3 It is a schematic flowchart of another embodiment of the implementation method of an encryption and decryption algorithm provided by the present invention;

[0046] Figure 4 It is a schematic diagram of an embodiment of the implementation device of the encryption and decryption algorithm provided by the present invention;

[0047] Figure 5 It is a schematic structural diagram of an embodiment of the computer device provided by the present invention;

[0048] Figure 6 It is a schematic structural diagram of an embodiment of the computer-readable storage medium provided by the present invention. Detailed implementation manners

[0049] To make the objectives, technical solutions, and advantages of the present invention clearer, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0050] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities or parameters with the same name but different identities. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. This will not be elaborated further in the subsequent embodiments.

[0051] Based on the above objectives, in the first aspect of the embodiments of the present invention, an embodiment of the implementation method of an encryption and decryption algorithm is proposed. As Figure 1 shown, it includes the following steps:

[0052] S10. Configure the FPGA program library and the software encryption and decryption algorithm corresponding to the hardware encryption and decryption algorithm in the FPGA program library, and initialize and configure the hardware encryption and decryption algorithms in each FPGA based on the FPGA program library;

[0053] S20. In response to receiving the encryption / decryption request, determine whether the target algorithm in the encryption / decryption request is the hardware encryption / decryption algorithm in the FPGA;

[0054] S30. Based on the determination result, select to implement the target algorithm by the corresponding FPGA or update the algorithm in the corresponding FPGA, and when the algorithm in the FPGA is updated, temporarily implement the target algorithm by the corresponding software encryption / decryption algorithm.

[0055] In a specific embodiment, an FPGA (Field Programmable Gate Array) is a semi-custom circuit, a chip built using a large number of general-purpose basic computing units. By downloading a program file in a specific format (binary bitstream) to configure the basic computing units in the chip, a specific function is formed. The embodiments of the present invention implement multiple encryption / decryption algorithms based on the cooperation between the FPGA and software. By pre-downloading different programs in the FPGA, the acceleration of multiple encryption / decryption algorithms can be achieved without replacing the chip. Compared with a fully-customized chip designed specifically for a circuit, the FPGA is at a disadvantage in terms of area, power consumption, and performance, but it is much higher than the software calculation method.

[0056] Pre-download the programs of the encryption / decryption algorithms that may be encountered in various scenarios as comprehensively as possible in the FPGA. If it is necessary to switch to a scenario with different encryption / decryption requirements or the algorithm needs to be upgraded, re-download and update the program on the FPGA. If an algorithm not supported by the pre-downloaded program in the FPGA is encountered temporarily, use the software encryption / decryption algorithm for calculation, so as to achieve the compatibility and acceleration of multiple encryption / decryption algorithms, with good versatility and the ability to flexibly switch between multiple acceleration algorithms, improving the calculation efficiency of the encryption / decryption algorithms.

[0057] In this embodiment, the number of FPGAs is at least one. If there is only one FPGA, as many hardware encryption / decryption algorithms as possible need to be pre-downloaded into the FPGA. If there are multiple FPGAs, 1 to multiple hardware encryption / decryption programs (i.e., hardware encryption / decryption algorithms) can be pre-downloaded into each FPGA. Preferably, there are multiple FPGAs, and 1 hardware encryption / decryption program is pre-downloaded into each FPGA. On the one hand, this can enable multiple FPGAs to execute their respective encryption / decryption algorithms in parallel, improving the acceleration efficiency of the encryption / decryption algorithms. On the other hand, when the algorithm needs to be updated, only one FPGA can be selected, and the encryption / decryption algorithm being executed in this FPGA is transferred to the software for execution, that is, executed based on the corresponding software encryption / decryption algorithm at the software end, and the operation of other FPGAs is not affected, effectively avoiding a significant reduction in the calculation efficiency caused by algorithm switching.

[0058] The preferred solution is further described below.

[0059] As shown Figure 2 in the figure, it is a schematic diagram of the connection structure between the CPU and the FPGA. Multiple replaceable FPGAs are connected to the CPU through a multiplexer (MUX). Since each FPGA only needs to be able to accommodate one encryption and decryption algorithm, FPGAs with a relatively small logical capacity scale can be selected as much as possible to reduce costs. The data transmission between multiple FPGAs and the CPU is divided into two types: one is the encryption and decryption data; the other is the data for downloading and updating the FPGA program.

[0060] For the same FPGA, these two types of data will not be transmitted simultaneously (the FPGA cannot perform data encryption and decryption during program downloading and updating). Therefore, compared with the structure of a single FPGA, the data transmission bandwidth requirement between the CPU and the MUX will not increase significantly. Even if multiple FPGAs are connected downstream of the MUX, the upstream port can still reuse the FPGA accelerator port with the usual bandwidth (usually PCIe).

[0061] The automatic download and update process of the hardware encryption and decryption algorithm in the FPGA is as follows:

[0062] Configure the FPGA program library, automatically start the control program for specifying the FPGA program download and update, and after the FPGA completes the program download and update and resets and powers on (i.e., can work normally), send a feedback to the CPU. During this period, the hardware encryption and decryption algorithm in the FPGA being downloaded and updated is implemented by the corresponding software encryption and decryption algorithm.

[0063] In this embodiment, all encryption and decryption algorithms simultaneously require corresponding software implementation programs. Since the software programs are generally small in capacity, they can be placed locally.

[0064] This embodiment proposes a method for realizing the compatibility of multiple encryption and decryption algorithms based on fine-grained dynamic switching. Under a general software and hardware architecture, flexible configuration of multiple encryption and decryption algorithm solutions can be achieved by using different numbers of small-scale FPGAs. The limitation of hardware acceleration resources is solved by dynamically switching the encryption and decryption algorithms on the FPGA, and the efficiency loss caused by the inability to work during the hardware function switching is compensated by software and hardware coordination during the dynamic switching process. On the premise of considering product generality and flexibility, the efficiency of parallel execution of multiple encryption and decryption algorithms is improved.

[0065] In some embodiments, selecting to implement the target algorithm by the corresponding FPGA based on the judgment result or updating the algorithm in the corresponding FPGA and temporarily implementing the target algorithm by the corresponding software encryption and decryption algorithm when the algorithm in the FPGA is updated includes:

[0066] In response to the target algorithm in the encryption / decryption request being the hardware encryption / decryption algorithm in the FPGA, the target algorithm is implemented based on the corresponding FPGA;

[0067] In response to the target algorithm in the encryption / decryption request not being the hardware encryption / decryption algorithm in the FPGA, it is determined whether there is an unused FPGA within a first preset time;

[0068] In response to there being an unused FPGA within the first preset time, the complexities of the hardware encryption / decryption algorithms in all the unused FPGAs are compared, and the unused FPGA corresponding to the hardware encryption / decryption algorithm with the lowest complexity is obtained;

[0069] The target algorithm is temporarily implemented by the corresponding software encryption / decryption algorithm, and the corresponding hardware encryption / decryption algorithm is downloaded from the FPGA program library and updated to the corresponding unused FPGA;

[0070] After the download and update of the corresponding hardware encryption / decryption algorithm are completed, the target algorithm is transferred to the corresponding unused FPGA for implementation.

[0071] As Figure 3 shown, it is a schematic diagram of the implementation process of another encryption / decryption algorithm, specifically as follows:

[0072] Configure the FPGA program library and the corresponding software encryption / decryption algorithms for the hardware encryption / decryption algorithms in the FPGA program library, and initialize and configure the hardware encryption / decryption algorithms in each FPGA based on the FPGA program library;

[0073] Determine whether there is a requirement for the encryption / decryption function;

[0074] If there is a requirement for the encryption / decryption function, it is determined whether the target algorithm in this encryption / decryption function requirement is implemented in the FPGA;

[0075] If the target algorithm in this encryption / decryption function requirement is implemented in the FPGA, the target algorithm is implemented by the corresponding FPGA to complete the data encryption / decryption operation;

[0076] If the target algorithm in this encryption / decryption function requirement is not implemented in the FPGA, it is determined whether there is an unused FPGA recently (the first preset time, customized by the user according to the usage scenario);

[0077] If there is an unused FPGA recently, the complexities of the hardware encryption / decryption algorithms in all the unused FPGAs are compared, and the FPGA where the hardware encryption / decryption algorithm with the lowest complexity is located is obtained;

[0078] Temporarily implement the target algorithm with the corresponding software encryption and decryption algorithm, and download the corresponding hardware encryption and decryption algorithm from the FPGA program library to update the FPGA where the hardware encryption and decryption algorithm with the lowest complexity is obtained;

[0079] Determine whether the download update is completed;

[0080] If the download update is completed, transfer the target algorithm to the FPGA where the hardware encryption and decryption algorithm with the lowest complexity is implemented;

[0081] If the download update is not completed, return to the step of temporarily implementing the target algorithm with the corresponding software encryption and decryption algorithm to continue the download update.

[0082] Thus, a dynamic switching process triggered by the new encryption and decryption algorithm requirements is realized.

[0083] After the download update of the corresponding hardware encryption and decryption algorithm is completed, transfer the target algorithm to the corresponding unused FPGA for implementation.

[0084] In some embodiments, after the step of determining whether there is an unused FPGA within the first preset time, the method further includes:

[0085] In response to there being no unused FPGA within the first preset time, compare the complexity of the hardware encryption and decryption algorithms in all FPGAs with the complexity of the target algorithm;

[0086] In response to the complexity of the target algorithm being the lowest, implement the target algorithm based on the corresponding software encryption and decryption algorithm;

[0087] In response to the complexity of the target algorithm not being the lowest, temporarily implement the data encryption and decryption operations corresponding to the target algorithm with the corresponding software encryption and decryption algorithm, and download the corresponding hardware encryption and decryption algorithm from the FPGA program library to update the corresponding unused FPGA;

[0088] After the download update of the corresponding hardware encryption and decryption algorithm is completed, transfer the target algorithm to the corresponding unused FPGA for implementation.

[0089] Combined Figure 3 , continue to illustrate the dynamic switching process triggered by the new encryption and decryption algorithm requirements.

[0090] When determining whether there is a recently unused FPGA, if there is no recently unused FPGA, compare the complexity of the hardware encryption and decryption algorithms in all unused FPGAs and the complexity of the target algorithm;

[0091] Determine whether the complexity of the target algorithm is the lowest;

[0092] If the complexity of the target algorithm is the lowest, implement the target algorithm based on the corresponding software encryption and decryption algorithm;

[0093] If the complexity of the target algorithm is not the lowest, temporarily implement the target algorithm with the corresponding software encryption and decryption algorithm, and download the corresponding hardware encryption and decryption algorithm from the FPGA program library to update the FPGA where the hardware encryption and decryption algorithm with the lowest complexity is obtained;

[0094] Judge whether the download update is completed;

[0095] If the download update is completed, transfer the target algorithm to the FPGA where the hardware encryption and decryption algorithm with the lowest complexity is implemented;

[0096] If the download update is not completed, return to the step of temporarily implementing the target algorithm with the corresponding software encryption and decryption algorithm to continue the download update.

[0097] In some embodiments, the method further includes:

[0098] Judge whether the running time of the software encryption algorithm exceeds a second preset time;

[0099] In response to the running time of the software encryption algorithm exceeding the second preset time, judge whether there is an unused FPGA within a third preset time;

[0100] In response to there being an unused FPGA within the third preset time, compare the complexity of the hardware encryption and decryption algorithms in all the unused FPGAs;

[0101] Update the hardware encryption and decryption algorithm with the lowest complexity in the corresponding FPGA to the hardware encryption and decryption algorithm corresponding to the software encryption algorithm whose running time exceeds the second preset time.

[0102] As Figure 3 shown, the method further includes a dynamic switching process triggered by the long-term operation of the software encryption and decryption algorithm. Specifically as follows:

[0103] Judge whether the running time of a software encryption algorithm exceeds a second preset time;

[0104] If the running time of a software encryption algorithm exceeds the second preset time, judge whether there is an unused FPGA within a third preset time;

[0105] If there is an unused FPGA within the third preset time, compare the complexity of the hardware encryption and decryption algorithms in all the unused FPGAs;

[0106] Download and update the algorithm in the FPGA where the hardware encryption and decryption algorithm with the lowest complexity to the hardware encryption and decryption algorithm corresponding to the software encryption algorithm whose running time exceeds the second preset time.

[0107] Thus, a dynamic switching process triggered by the long-term operation of the software encryption and decryption algorithm is realized.

[0108] In some embodiments, the FPGA includes: a timing register configured to record the time when the FPGA last transmitted data to the CPU.

[0109] In some embodiments, the method further includes:

[0110] After the FPGA is reset or data is sent to the CPU, set the value of the timing register corresponding to the FPGA to 0, and increment the value of the corresponding timing register by 1 in each clock cycle;

[0111] Determining whether there is an unused FPGA within a first preset time includes:

[0112] Determining whether the values of the timing registers of all FPGAs reach a threshold;

[0113] In response to the value of the timing register of the FPGA reaching the threshold, it is determined that the FPGA has not been used within the first preset time;

[0114] Determining whether there is an unused FPGA within a third preset time includes:

[0115] Periodically scan the timing registers of all FPGAs and determine whether the values of the timing registers of the FPGAs reach the threshold;

[0116] In response to the value of the timing register of the FPGA reaching the threshold, it is determined that the FPGA has not been used within the third preset time.

[0117] Specifically, in this embodiment, the switching mechanism of the encryption and decryption algorithm based on the FPGA can be divided into two cases: one is that some of the algorithms in the current FPGA have not been used recently or have a very low usage frequency; the other is that all current algorithms are used in parallel.

[0118] For the judgment of the above two cases, a set of timing registers is set in each FPGA to record the time of the last data transmission to the CPU. Specifically, after the FPGA is reset, the initial value of the timing register is set to 0. After that, if the FPGA sends data to the CPU, the register is reset to 0 at the same time. Otherwise, the register value is incremented by 1 in each clock cycle until the maximum value of the register is reached, which can be considered as not being used recently. The maximum value of the register can be determined based on experience.

[0119] When a new encryption and decryption algorithm needs to be supported, the software will scan all FPGA timing registers. If no register reaches the maximum value, the complexity of all algorithms to be supported (including new requirements) will be judged, that is, the size of the corresponding hardware encryption and decryption program in the FPGA program library will be judged. The larger the program, the higher the complexity. Finally, the algorithm with high complexity will be retained in the FPGA for implementation, and the one with low complexity will be implemented by software for encryption and decryption. If a register is found to have reached the maximum value when scanning the timing register, the one with the lowest complexity will be selected from the FPGA algorithm that has reached the maximum value for replacement.

[0120] At the same time, in order to avoid the waste of FPGA resources, when there are algorithms that are encrypted and decrypted by software, all timing registers will be scanned regularly (this cycle should be greater than the maximum value of the timing register). If it is found that a register has reached the maximum value, the encryption and decryption algorithm implemented in the software will be replaced with the FPGA with the lowest current algorithm complexity. The length of the scanning cycle can be adjusted according to the actual situation. If the time is too long, the algorithm in the software will not be replaced in time. If the time is too short, the algorithm in use may be replaced, resulting in repeated replacements, both of which will affect efficiency. Based on the above process, when there are encryption and decryption algorithms that exceed the number of FPGAs that need to be supported at the same time, the algorithm with relatively high complexity will be downloaded and updated to the FPGA. Therefore, when evaluating whether the algorithm running the software needs to be replaced on the FPGA, you only need to consider whether the current FPGA has a very low usage frequency.

[0121] When the algorithm in the FPGA needs to be replaced, in order to avoid the long waiting time for the FPGA to download the program (the length of time depends on the complexity, generally tens of minutes to several hours) affecting the system efficiency, the software will start the encryption and decryption of the target algorithm at the same time as the FPGA download update is started. After the corresponding FPGA feedback can work normally, the encryption and decryption functions of the algorithm will be transferred to the FPGA.

[0122] Through this embodiment, a mechanism for FPGA to automatically download and update programs is implemented; and the FPGA usage time and FPGA algorithm program size are used as the basis for judging the future usage frequency and complexity of each algorithm on the FPGA, so that algorithms with high complexity can be implemented through hardware acceleration as much as possible. By taking advantage of the fact that software does not need to download programs for a long time like FPGA, while the FPGA automatically updates the algorithm, the software is used to temporarily replace it to perform encryption and decryption calculations, thereby compensating for the efficiency loss caused by the failure of the hardware function to work when switching, and improving the efficiency of multiple encryption and decryption algorithms in parallel while taking into account the versatility and flexibility of the product.

[0123] In some embodiments, configuring the FPGA library includes: configuring a local FPGA library and a cloud FPGA library;

[0124] Configuring the software encryption and decryption algorithms corresponding to the hardware encryption and decryption algorithms in the FPGA library includes: locally configuring the software encryption and decryption algorithms corresponding to the hardware encryption and decryption algorithms in the FPGA library.

[0125] Specifically, some classic algorithms in the encryption and decryption algorithms, such as MD5, AES, etc., will not be updated iteratively and are relatively simple. The binary data used to generate the FPGA program is not too large, and the usage frequency is relatively high. While some cutting-edge new algorithms, such as lattice cryptography, etc., the standards are still being updated and are relatively complex, and are only used in a few specific scenarios. Based on this, the FPGA library is divided into a local library and a cloud library. The FPGA programs of classic algorithms are placed in the local storage, and the FPGA programs of cutting-edge new algorithms are placed in the cloud and downloaded for use when needed.

[0126] In addition, all encryption and decryption algorithms require corresponding software implementation programs at the same time. However, the software programs are generally small in size, so all software encryption and decryption algorithms can be placed locally.

[0127] Based on the same inventive concept, according to another aspect of the present invention, as Figure 4 shown, an embodiment of the present invention further provides an implementation device for an encryption and decryption algorithm, including:

[0128] A configuration module 110, the configuration module 110 is configured to configure the FPGA library and the software encryption and decryption algorithms corresponding to the hardware encryption and decryption algorithms in the FPGA library, and initialize and configure the hardware encryption and decryption algorithms in each FPGA based on the FPGA library;

[0129] A judgment module 120, the judgment module 120 is configured to, in response to receiving the encryption and decryption request, judge whether the target algorithm in the encryption and decryption request is the hardware encryption and decryption algorithm in the FPGA;

[0130] An implementation module 130, the implementation module 130 is configured to select to implement the target algorithm by the corresponding FPGA based on the judgment result or update the algorithm in the corresponding FPGA, and temporarily implement the target algorithm by the corresponding software encryption and decryption algorithm when the algorithm in the FPGA is updated.

[0131] Based on the same inventive concept, according to another aspect of the present invention, as Figure 5As shown in the figure, an embodiment of the present invention further provides a computer device 30. In this computer device 30, a processor 310 and a memory 320 are included. The memory 320 stores a computer program 321 that can run on the processor. When the processor 310 executes the program, it executes the steps of the above method.

[0132] Among them, as a non-volatile computer-readable storage medium, the memory can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the implementation method of the encryption and decryption algorithm in the embodiments of the present application. By running the non-volatile software programs, instructions, and modules stored in the memory, the processor can execute various functional applications and data processing of the device, that is, implement the implementation method of the encryption and decryption algorithm in the above method embodiments.

[0133] The memory can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the device, etc. In addition, the memory can include high-speed random access memory, and can also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory optionally includes a memory remotely set relative to the processor, and these remote memories can be connected to the local module through a network. Examples of the above networks include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0134] Based on the same inventive concept, according to another aspect of the present invention, as Figure 6 shown in the figure, an embodiment of the present invention further provides a computer-readable storage medium 40. The computer-readable storage medium 40 stores a computer program 410 that, when executed by a processor, executes the above method.

[0135] Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes of implementing the above method embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. Among them, the storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc. The embodiments of the above computer program can achieve the same or similar effects as the corresponding foregoing method embodiments.

[0136] Those skilled in the art will also understand that the various exemplary logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, functions have been generally described for various illustrative components, blocks, modules, circuits, and steps. Whether this function is implemented as software or hardware depends on the particular application and the design constraints imposed on the overall system. The functions that can be implemented in various ways for each specific application by those skilled in the art, but such implementation decisions should not be construed as causing a departure from the scope of the disclosure of the embodiments of the present invention.

[0137] The above are exemplary embodiments of the disclosure of the present invention, but it should be noted that various changes and modifications can be made without departing from the scope of the disclosure of the embodiments of the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any particular order. The above serial numbers of the disclosed embodiments of the present invention are only for description and do not represent the superiority or inferiority of the embodiments. In addition, although the elements of the disclosed embodiments of the present invention can be described or claimed in individual form, they can also be understood as plural unless explicitly limited to the singular.

[0138] It should be understood that, as used herein, unless the context clearly supports exceptions, the singular form "a" is also intended to include the plural form. It should also be understood that the "and / or" used herein refers to any and all possible combinations of one or more of the associated listed items.

[0139] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features between the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for implementing an encryption and decryption algorithm, characterized in that Including: Configuring an FPGA program library and software encryption and decryption algorithms corresponding to the hardware encryption and decryption algorithms in the FPGA program library, and initializing and configuring the hardware encryption and decryption algorithms in each FPGA based on the FPGA program library; In response to receiving the encryption and decryption request, determining whether the target algorithm in the encryption and decryption request is the hardware encryption and decryption algorithm in the FPGA; In response to the target algorithm in the encryption and decryption request being the hardware encryption and decryption algorithm in the FPGA, implementing the target algorithm based on the corresponding FPGA; In response to the target algorithm in the encryption and decryption request not being the hardware encryption and decryption algorithm in the FPGA, determining whether there is an unused FPGA within a first preset time; In response to there being an unused FPGA within the first preset time, comparing the complexities of the hardware encryption and decryption algorithms in all the unused FPGAs, and obtaining the unused FPGA corresponding to the hardware encryption and decryption algorithm with the lowest complexity; Temporarily implementing the target algorithm by the corresponding software encryption and decryption algorithm, and downloading the corresponding hardware encryption and decryption algorithm from the FPGA program library to update the corresponding unused FPGA; After the download and update of the corresponding hardware encryption and decryption algorithm are completed, transferring the target algorithm to the corresponding unused FPGA for implementation.

2. The method according to claim 1, characterized in that, After the step of determining whether there is an unused FPGA within the first preset time, it further includes: In response to there being no unused FPGA within the first preset time, comparing the complexity of the hardware encryption and decryption algorithms in all FPGAs with the complexity of the target algorithm; In response to the complexity of the target algorithm being the lowest, implementing the target algorithm based on the corresponding software encryption and decryption algorithm; In response to the complexity of the target algorithm not being the lowest, temporarily implementing the data encryption and decryption operation corresponding to the target algorithm by the corresponding software encryption and decryption algorithm, and downloading the corresponding hardware encryption and decryption algorithm from the FPGA program library to update the FPGA where the hardware encryption and decryption algorithm with the lowest complexity is located; After the download and update of the corresponding hardware encryption and decryption algorithm are completed, transferring the target algorithm to the FPGA where the hardware encryption and decryption algorithm with the lowest complexity is located for implementation.

3. The method according to claim 1, wherein It further includes: Determining whether the running time of the software encryption and decryption algorithm exceeds a second preset time; In response to the running time of the software encryption and decryption algorithm exceeding the second preset time, determining whether there is an unused FPGA within a third preset time; In response to there being an unused FPGA within the third preset time, comparing the complexities of the hardware encryption and decryption algorithms in all the unused FPGAs; Updating the hardware encryption and decryption algorithm with the lowest complexity in the corresponding FPGA to the hardware encryption and decryption algorithm corresponding to the software encryption and decryption algorithm whose running time exceeds the second preset time.

4. The method according to claim 1, wherein The FPGA includes: a timing register configured to record the time when the FPGA last transmitted data to the CPU.

5. The method according to claim 4, wherein It further includes: After the FPGA is reset or data is sent to the CPU, the value of the timing register corresponding to the FPGA is set to 0, and the value of the corresponding timing register is incremented by 1 in each clock cycle; Determining whether there is an unused FPGA within a first preset time includes: Determining whether the values of the timing registers of all FPGAs reach a threshold; In response to the value of the timing register of the FPGA reaching the threshold, determining that the FPGA has not been used within the first preset time; Determining whether there is an unused FPGA within a third preset time includes: Periodically scanning the timing registers of all FPGAs and determining whether the values of the timing registers of the FPGAs reach the threshold; In response to the value of the timing register of the FPGA reaching the threshold, determining that the FPGA has not been used within the third preset time.

6. The method according to claim 1, characterized in that Configuring the FPGA program library includes: configuring the local FPGA program library and the cloud FPGA program library; Configuring the software encryption and decryption algorithms corresponding to the hardware encryption and decryption algorithms in the FPGA program library includes: locally configuring the software encryption and decryption algorithms corresponding to the hardware encryption and decryption algorithms in the FPGA program library.

7. An implementation device of an encryption and decryption algorithm, characterized in that, Includes: A configuration module configured to configure the FPGA program library and the software encryption and decryption algorithms corresponding to the hardware encryption and decryption algorithms in the FPGA program library, and initialize and configure the hardware encryption and decryption algorithms in each FPGA based on the FPGA program library; A judgment module configured to, in response to receiving the encryption and decryption request, judge whether the target algorithm in the encryption and decryption request is the hardware encryption and decryption algorithm in the FPGA; An implementation module configured to, in response to the target algorithm in the encryption and decryption request being the hardware encryption and decryption algorithm in the FPGA, implement the target algorithm based on the corresponding FPGA; in response to the target algorithm in the encryption and decryption request not being the hardware encryption and decryption algorithm in the FPGA, judge whether there is an unused FPGA within a first preset time; in response to there being an unused FPGA within the first preset time, compare the complexities of the hardware encryption and decryption algorithms in all the unused FPGAs, and obtain the unused FPGA corresponding to the hardware encryption and decryption algorithm with the lowest complexity; temporarily implement the target algorithm by the corresponding software encryption and decryption algorithm, and download the corresponding hardware encryption and decryption algorithm from the FPGA program library to update the corresponding unused FPGA; after the download and update of the corresponding hardware encryption and decryption algorithm are completed, transfer the target algorithm to the corresponding unused FPGA for implementation.

8. A computer device, comprising: At least one processor; And A memory storing a computer program that can run on the processor, wherein when the processor executes the program, it executes the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it executes the steps of the method according to any one of claims 1 to 6.

Images