A shift register, a display panel and a display device

Abstract

The present invention provides a shift register, a display panel and a display device, comprising a first input module, a second input module, a feedback adjustment module and an output module; the first input module is electrically connected to the first input signal terminal and the first clock signal terminal; the second input module is electrically connected to the second input signal terminal and the first clock signal terminal; the feedback adjustment module is electrically connected to the first clock signal terminal, the first node and the third node, and is used to transmit the signal of the first clock signal terminal to the third node under the control of the first node; the output module is electrically connected to the second clock signal terminal, the second node, the third node, the first voltage terminal and the output signal terminal, and is used to transmit the signal of the second clock signal terminal to the output signal terminal under the control of the second node, and transmit the signal of the first voltage terminal to the output signal terminal under the control of the third node. The present invention reduces the risk of competition risk in the shift register and improves the voltage resistance of the shift register.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a display panel and a display device. Background Art

[0002] At present, with the vigorous development of the display field, the cost requirements of display panels are getting lower and lower. How to effectively reduce the production cost of the panel is related to the competitiveness of the panel developer. In order to reduce the production cost of the display panel, relevant technicians will use the edge of the display panel to design a gate drive circuit. The gate drive circuit includes multiple gate shift registers. In the display stage, each row of gate shift registers controls the row of pixels for display. And each shift register is connected. When the upper-level shift register receives the signal and completes the shift, it will pass the output signal to the next-level shift register, thus realizing the function of line-by-line scanning. Such a design can save the placement of multiple gate drive chips in the edge area of ​​the display panel, and can realize the narrow border design of the display panel, while reducing the production cost of the display panel and improving the competitiveness of the product.

[0003] However, the shift register in the prior art has problems of contention risk and voltage tolerance. Summary of the invention

[0004] The present invention provides a shift register, a display panel and a display device, so as to reduce the risk of competition hazard in the shift register and improve the voltage resistance of the shift register.

[0005] In a first aspect, an embodiment of the present invention provides a shift register, comprising a first input module, a second input module, a feedback adjustment module and an output module;

[0006] The first input module is electrically connected to the first input signal terminal and the first clock signal terminal, and is used to transmit the signal of the first input signal terminal to the first node under the control of the first clock signal terminal;

[0007] The second input module is electrically connected to the second input signal terminal and the first clock signal terminal, and is used to transmit the signal of the second input signal terminal to the second node under the control of the first clock signal terminal;

[0008] The feedback adjustment module is electrically connected to the first clock signal terminal, the first node and the third node, and is used to transmit the signal of the first clock signal terminal to the third node under the control of the first node;

[0009] The output module is electrically connected to the second clock signal terminal, the second node, the third node, the first voltage terminal and the output signal terminal, and is used to transmit the signal of the second clock signal terminal to the output signal terminal under the control of the second node, and to transmit the signal of the first voltage terminal to the output signal terminal under the control of the third node.

[0010] In a second aspect, an embodiment of the present invention provides a display panel, comprising a plurality of cascaded shift registers as described in the first aspect;

[0011] Except for the last stage of the shift register, the output signal end of each of the remaining stages of the shift register is electrically connected to the second input signal end of the next stage of the shift register unit.

[0012] In a third aspect, an embodiment of the present invention provides a display device, comprising the display panel as described in the second aspect.

[0013] The embodiment of the present invention provides a shift register, which uses a first input module to control the input of a first node, and uses a second input module to control the input of a second node. That is, by using two different input modules to control the input of the first node and the second node respectively, the first node and the second node are separated, the first node and the second node are not connected, the first node and the second node do not interfere with each other, the voltage change of the first node does not affect (for example, pull down) the voltage of the second node, and the signal of the second clock signal end is not mistakenly transmitted to the output signal end under the control of the second node, and the peak spike does not occur, thereby reducing the risk of competition risk in the shift register. On the other hand, the first node and the second node are separated, and when the voltage of the second node changes (for example, is pulled down), it will not affect (for example, pull down) the voltage of the first node, so that the voltage transmitted to the third node will not be affected by the control of the first node, thereby improving the voltage resistance of the shift register. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the structure of a shift register provided by an embodiment of the present invention;

[0015] Figure 2 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0016] Figure 3 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0017] Figure 4 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0018] Figure 5 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0019] Figure 6 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0020] Figure 7 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0021] Figure 8 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0022] Fig. 9 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0023] Fig.10 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0024] Fig.11 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0025] Fig.12 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0026] Fig.13 A timing diagram of a shift register provided by an embodiment of the present invention;

[0027] Fig.14 A timing diagram of another shift register provided by an embodiment of the present invention;

[0028] Fig.15 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0029] Fig.16 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0031] Figure 1 A schematic diagram of a shift register structure provided by an embodiment of the present invention, referring to Figure 1, the shift register includes a first input module 11, a second input module 12, a feedback adjustment module 13 and an output module 14. The first input module 11 is electrically connected to the first input signal terminal IN1 and the first clock signal terminal CK, and the first input module 11 is used to transmit the signal of the first input signal terminal IN1 to the first node N1 under the control of the first clock signal terminal CK. The second input module 12 is electrically connected to the second input signal terminal IN2 and the first clock signal terminal CK, and the second input module 12 is used to transmit the signal of the second input signal terminal IN2 to the second node N2 under the control of the first clock signal terminal CK. The feedback adjustment module 13 is electrically connected to the first clock signal terminal CK, the first node N1 and the third node N3, and the feedback adjustment module 13 is used to transmit the signal of the first clock signal terminal CK to the third node N3 under the control of the first node N1. The feedback adjustment module 13 realizes the feedback of the first node N1 to the third node N3. The output module 14 is electrically connected to the second clock signal terminal XCK, the second node N2, the third node N3, the first voltage terminal VGH and the output signal terminal GOUT. The output module 14 is used to transmit the signal of the second clock signal terminal XCK to the output signal terminal GOUT under the control of the second node N2, and to transmit the signal of the first voltage terminal VGH to the output signal terminal GOUT under the control of the third node N3.

[0032] The embodiment of the present invention provides a shift register, which uses a first input module 11 to control the input of the first node N1, and uses a second input module 12 to control the input of the second node N2. That is, by using two different input modules to control the input of the first node N1 and the second node N2 respectively, the first node N1 and the second node N2 are separated, the first node N1 and the second node N2 are not connected, the first node N1 and the second node N2 do not interfere with each other, the voltage change of the first node N1 does not affect (for example, pull down) the voltage of the second node N2, and the signal of the second clock signal terminal XCK is not mistakenly transmitted to the output signal terminal GOUT under the control of the second node N2, and the peak spike does not occur, thereby reducing the risk of competition risk in the shift register. On the other hand, the first node N1 and the second node N2 are separated, and when the voltage of the second node N2 changes (for example, is pulled down), it will not affect (for example, pull down) the voltage of the first node N1, so that the voltage transmitted to the third node N3 will not be affected by the control of the first node N1, thereby improving the voltage resistance of the shift register.

[0033] For example, reference Figure 1 , opposite clock signals are applied to the first clock signal terminal CK and the second clock signal terminal XCK respectively. When the first clock signal terminal CK is a low voltage, the second clock signal terminal XCK is a high voltage; when the first clock signal terminal CK is a high voltage, the second clock signal terminal XCK is a low voltage.

[0034] Figure 2 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 2 ,,refer to Figure 2 The shift register further includes a first reset module 15. The first reset module 15 is electrically connected to the first clock signal terminal CK, the second voltage terminal VGL and the third node N3. The first reset module 15 is used to transmit the signal of the second voltage terminal VGL to the third node N3 under the control of the first clock signal terminal CK, and reset the third node N3.

[0035] For example, reference Figure 2 , the voltage of the first voltage terminal VGH is greater than the voltage of the second voltage terminal VGL, the voltage of the first voltage terminal VGH is a constant high voltage, and the voltage of the second voltage terminal VGL is a constant low voltage. When the first clock signal terminal CK is a low voltage, the low voltage of the second voltage terminal VGL is transmitted to the third node N3, setting the third node N3 to a low voltage, thereby resetting the third node N3.

[0036] Figure 3 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 3 The shift register further includes a second reset module 16. The second reset module 16 is electrically connected to the third node N3, the first voltage terminal VGH, the second clock signal terminal XCK and the second node N2. The second reset module 16 is used to transmit the signal of the first voltage terminal VGH to the second node N2 under the control of the third node N3 and the second clock signal terminal XCK.

[0037] For example, reference Figure 3 When the second clock signal terminal XCK is at a low voltage and the third node N3 is at a low voltage, the high voltage of the first voltage terminal VGH is transmitted to the second node N2, setting the second node N2 to a high voltage to achieve resetting of the second node N2.

[0038] Figure 4 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 4 The output module 14 includes a first transistor M1, a second transistor M2 and a first capacitor C1. The gate of the first transistor M1 is electrically connected to the third node N3, the first electrode of the first transistor M1 is electrically connected to the first voltage terminal VGH, and the second electrode of the first transistor M1 is electrically connected to the output signal terminal GOUT. The gate of the second transistor M2 is electrically connected to the second node N2, the first electrode of the second transistor M2 is electrically connected to the second clock signal terminal XCK, and the second electrode of the second transistor M2 is electrically connected to the output signal terminal GOUT. The first capacitor C1 is electrically connected to the third node N3, and the first capacitor C1 is used to stabilize the voltage of the third node N3.

[0039] For example, reference Figure 4 , taking the first transistor M1 and the second transistor M2 as P-type transistors as an example. When the third node N3 is a low voltage, the first transistor M1 is turned on, and the high voltage of the first voltage terminal VGH is transmitted to the output signal terminal GOUT. At this time, it is the non-enabled output stage of the shift register. When the second node N2 is a low voltage and the second clock signal terminal XCK is a low voltage, the second transistor M2 is turned on, and the low voltage of the second clock signal terminal XCK is transmitted to the output signal terminal GOUT. At this time, it is the enabled output stage of the shift register.

[0040] For example, reference Figure 4 , the first plate of the first capacitor C1 is electrically connected to the third node N3, and the second plate of the first capacitor C1 is electrically connected to the first voltage terminal VGH. The first capacitor C1 is used to stabilize the voltage of the third node N3, so that the third node N3 is maintained at a low voltage for a long period of time, and the first transistor M1 is turned on. The output signal terminal GOUT maintains a high voltage output for a long period of time. The output signal terminal GOUT maintains a low voltage output for a short period of time, and the second node N2 is maintained at a low voltage for a short time to turn on the second transistor M2. On the other hand, the second transistor M2 is used to output the enable output signal of the shift register, and the second transistor M2 is larger than the first transistor M1 and has better maintenance ability. Therefore, in one embodiment, a first capacitor C1 is provided for maintaining the voltage of the third node N3, and there is no need to provide a capacitor for maintaining the voltage of the second node N2.

[0041] Figure 5 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 5 The output module 14 further includes a second capacitor C2, which is electrically connected to the second node N2, and is used to stabilize the voltage of the second node N2.

[0042] For example, reference Figure 5 The first plate of the second capacitor C2 is electrically connected to the second node N2, and the second plate of the second capacitor C2 is electrically connected to the output signal terminal GOUT. The second capacitor C2 is used to stabilize the voltage of the second node N2, so that the second node N2 is maintained at a low voltage for a period of time, the second transistor M2 is turned on, and the output signal terminal GOUT maintains a low voltage output, thereby improving the output stability of the shift register.

[0043] Figure 6 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 6The first input module 11 includes a third transistor M3. A gate of the third transistor M3 is electrically connected to the first clock signal terminal CK, a first electrode of the third transistor M3 is electrically connected to the first input signal terminal IN1, and a second electrode of the third transistor M3 is electrically connected to the first node N1.

[0044] For example, reference Figure 6 , taking the third transistor M3 as a P-type transistor as an example, when the first clock signal terminal CK is at a low voltage, the third transistor M3 is turned on, and the signal of the first input signal terminal IN1 is transmitted to the first node N1.

[0045] Figure 7 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 7 The second input module 12 includes a fourth transistor M4. A gate of the fourth transistor M4 is electrically connected to the first clock signal terminal CK, a first electrode of the fourth transistor M4 is electrically connected to the second input signal terminal IN2, and a second electrode of the fourth transistor M4 is electrically connected to the second node N2.

[0046] For example, reference Figure 7 , taking the fourth transistor M4 as a P-type transistor as an example, when the first clock signal terminal CK is at a low voltage, the fourth transistor M4 is turned on, and the signal of the second input signal terminal IN2 is transmitted to the second node N2.

[0047] Figure 8 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 8 The feedback regulation module 13 includes a fifth transistor M5 and a third capacitor C3. The gate of the fifth transistor M5 is electrically connected to the first node N1, the first electrode of the fifth transistor M5 is electrically connected to the first clock signal terminal CK, and the second electrode of the fifth transistor M5 is electrically connected to the third node N3. The third capacitor C3 is electrically connected to the first node N1 and is used to stabilize the voltage of the first node N1.

[0048] For example, reference Figure 8 , taking the fifth transistor M5 as a P-type transistor as an example. When the first node N1 is at a low voltage, the fifth transistor M5 is turned on, and the signal of the first clock signal terminal CK is transmitted to the third node N3, realizing the feedback of the first node N1 to the third node N3. Among them, the first plate of the third capacitor C3 is electrically connected to the first node N1, and the second plate of the third capacitor C3 is electrically connected to the first voltage terminal VGH. The third capacitor C3 is used to stabilize the voltage of the first node N1, so that the first node N1 is maintained at a low voltage for a long period of time, the fifth transistor M5 is turned on, and the signal of the first clock signal terminal CK is transmitted to the third node N3.

[0049] Fig. 9A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Fig. 9 The first reset module 15 includes a sixth transistor M6. A gate of the sixth transistor M6 is electrically connected to the first clock signal terminal CK, a first electrode of the sixth transistor M6 is electrically connected to the second voltage terminal VGL, and a second electrode of the sixth transistor M6 is electrically connected to the third node N3.

[0050] For example, reference Fig. 9 When the first clock signal terminal CK is at a low voltage, the sixth transistor M6 is turned on, and the low voltage of the second voltage terminal VGL is transmitted to the third node N3, setting the third node N3 to a low voltage, thereby resetting the third node N3.

[0051] Fig.10 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Fig.10 The second reset module 16 includes a seventh transistor M7 and an eighth transistor M8. The gate of the seventh transistor M7 is electrically connected to the second clock signal terminal XCK, the first electrode of the seventh transistor M7 is electrically connected to the second node N2, and the second electrode of the seventh transistor M7 is electrically connected to the first electrode of the eighth transistor M8. The gate of the eighth transistor M8 is electrically connected to the third node N3, and the second electrode of the eighth transistor M8 is electrically connected to the first voltage terminal VGH.

[0052] For example, reference Fig.10 , taking the seventh transistor M7 and the eighth transistor M8 as P-type transistors as an example, when the second clock signal terminal XCK is at a low voltage and the third node N3 is at a low voltage, the seventh transistor M7 and the eighth transistor M8 are both turned on, and the high voltage of the first voltage terminal VGH is transmitted to the second node N2, setting the second node N2 to a high voltage, thereby resetting the second node N2.

[0053] Fig.11 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Fig.11 , the shift register further includes a ninth transistor M9. The gate of the ninth transistor M9 is electrically connected to the second voltage terminal VGL, the first electrode of the ninth transistor M9 is electrically connected to the second input module 12, the second electrode of the ninth transistor M9 is electrically connected to the second node N2, and the ninth transistor M9, under the control of the second voltage terminal VGL, connects the second input module 12 to the second node N2. It can be understood that, Fig.10 As shown, without setting the ninth transistor M9, the second input module 12, the second reset module 16 and the output module 14 are all connected to the second node N2, and the number of modules directly connected to the second node N2 is three; Fig.11As shown, by connecting the ninth transistor M9 to the second node N2 in the second input module 12, the ninth transistor M9 and the output module 14 are connected to the second node N2, and the number of modules directly connected to the second node N2 is two, thereby reducing the number of modules directly connected to the second node N2, improving the voltage stability of the second node N2, and improving the circuit stability of the shift register.

[0054] For example, reference Fig.11 Taking the ninth transistor M9 as a P-type transistor as an example, the ninth transistor M9 is always turned on under the control of the second voltage terminal VGL, connecting the second input module 12 and the second node N2 to be turned on.

[0055] For example, reference Fig.11 , the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are all P-type transistors. In other embodiments, at least one of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 may also be an N-type transistor.

[0056] Fig.12 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Fig.12 , the first input signal terminal IN1 is electrically connected to the second input signal terminal IN2. The first input signal terminal IN1 and the second input signal terminal IN2 have voltage signals with the same timing, so there is no need to provide driving signals to the first input signal terminal IN1 and the second input signal terminal IN2 respectively, which simplifies the driving timing of the shift register and reduces the driving difficulty of the shift register.

[0057] Fig.13 A timing diagram of a shift register provided by an embodiment of the present invention, combined with reference to Fig.12 and Fig.13, in the first stage P1, the first input signal terminal IN1 and the second input signal terminal IN2 are low voltages, the first clock signal terminal CK is low voltage, and the second clock signal terminal XCK is high voltage. The third transistor M3 is turned on, the first node N1 is low voltage, and the fifth transistor M5 is turned on. The sixth transistor M6 is turned on, the third node N3 is low voltage, the first transistor M1 and the eighth transistor M8 are turned on, and the high voltage signal of the first voltage terminal VGH is transmitted to the output signal terminal GOUT. The fourth transistor M4 is turned on, the second node N2 is low voltage, and the second transistor M2 is turned on. The seventh transistor M7 is turned off. In the second stage P2, the first input signal terminal IN1 and the second input signal terminal IN2 are high voltages, the first clock signal terminal CK is high voltage, and the second clock signal terminal XCK is low voltage. The third transistor M3, the fourth transistor M4 and the sixth transistor M6 are turned off. The first node N1 maintains a low voltage, the fifth transistor M5 is turned on, the high voltage of the first clock signal terminal CK is transmitted to the third node N3, the third node N3 is changed from a low voltage to a high voltage, and the first transistor M1 and the eighth transistor M8 are turned off. The second node N2 maintains a low voltage, the second transistor M2 is turned on, and the low voltage signal of the second clock signal terminal XCK is transmitted to the output signal terminal GOUT. The seventh transistor M7 is turned on. In the third stage P3, the first input signal terminal IN1 and the second input signal terminal IN2 are high voltages, the first clock signal terminal CK is a low voltage, and the second clock signal terminal XCK is a high voltage. The third transistor M3 is turned on, the high voltage of the first input signal terminal IN1 is transmitted to the first node N1, the first node N1 is changed from a low voltage to a high voltage, and the fifth transistor M5 is turned off. The fourth transistor M4 is turned on, the high voltage of the second input signal terminal IN2 is transmitted to the second node N2, the second node N2 is changed from a low voltage to a high voltage, and the second transistor M2 is turned off. The sixth transistor M6 is turned on, the third node N3 maintains a low voltage, the first transistor M1 and the eighth transistor M8 are turned on, and the high voltage signal of the first voltage terminal VGH is transmitted to the output signal terminal GOUT. The seventh transistor M7 is turned off. In the fourth stage P4, the first input signal terminal IN1 and the second input signal terminal IN2 are high voltages, the first clock signal terminal CK is high voltage, and the second clock signal terminal XCK is low voltage. The third transistor M3, the fourth transistor M4 and the sixth transistor M6 are turned off. The first node N1 maintains a high voltage, and the fifth transistor M5 is turned off. The third node N3 maintains a low voltage, the first transistor M1 and the eighth transistor M8 are turned on, and the high voltage signal of the first voltage terminal VGH is transmitted to the output signal terminal GOUT. The second node N2 maintains a high voltage, and the second transistor M2 is turned off. The seventh transistor M7 is turned on. In the fifth stage P5, the first input signal terminal IN1 and the second input signal terminal IN2 are high voltages, the first clock signal terminal CK is low voltage, and the second clock signal terminal XCK is high voltage. The third transistor M3 is turned on, the first node N1 maintains a high voltage, and the fifth transistor M5 is turned off.The fourth transistor M4 is turned on, the second node N2 maintains a high voltage, and the second transistor M2 is turned off. The sixth transistor M6 is turned on, the third node N3 maintains a low voltage, the eighth transistor M8 and the first transistor M1 are turned on, and the high voltage signal of the first voltage terminal VGH is transmitted to the output signal terminal GOUT. The seventh transistor M7 is turned off.

[0058] In other implementations, signals with the same timing change (ie, the timing of high and low voltage transitions) but different voltage values ​​may be provided to the first input signal terminal IN1 and the second input signal terminal IN2.

[0059] Fig.14 A timing diagram of a shift register provided by an embodiment of the present invention, combined with reference to Fig.10 and Fig.14 , the voltage of the first input signal terminal IN1 and the second input signal terminal IN2 jumps at the same time, from a low voltage to a high voltage or from a high voltage to a low voltage. The signal of the first input signal terminal IN1 applied to the first node N1 is used to transmit the signal of the first clock signal terminal CK to the third node N3. Therefore, the voltage value of the first input signal terminal IN1 can be set to be greater than the voltage value of the second input signal terminal IN2, so that the signal of the first input signal terminal IN1 applied to the first node N1 does not need to be particularly low, thereby reducing the power consumption of the shift register and improving the stability of the shift register.

[0060] Fig.15 A schematic diagram of a display panel provided by an embodiment of the present invention, Fig.15 The gate driving circuit including a plurality of shift registers is schematically shown, and other known structures in the display panel except the gate driving circuit are omitted, such as gate lines, data lines, pixel driving circuits and light-emitting units. Fig.15 The display panel includes a plurality of cascaded shift registers. Except for the last shift register, the output signal terminal GOUT of each shift register of the remaining stages is electrically connected to the second input signal terminal IN2 of the next shift register unit.

[0061] In the display panel provided by the embodiment of the present invention, in each level of shift register, the first input module 11 is used to control the input of the first node N1, and the second input module 12 is used to control the input of the second node N2. That is to say, by adopting two different input modules, the inputs of the first node N1 and the second node N2 are respectively controlled, so that the first node N1 and the second node N2 are separated, the first node N1 and the second node N2 are not connected, and the first node N1 and the second node N2 do not interfere with each other, so as to reduce the risk of competition hazard in the shift register and improve the voltage resistance of the shift register.

[0062] For example, reference Fig.15If the first input signal terminal IN1 is electrically connected to the second input signal terminal IN2, except for the last shift register, the output signal terminal GOUT of each shift register is electrically connected to the first input signal terminal IN1 and the second input signal terminal IN2 of the next shift register unit.

[0063] For example, reference Fig.15 For the first stage shift register, the second input signal terminal IN2 may be electrically connected to the initialization signal terminal STV, and the initialization signal terminal STV provides a signal to the second input signal terminal IN2.

[0064] For example, reference Fig.15 The display panel may further include a first clock signal line CLK1 and a second clock signal line CLK2, the first clock signal terminal CK of each stage of the shift register is electrically connected to the first clock signal line CLK1, and the second clock signal terminal XCK of each stage of the shift register is electrically connected to the second clock signal line CLK2.

[0065] An embodiment of the present invention further provides a display device. Fig.16 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig.16 The display device includes any one of the display panels provided in the embodiments of the present invention. The display device may specifically be a mobile phone, a tablet computer, a smart wearable device, and the like.

[0066] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A shift register, characterized in that: It includes a first input module, a second input module, a feedback adjustment module and an output module; The first input module is electrically connected to the first input signal terminal and the first clock signal terminal, and is used to transmit the signal of the first input signal terminal to the first node under the control of the first clock signal terminal; The second input module is electrically connected to the second input signal terminal and the first clock signal terminal, and is used to transmit the signal of the second input signal terminal to the second node under the control of the first clock signal terminal; The feedback adjustment module is electrically connected to the first clock signal terminal, the first node and the third node, and is used to transmit the signal of the first clock signal terminal to the third node under the control of the first node; The output module is electrically connected to the second clock signal terminal, the second node, the third node, the first voltage terminal and the output signal terminal, and is used to transmit the signal of the second clock signal terminal to the output signal terminal under the control of the second node, and transmit the signal of the first voltage terminal to the output signal terminal under the control of the third node; The timing changes of the first input signal terminal and the second input signal terminal are the same.

2. The shift register according to claim 1, characterized in that: It also includes a first reset module, which is electrically connected to the first clock signal terminal, the second voltage terminal and the third node, and is used to transmit the signal of the second voltage terminal to the third node under the control of the first clock signal terminal.

3. The shift register according to claim 1, wherein: It also includes a second reset module, which is electrically connected to the third node, the first voltage terminal, the second clock signal terminal and the second node, and is used to transmit the signal of the first voltage terminal to the second node under the control of the third node and the second clock signal terminal.

4. The shift register according to claim 1, wherein: The output module includes a first transistor, a second transistor and a first capacitor; The gate of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the output signal terminal; The gate of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the second clock signal terminal, and the second electrode of the second transistor is electrically connected to the output signal terminal; The first capacitor is electrically connected to the third node and is used to stabilize the voltage of the third node.

5. The shift register according to claim 4, characterized in that: The output module further includes a second capacitor, which is electrically connected to the second node and is used to stabilize the voltage of the second node.

6. The shift register according to claim 1, characterized in that: The first input module includes a third transistor, a gate of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the first input signal terminal, and a second electrode of the third transistor is electrically connected to the first node.

7. The shift register according to claim 1, characterized in that: The second input module includes a fourth transistor, a gate of the fourth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourth transistor is electrically connected to the second input signal terminal, and a second electrode of the fourth transistor is electrically connected to the second node.

8. The shift register according to claim 1, characterized in that: The feedback regulation module includes a fifth transistor and a third capacitor; The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the third node; The third capacitor is electrically connected to the first node and is used to stabilize the voltage of the first node.

9. The shift register according to claim 2, characterized in that: The first reset module includes a sixth transistor, a gate of the sixth transistor is electrically connected to the first clock signal terminal, a first electrode of the sixth transistor is electrically connected to the second voltage terminal, and a second electrode of the sixth transistor is electrically connected to the third node.

10. The shift register according to claim 3, characterized in that: The second reset module includes a seventh transistor and an eighth transistor, the gate of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; A gate of the eighth transistor is electrically connected to the third node, and a second electrode of the eighth transistor is electrically connected to the first voltage terminal.

11. The shift register according to claim 1, characterized in that: It also includes a ninth transistor, a gate of the ninth transistor is electrically connected to the second voltage terminal, a first electrode of the ninth transistor is electrically connected to the second input module, a second electrode of the ninth transistor is electrically connected to the second node, and under the control of the second voltage terminal, the ninth transistor connects the second input module to the second node for conduction.

12. The shift register according to claim 1, characterized in that: The first input signal terminal is electrically connected to the second input signal terminal.

13. The shift register according to claim 1, characterized in that: The voltage value of the first input signal terminal is greater than the voltage value of the second input signal terminal.

14. A display panel, characterized in that: A plurality of shift registers according to any one of claims 1 to 13 connected in cascade; Except for the last stage of the shift register, the output signal end of each of the remaining stages of the shift register is electrically connected to the second input signal end of the next stage of the shift register unit.

15. A display device, characterized in that: Comprising the display panel as claimed in claim 14.

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