A trench transistor processing method for a wafer
By forming silicon nitride sidewalls on the wafer to limit trench openings and providing contact hole insulation protection, the problem of high-precision equipment requirements is solved, and high-quality wafer processing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-07
- Publication Date
- 2026-04-14
AI Technical Summary
In existing technologies, high-precision equipment is required during wafer processing to ensure etching accuracy, resulting in high equipment costs and significant technical challenges.
By forming silicon nitride sidewalls on the wafer, the trench opening size is limited, and insulation protection is provided during contact hole etching, preventing metal from contacting polysilicon and reducing equipment accuracy requirements.
This reduces the precision requirements of etching equipment, avoids conductivity problems caused by positional deviations, and ensures wafer processing quality.
Smart Images
Figure CN115064436B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of wafer fabrication technology, specifically a method for fabricating trench transistors on wafers. Background Technology
[0002] A wafer is a silicon wafer used to make silicon semiconductor circuits. Its raw material is silicon. High-purity polycrystalline silicon is dissolved and mixed with silicon crystal seeds, and then slowly pulled out to form a cylindrical single-crystal silicon.
[0003] In existing technologies, during the wafer fabrication process, if the position of the contact holes is deviated when etching contact holes on the wafer, it will cause the metal to come into contact with the single crystal silicon when filling the contact holes, resulting in conductivity and affecting the use of the wafer. This means that high-precision processing equipment must be used to ensure the etching accuracy during wafer processing. However, using high-precision processing equipment not only presents technical challenges, but also increases the cost of manufacturing such equipment. Summary of the Invention
[0004] To address the shortcomings mentioned in the background section, the present invention aims to provide a trench transistor fabrication method for wafers, thereby solving the problem that high-precision processing equipment must be used to ensure etching accuracy during wafer fabrication.
[0005] The objective of this invention can be achieved through the following technical solutions:
[0006] A method for fabricating trench transistors for wafers includes the following steps:
[0007] S1. A silicon nitride deposition layer is formed on the wafer with silicon oxide on the back side using chemical vapor deposition. Then the wafer is etched to remove the silicon nitride deposition layer on the wafer, so that the silicon nitride deposition layer forms sidewalls on both sides of the silicon oxide. Finally, the position between the sidewalls on the top of the wafer is etched to form a trench on the top of the wafer.
[0008] S2. The wafer obtained in step S1 is oxidized to form a gate silicon oxide layer on the back side of the wafer and the inner wall of the trench. Then the back side of the wafer is etched to remove the gate silicon oxide layer on the back side of the wafer and the trench. Finally, ion implantation is performed on the back side of the wafer using the ion implantation method.
[0009] S3. The inner wall of the wafer trench obtained in step S2 is oxidized separately to form a dense gate silicon oxide layer on the inner wall of the trench.
[0010] S4. For the wafer obtained in step S3, a layer of polysilicon is formed on the back side of the wafer and inside the trench using chemical vapor deposition, and then the top of the polysilicon on the back side of the wafer is planarized using CMP process.
[0011] S5. The back side of the wafer obtained in step S4 is etched to remove the polysilicon located on the back side of the wafer, and then a layer of silicon oxynitride is deposited on the back side of the wafer using chemical vapor deposition.
[0012] S6. For the wafer obtained in step S5, a silicon oxide layer is deposited on top of silicon oxynitride using chemical vapor deposition, and then the top of the silicon oxide layer is planarized using CMP process.
[0013] S7. For the wafer obtained in step S6, etching is performed on the silicon oxide layer to the silicon oxynitride surface, and then the silicon oxynitride, silicon oxide and the top of the wafer below the opening of the silicon oxide layer are etched away in sequence to form a contact hole on the top of the wafer.
[0014] S8. In step S7, the bottom of the contact hole formed at the top of the wafer is implanted with ion implantation, and then metal is filled into the contact hole.
[0015] In steps S2 and S3, both the oxidation of the wafer and the oxidation of the inner wall of the trench are carried out in an oxidation furnace.
[0016] In step S2, the back side of the wafer is etched. When the gate silicon oxide layer on the back side of the wafer is etched away, a portion of the top of the silicon oxide on the back side of the wafer is also etched away.
[0017] In step S8, when etching is performed above the silicon oxide layer on the back of the wafer, the wafer needs to be developed. The steps are as follows: first, a layer of photoresist is coated on the surface of the wafer, then light exposure is performed to form a pattern on the surface of the wafer that is partially exposed and partially unexposed. After development, the unexposed areas are covered by the photoresist.
[0018] In steps S1, S4 and S8, the sidewall formed in step S1 is located between the metal and the polysilicon to avoid electrical conductivity between the metal and the polysilicon.
[0019] In steps S4 and S5, the polysilicon deposited by chemical vapor deposition is polysilicon containing impurities, so as to form transistors at the trench locations of the wafer.
[0020] In step S8, the ions implanted at the bottom of the contact hole and the ions implanted in step S2 form an electrode on the back side of the wafer.
[0021] Step S1 can also first perform ion implantation on the back side of the wafer using ion implantation method, then form a silicon nitride deposition layer using chemical vapor deposition method, then etch the wafer to remove the silicon nitride deposition layer on the wafer, so that the silicon nitride deposition layer forms sidewalls on both sides of silicon oxide, and finally etch the position between the sidewalls on the top of the wafer to form a trench on the top of the wafer.
[0022] In step S2, the wafer obtained in step S1 can be oxidized first to form a gate silicon oxide layer on the back side of the wafer and the inner wall of the trench, and then the back side of the wafer can be etched to remove the gate silicon oxide layer on the back side of the wafer and the trench.
[0023] The beneficial effects of this invention are:
[0024] 1. By etching silicon nitride to form sidewalls on the wafer, the size of the trench opening on the wafer can be limited by the sidewalls when making transistors through the etched trenches. This avoids the trench opening being too large due to insufficient precision of the etching equipment, and reduces the precision requirements of the equipment used when etching trenches.
[0025] Second, by creating contact holes on the wafer, the sidewalls can provide insulation protection between the contact holes and the polysilicon in the trenches. This prevents the contact holes from contacting the polysilicon even if there is a deviation in the position of the contact holes when they are directly created. This avoids the metal and polysilicon becoming conductive when the contact holes are filled with metal due to the position deviation of the contact holes. This reduces the precision requirements of the equipment when creating transistors and metals on the back of the wafer. Even if there is a deviation in the etching position, it will not affect the wafer manufacturing. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a flowchart illustrating step S1 in Embodiment 1 of the present invention;
[0028] Figure 2 This is a flowchart illustrating step S2 in Embodiment 1 of the present invention;
[0029] Figure 3 This is a flowchart illustrating step S3 in Embodiment 1 of the present invention;
[0030] Figure 4 This is a flowchart illustrating step S4 in Embodiment 1 of the present invention;
[0031] Figure 5 This is a flowchart illustrating step S5 in Embodiment 1 of the present invention;
[0032] Figure 6 This is a flowchart illustrating step S6 in Embodiment 1 of the present invention;
[0033] Figure 7 This is a flowchart illustrating step S7 in Embodiment 1 of the present invention;
[0034] Figure 8 This is a flowchart illustrating step S8 in Embodiment 1 of the present invention;
[0035] Figure 9 yes Figure 8 Enlarged view of point A in the middle;
[0036] Figure 10 This is a schematic diagram of the wafer state without sidewalls when filling the contact hole with metal in step S8 of embodiment 1 of the present invention;
[0037] Figure 11 This is a flowchart illustrating step S1 in Embodiment 2 of the present invention;
[0038] Figure 12 This is a flowchart illustrating step S2 in Embodiment 2 of the present invention. Detailed Implementation
[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0040] Example 1
[0041] A method for fabricating trench transistors for wafers includes the following steps:
[0042] S1. A silicon nitride deposition layer is formed on the wafer with silicon oxide on the back side using chemical vapor deposition. Then the wafer is etched to remove the silicon nitride deposition layer on the wafer, so that the silicon nitride deposition layer forms sidewalls on both sides of the silicon oxide. Finally, the position between the sidewalls on the top of the wafer is etched to form a trench on the top of the wafer.
[0043] S2. The wafer obtained in step S1 is oxidized to form a gate silicon oxide layer on the back side of the wafer and the inner wall of the trench. Then the back side of the wafer is etched to remove the gate silicon oxide layer on the back side of the wafer and the trench. Finally, ion implantation is performed on the back side of the wafer using the ion implantation method.
[0044] S3. The inner wall of the wafer trench obtained in step S2 is oxidized separately to form a dense gate silicon oxide layer on the inner wall of the trench.
[0045] S4. For the wafer obtained in step S3, a layer of polysilicon is formed on the back side of the wafer and inside the trench using chemical vapor deposition, and then the top of the polysilicon on the back side of the wafer is planarized using CMP process.
[0046] S5. The back side of the wafer obtained in step S4 is etched to remove the polysilicon located on the back side of the wafer, and then a layer of silicon oxynitride is deposited on the back side of the wafer using chemical vapor deposition.
[0047] S6. For the wafer obtained in step S5, a silicon oxide layer is deposited on top of silicon oxynitride using chemical vapor deposition, and then the top of the silicon oxide layer is planarized using CMP process.
[0048] S7. For the wafer obtained in step S6, etching is performed on the silicon oxide layer to the silicon oxynitride surface, and then the silicon oxynitride, silicon oxide and the top of the wafer below the opening of the silicon oxide layer are etched away in sequence to form a contact hole on the top of the wafer.
[0049] S8. In step S7, the bottom of the contact hole formed at the top of the wafer is implanted with ion implantation, and then metal is filled into the contact hole.
[0050] Example 2
[0051] A method for fabricating trench transistors for wafers includes the following steps:
[0052] S1. First, ion implantation is performed on the back side of the wafer using the ion implantation method. Then, a silicon nitride deposition layer is formed using chemical vapor deposition. Next, the wafer is etched to remove the silicon nitride deposition layer on the wafer, so that the silicon nitride deposition layer forms sidewalls on both sides of the silicon oxide. Finally, the position between the sidewalls on the top of the wafer is etched to form a trench on the top of the wafer.
[0053] S2. First, oxidize the wafer obtained in step S1 to form a gate silicon oxide layer on the back side of the wafer and the inner wall of the trench. Then, etch the back side of the wafer to remove the gate silicon oxide layer on the back side of the wafer and the trench.
[0054] S3. The inner wall of the wafer trench obtained in step S2 is oxidized separately to form a dense gate silicon oxide layer on the inner wall of the trench.
[0055] S4. For the wafer obtained in step S3, a layer of polysilicon is formed on the back side of the wafer and inside the trench using chemical vapor deposition, and then the top of the polysilicon on the back side of the wafer is planarized using CMP process.
[0056] S5. The back side of the wafer obtained in step S4 is etched to remove the polysilicon located on the back side of the wafer, and then a layer of silicon oxynitride is deposited on the back side of the wafer using chemical vapor deposition.
[0057] S6. For the wafer obtained in step S5, a silicon oxide layer is deposited on top of silicon oxynitride using chemical vapor deposition, and then the top of the silicon oxide layer is planarized using CMP process.
[0058] S7. For the wafer obtained in step S6, etching is performed on the silicon oxide layer to the silicon oxynitride surface, and then the silicon oxynitride, silicon oxide and the top of the wafer below the opening of the silicon oxide layer are etched away in sequence to form a contact hole on the top of the wafer.
[0059] S8. In step S7, ion implantation is performed on the bottom of the contact hole formed at the top of the wafer using an ion implantation method, and then metal is filled into the contact hole.
[0060] The working principle of the trench transistor fabrication method for wafers provided by this invention is as follows:
[0061] like Figure 1 In step S1, sidewalls are formed on both sides of silicon oxide, so that the sidewalls on both sides will protect the opening position in the etched trench on the wafer surface, so that the trench opening position can only be between the two sidewalls, and the maximum length of the formed trench opening can only be between the two sidewalls, thus avoiding the trench opening etched on the wafer being too large.
[0062] like Figure 8 and Figure 9 In steps S7 and S8, when etching above the silicon oxide layer to form contact holes on the wafer, if the contact hole etching position deviates, the sidewall will not be etched away during the first etching above the silicon oxide layer. This ensures that even if the formed contact hole etching position deviates, the position of the contact hole will be restricted by the sidewall. This also ensures that when filling the contact hole with metal in step S8, the metal will not conduct electricity with the polysilicon, thus providing insulation protection through the sidewall.
[0063] like Figure 10 If no sidewall is made to provide protection in step S1, and the contact hole is etched in step S8, if the contact hole position is deviated due to insufficient equipment precision, the metal filling the contact hole and the polysilicon in the contact trench will become conductive, which will cause the wafer to fail to meet the usage requirements.
[0064] Compared with related technologies, the trench transistor fabrication method for wafers provided by this invention has the following advantages:
[0065] 1. By etching silicon nitride to form sidewalls on the wafer, the size of the trench opening on the wafer can be limited by the sidewalls when making transistors through the etched trenches. This avoids the trench opening being too large due to insufficient precision of the etching equipment, and reduces the precision requirements of the equipment used when etching trenches.
[0066] Second, by creating contact holes on the wafer, the sidewalls can provide insulation protection between the contact holes and the polysilicon in the trenches. This prevents the contact holes from contacting the polysilicon even if there is a deviation in the position of the contact holes when they are directly created. This avoids the metal and polysilicon becoming conductive when the contact holes are filled with metal due to the position deviation of the contact holes. This reduces the precision requirements of the equipment when creating transistors and metals on the back of the wafer. Even if there is a deviation in the etching position, it will not affect the wafer manufacturing.
[0067] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.
Claims
1. A method for fabricating trench transistors on wafers, characterized in that, Includes the following steps: S1. A silicon nitride deposition layer is formed on the wafer with silicon oxide on the back side using chemical vapor deposition. Then the wafer is etched to remove the silicon nitride deposition layer on the wafer, so that the silicon nitride deposition layer forms sidewalls on both sides of the silicon oxide. Finally, the position between the sidewalls on the top of the wafer is etched to form a trench on the top of the wafer. S2. The wafer obtained in step S1 is oxidized to form a gate silicon oxide layer on the back side of the wafer and the inner wall of the trench. Then the back side of the wafer is etched to remove the gate silicon oxide layer on the back side of the wafer and the trench. Finally, ion implantation is performed on the back side of the wafer using the ion implantation method. S3. The inner wall of the wafer trench obtained in step S2 is oxidized separately to form a dense gate silicon oxide layer on the inner wall of the trench. S4. For the wafer obtained in step S3, a layer of polysilicon is formed on the back side of the wafer and inside the trench using chemical vapor deposition, and then the top of the polysilicon on the back side of the wafer is planarized using CMP process. S5. Etch the back side of the wafer obtained in step S4 to remove the polysilicon located on the back side of the wafer, and then deposit a layer of silicon oxynitride on the back side of the wafer using chemical vapor deposition. S6. For the wafer obtained in step S5, a silicon oxide layer is deposited on top of silicon oxynitride using chemical vapor deposition, and then the top of the silicon oxide layer is planarized using CMP process. S7. For the wafer obtained in step S6, etching is performed on the silicon oxide layer to the silicon oxynitride surface, and then the silicon oxynitride, silicon oxide and the top of the wafer below the opening of the silicon oxide layer are etched away in sequence to form a contact hole on the top of the wafer. S8. In step S7, the bottom of the contact hole formed at the top of the wafer is ion implanted using the ion implantation method, and then metal is filled into the contact hole. In steps S2 and S3, both the oxidation of the wafer and the oxidation of the inner wall of the trench are carried out in an oxidation furnace. In step S2, the back side of the wafer is etched away. When the gate silicon oxide layer on the back side of the wafer is etched away, a portion of the top of the silicon oxide layer on the back side of the wafer is also etched away. In step S8, when etching is performed above the silicon oxide layer on the back of the wafer, the wafer needs to be developed. The steps are as follows: first, a layer of photoresist is coated on the surface of the wafer, then light exposure is performed to form a pattern on the surface of the wafer that is partially exposed and partially unexposed. After development, the unexposed areas are covered by the photoresist.
2. The trench transistor fabrication method for wafers according to claim 1, characterized in that, In steps S1, S4 and S8, the sidewall formed in step S1 is located between the metal and the polysilicon to avoid electrical conductivity between the metal and the polysilicon.
3. The trench transistor fabrication method for wafers according to claim 1, characterized in that, In steps S4 and S5, the polysilicon deposited by chemical vapor deposition is polysilicon containing impurities, so as to form transistors at the trench locations of the wafer.
4. The trench transistor fabrication method for wafers according to claim 1, characterized in that, In step S8, the ions implanted at the bottom of the contact hole and the ions implanted in step S2 form an electrode on the back side of the wafer.
5. A method for fabricating trench transistors for wafers according to claim 1, characterized in that, Step S1 can also first perform ion implantation on the back side of the wafer using ion implantation method, then form a silicon nitride deposition layer using chemical vapor deposition method, then etch the wafer to remove the silicon nitride deposition layer on the wafer, so that the silicon nitride deposition layer forms sidewalls on both sides of silicon oxide, and finally etch the position between the sidewalls on the top of the wafer to form a trench on the top of the wafer. In step S2, the wafer obtained in step S1 can be oxidized first to form a gate silicon oxide layer on the back side of the wafer and the inner wall of the trench, and then the back side of the wafer can be etched to remove the gate silicon oxide layer on the back side of the wafer and the trench.
Citation Information
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