Method for manufacturing thin film transistor array substrate

Abstract

The present invention provides a method for manufacturing a thin-film transistor array substrate, comprising: providing a prefabricated substrate, forming a transparent conductive layer on the prefabricated substrate; the prefabricated substrate comprising a stacked opaque conductive layer and a spacer layer, the spacer layer being disposed on the opaque conductive layer, the spacer layer being provided with a connection hole, the transparent conductive layer being inserted into the connection hole to contact and connect with the opaque conductive layer; patterning the transparent conductive layer using a yellow light process; forming an isolation layer on the patterned transparent conductive layer; performing high-temperature annealing on the patterned transparent conductive layer with the isolation layer; and removing the isolation layer. The method for manufacturing a thin-film transistor array substrate of the present invention can improve product yield.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a method for manufacturing a thin film transistor array substrate. Background Art

[0002] Liquid crystal display panels have the advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, and dominate the field of flat panel displays.

[0003] Currently, thin-film transistor array substrates for liquid crystal display panels use indium tin oxide (ITO) as transparent conductive film layers (such as pixel electrodes and common electrodes) in combination with copper (Cu) or copper-containing composite materials as opaque conductive film layers (such as source / drain electrodes, scan lines, and data lines). This is a common practice in thin-film transistor array substrate technology in recent years. When a transparent conductive film layer needs to be electrically connected to an opaque conductive film layer, connection holes are typically opened in the various film layers located between the transparent and opaque conductive film layers. When the transparent conductive film layer is formed, it is filled into the connection hole to contact and connect with the opaque conductive film layer.

[0004] Figure 1 This is a schematic diagram of the manufacturing process of an indium tin oxide transparent conductive film layer of an existing thin film transistor array substrate. The process of manufacturing the indium tin oxide transparent conductive film layer includes:

[0005] Step S1: forming an ITO film layer, that is, disposing an entire ITO layer on a substrate on which an indium tin oxide transparent conductive film layer is to be disposed;

[0006] Step S2: Patterning the ITO film layer using a yellow light process, including cleaning - applying photoresist - exposing - developing - removing photoresist and other processes;

[0007] Step S3: high temperature annealing, that is, heat treatment of the patterned ITO film layer to convert it into a polycrystalline state with low resistance and high transmittance.

[0008] However, during the high-temperature annealing process in step S3, the insulation performance of the ITO film layer deteriorates due to the high temperature. Water vapor and oxygen molecules in the environment will pass through the ITO film layer at high temperature and oxidize the copper in the copper-containing opaque conductive film layer that is directly in contact with the ITO film layer in the connection hole, forming small black spots (such as Figure 2 and Figure 3 (as shown), copper oxidizes, corrodes, and bulges, shortening the product's lifespan. During subsequent reliability testing of finished products, small black spots at the connection holes accelerate corrosion, ultimately affecting product yield. Summary of the Invention

[0009] An object of the present invention is to provide a method for manufacturing a thin film transistor array substrate, which can improve the yield of the product.

[0010] The present invention provides a method for manufacturing a thin-film transistor array substrate, comprising: providing a prefabricated substrate; forming a transparent conductive layer on the prefabricated substrate; the prefabricated substrate comprising a stacked opaque conductive layer and a spacer layer, the spacer layer being disposed on the opaque conductive layer and having a connection hole formed therein; the transparent conductive layer being inserted into the connection hole to contact and connect with the opaque conductive layer; patterning the transparent conductive layer using a photolithography process; forming an isolation layer on the patterned transparent conductive layer; performing a high-temperature annealing on the patterned transparent conductive layer with the isolation layer; and removing the isolation layer.

[0011] Furthermore, the opaque conductive layer is made of copper or copper alloy and has a single-layer or multi-layer structure, and the transparent conductive layer is made of indium tin oxide.

[0012] Furthermore, the prefabricated substrate further includes a barrier layer, and the barrier layer is arranged below the opaque conductive layer.

[0013] Furthermore, the opaque conductive layer is a scan line, a source / drain, a data line or a peripheral connection line on the thin film transistor array substrate.

[0014] Furthermore, the patterned transparent conductive layer is a pixel electrode, a common electrode or a peripheral connection line on the thin film transistor array substrate.

[0015] Furthermore, the material of the isolation layer is molybdenum.

[0016] Furthermore, the method for removing the isolation layer includes: removing the isolation layer by wet etching using an aluminate etching solution.

[0017] The present invention provides a method for manufacturing a thin film transistor array substrate. The thin film transistor array substrate has a display area and includes:

[0018] providing a substrate;

[0019] forming a gate on the substrate, wherein the gate is located in a display area;

[0020] forming a gate insulating layer covering the gate on the substrate;

[0021] forming a semiconductor layer on the gate insulating layer, wherein the semiconductor layer is located above the gate;

[0022] forming a source electrode and a drain electrode on the gate insulating layer, wherein the source electrode and the drain electrode are spaced apart from each other and cover a portion of the semiconductor layer, and the remaining portion of the semiconductor layer is exposed between the source electrode and the drain electrode;

[0023] forming a first passivation layer on the gate insulating layer, wherein the first passivation layer covers the source electrode, the drain electrode, and a portion of the semiconductor layer exposed between the source electrode and the drain electrode;

[0024] forming a planarization layer on the first passivation layer;

[0025] forming a first electrode layer on the planar layer;

[0026] forming a second passivation layer on the planar layer, wherein the second passivation layer covers the first electrode layer;

[0027] forming a first connection hole in the second passivation layer, the planar layer, and the first passivation layer at a position corresponding to the drain electrode to expose the drain electrode;

[0028] forming an indium tin oxide thin film on the second passivation layer;

[0029] Patterning the indium tin oxide thin film using a yellow light process to form a second electrode layer, and filling the first connection hole with the second electrode layer so as to contact and connect with the drain electrode;

[0030] forming an isolation layer on the second passivation layer, wherein the isolation layer covers the second electrode layer;

[0031] annealing the prefabricated substrate formed in the above steps at a high temperature; and

[0032] The isolation layer is removed.

[0033] Furthermore, the thin film transistor array substrate has a non-display area arranged around the display area, the second passivation layer, the planarization layer, the first passivation layer, and the gate insulating layer all cover the display area and the non-display area, and the manufacturing method further includes:

[0034] When forming the gate, a first peripheral conductive line is simultaneously formed in the non-display area;

[0035] When forming the first connection hole, a second connection hole is simultaneously formed in the second passivation layer, the planar layer, the first passivation layer and the gate insulating layer at a position corresponding to the first peripheral wire to expose the first peripheral wire;

[0036] When forming the second electrode layer, a second peripheral wire is simultaneously formed in the non-display area. The second peripheral wire is filled in the second connection hole and is in contact with and connected to the first peripheral wire.

[0037] Furthermore, the first peripheral wire and / or the drain electrode is a single-layer or multi-layer structure made of copper or copper alloy.

[0038] The method for manufacturing a thin-film transistor array substrate provided by the present invention effectively prevents water vapor and oxygen molecules in the environment from penetrating the high-temperature transparent conductive layer (second electrode layer, second peripheral wire) and corroding the opaque conductive layer (drain, first peripheral wire) in the connection hole during the high-temperature annealing step by providing an isolation layer on the transparent conductive layer (second electrode layer, second peripheral wire), thereby improving the product yield.

[0039] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above-mentioned oxide semiconductor thin film transistor array substrate and its data line repair method, and other purposes, features and advantages of the display device of the present invention more obvious and easy to understand, the following specifically cites preferred embodiments and explains them in detail with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 The present invention is a schematic diagram of the manufacturing process of an indium tin oxide transparent conductive film layer of an existing thin film transistor array substrate.

[0041] Figure 2 It is a surface image of small black spots formed by copper oxidation at the connection hole position of an existing thin film transistor array substrate.

[0042] Figure 3 yes Figure 2 Cross-sectional images of the locations of small and medium black dots.

[0043] Figure 4 FIG. 4 is a schematic diagram of a process of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

[0044] Figure 5a to Figure 5b FIG1 is a schematic cross-sectional structural diagram of a method for manufacturing a thin film transistor array substrate according to a first embodiment of the present invention during the manufacturing process.

[0045] Figures 6a to 6b FIG2 is a schematic cross-sectional structural diagram of a method for manufacturing a thin film transistor array substrate according to a second embodiment of the present invention during the manufacturing process. DETAILED DESCRIPTION

[0046] To further illustrate the technical means and effects of the present invention to achieve the intended purpose, the following describes in detail the specific implementation, structure, features, and effects of the method for manufacturing a thin film transistor array substrate according to the present invention, in conjunction with the accompanying drawings and preferred embodiments.

[0047] The aforementioned and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiment with reference to the accompanying drawings. Through the description of the specific embodiments, a deeper and more detailed understanding of the technical means and effects adopted by the present invention to achieve the intended objectives can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the present invention.

[0048] [First embodiment]

[0049] Figure 4 FIG. 4 is a schematic diagram of a process of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention. Figure 5a to Figure 5b FIG1 is a schematic cross-sectional view of a method for manufacturing a thin film transistor array substrate according to a first embodiment of the present invention during the manufacturing process. Figures 4 to 5b The method for manufacturing a thin film transistor array substrate provided in this embodiment includes:

[0050] Step S11 : providing a prefabricated substrate 100 , and forming a transparent conductive layer 40 on the prefabricated substrate 100 .

[0051] Specifically, if Figure 5a As shown, the prefabricated substrate 100 includes an opaque conductive layer 20 and a spacer layer 30 stacked together. The spacer layer 30 is disposed on the opaque conductive layer 20 and has a connection hole 31 formed therein. The transparent conductive layer 40 is inserted into the connection hole 31 and is in contact with the opaque conductive layer 20. The opaque conductive layer 20 is a single-layer or multi-layer structure made of copper (Cu) or a copper alloy, and the transparent conductive layer 40 is made of indium tin oxide (ITO).

[0052] Furthermore, the prefabricated substrate 100 includes a barrier layer 10. Disposed beneath the opaque conductive layer 20, the barrier layer 10 is used to prevent copper elements within the opaque conductive layer 20 from diffusing downward and to prevent water vapor and oxygen molecules within other layers below the barrier layer 10 from diffusing upward and affecting the opaque conductive layer 20. The barrier layer 10 is made of, for example, molybdenum-niobium alloy (MoNb).

[0053] Furthermore, the opaque conductive layer 20 may be a scan line, a source / drain, a data line, a peripheral connection line, etc. on the thin film transistor array substrate.

[0054] Step S12: patterning the transparent conductive layer 40 using a photolithography process.

[0055] The yellow light process includes cleaning-photoresist application-exposure-development-photoresist removal and other processes, which are well known to those skilled in the art and will not be described in detail here.

[0056] The patterned transparent conductive layer 40 can be a pixel electrode, a common electrode, a peripheral connection line, etc. on a thin film transistor array substrate.

[0057] Step S13: forming an isolation layer 50 on the patterned transparent conductive layer 40, the isolation layer 50 covering the patterned transparent conductive layer 40 and other structures on the prefabricated substrate 1 exposed from the patterned transparent conductive layer 40. The isolation layer 50 is made of a material that can block the passage of water vapor, oxygen molecules, etc.

[0058] Furthermore, the material of the isolation layer 50 may be molybdenum (Mo).

[0059] Step S14: performing high-temperature annealing on the patterned transparent conductive layer 40 provided with the isolation layer 50 .

[0060] The transparent conductive layer 40 is subjected to high-temperature annealing to transform it into a polycrystalline state with low resistance and high transmittance. In this embodiment, since an isolation layer 50 is disposed above the transparent conductive layer 40, during the high-temperature annealing process, the isolation layer 50 blocks water vapor and oxygen molecules from passing through the high-temperature transparent conductive layer 40. Therefore, the copper-containing opaque conductive layer 20 located within the connection hole 31 is not corroded by water vapor and oxygen molecules, thereby preventing the formation of small black spots.

[0061] Step S15: removing the isolation layer 50.

[0062] Specifically, if Figure 5b As shown, the isolation layer 50 is removed using an etching solution that can remove the isolation layer 50. For example, when the isolation layer 50 is made of molybdenum, the isolation layer 50 can be removed by wet etching using an aluminic acid etching solution.

[0063] The method for manufacturing a thin-film transistor array substrate provided by an embodiment of the present invention effectively prevents water vapor and oxygen molecules from penetrating the high-temperature transparent conductive layer 40 and corroding the opaque conductive layer 20 within the connection hole 31 during the high-temperature annealing step by disposing an isolation layer 50 on the transparent conductive layer 40 before the layer is subjected to high-temperature annealing, thereby improving product yield. Compared to the prior art, the present invention only adds two steps and does not affect other existing processes, making it easy to implement.

[0064] After removing the isolation layer 50, the process of disposing other film layers on the patterned transparent conductive layer 40 is also included. This process is well known to those skilled in the art and will not be described in detail here. The thin film transistor array substrate produced by the above-mentioned production method can be used in liquid crystal display devices or organic light emitting diode display devices.

[0065] [Second embodiment]

[0066] Figures 6a to 6b FIG2 is a cross-sectional structural diagram of a manufacturing method of a thin film transistor array substrate according to a second embodiment of the present invention during the manufacturing process. Figure 4 、 Figure 6a and Figure 6b The thin film transistor array substrate has a display area ( Figure 6a 、 Figure 6b left of the middle dotted line) and non-display area ( Figure 6a 、 Figure 6b The non-display area is arranged around the display area. The manufacturing method of the thin film transistor array substrate includes:

[0067] A substrate 1 is provided; the substrate 1 is, for example, a transparent plastic plate or a glass plate.

[0068] A gate 2a and a first peripheral conductive line 2b are formed on a substrate 1. The gate 2a and the first peripheral conductive line 2b are arranged on the same layer, with the gate 2a located in the display area and the first peripheral conductive line 2b located in the non-display area. The gate 2a and the first peripheral conductive line 2b are generally formed of a single-layer or multi-layer structure made of materials such as chromium (Cr), chromium alloys, molybdenum-tantalum (MoTa) alloys, aluminum (Al), aluminum alloys, copper (Cu), and copper alloys. The formation of the gate 2a and the first peripheral conductive line 2b also includes forming scan lines within the display area.

[0069] A gate insulating layer 3 is formed on the substrate 1, and the gate insulating layer 3 covers the gate 2a and the first peripheral wire 2b; the material of the gate insulating layer 3 can be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) etc., or silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and silicon nitride (SiN x ) is a multilayer composite material formed by combining multiple ).

[0070] A semiconductor layer 4 is formed on the gate insulating layer 3 and is located above the gate 2a. The material of the semiconductor layer 4 can be amorphous silicon (a-Si), doped amorphous silicon (n+a-Si) or metal oxide.

[0071] A source electrode 5a and a drain electrode 5b are formed on the gate insulating layer 3. The source electrode 5a and the drain electrode 5b are spaced apart from each other and cover a portion of the semiconductor layer 4. The remaining portion of the semiconductor layer 4 is exposed between the source electrode 5a and the drain electrode 5b. The source electrode 5a and the drain electrode 5b are a single-layer or multi-layer structure made of copper (Cu) or a copper alloy. When forming the source electrode 5a and the drain electrode 5b, a data line connected to the source electrode 5a is also formed in the display area.

[0072] A first passivation layer 6 is formed on the gate insulating layer 3, and the first passivation layer 6 covers the source electrode 5a, the drain electrode 5b and the portion of the semiconductor layer 4 exposed between the source electrode 5a and the drain electrode 5b; the material of the first passivation layer 6 can be silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, etc., or a multilayer composite material formed by a combination of multiple silicon oxide, silicon oxynitride, aluminum oxide and silicon nitride.

[0073] A planarization layer 7 is formed on the first passivation layer 6 ; an example of a material of the planarization layer 7 may be resin.

[0074] A first electrode layer 8 is formed on the planar layer 7 . The material of the first electrode layer 8 may be indium tin oxide (ITO). The first electrode layer 8 is, for example, a common electrode.

[0075] A second passivation layer 9 is formed on the planarization layer 7, covering the first electrode layer 8. The material of the second passivation layer 9 can be silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or a multilayer composite material formed by combining multiple of these materials. The second passivation layer 9, the planarization layer 7, the first passivation layer 6, and the gate insulation layer 3 all cover both the display area and the non-display area.

[0076] A first connection hole 9a is formed in the second passivation layer 9, the flat layer 7 and the first passivation layer 6 at a position corresponding to the drain electrode 5b to expose the drain electrode 5b. At the same time, a second connection hole 9b is formed in the second passivation layer 9, the flat layer 7, the first passivation layer 6 and the gate insulation layer 3 at a position corresponding to the first peripheral wire 2b to expose the first peripheral wire 2b.

[0077] An indium tin oxide thin film is formed on the second passivation layer 9 .

[0078] The indium tin oxide film is patterned using a photolithography process to form a second electrode layer 10a and a second peripheral conductive line 10b. The second electrode layer 10a is inserted into the first connection hole 9a and is in contact with the drain electrode 5b. The second peripheral conductive line 10b is inserted into the second connection hole 9b and is in contact with the first peripheral conductive line 2b. The second electrode 10a is, for example, a pixel electrode.

[0079] like Figure 6a As shown, an isolation layer 50 is formed on the second passivation layer 9 , and the isolation layer 50 covers the second electrode layer 10 a and the second peripheral wire 10 b ; the material of the isolation layer 50 may be molybdenum (Mo).

[0080] The prefabricated substrate formed in the above steps is subjected to high-temperature annealing to transform the second electrode layer 10a and the second peripheral wire 10b into a polycrystalline state with low resistance and high transmittance.

[0081] like Figure 6bAs shown, the isolation layer 50 is finally removed. The isolation layer 50 is removed using an etching solution that can remove the isolation layer 50. For example, when the isolation layer 50 is made of molybdenum, the isolation layer 50 can be removed using an aluminate etching solution by wet etching.

[0082] In this embodiment, an isolation layer 50 is formed before the second electrode layer 10a and the second peripheral wire 10b are subjected to high-temperature annealing. During the high-temperature annealing process, the isolation layer 50 blocks water vapor and oxygen molecules in the environment from passing through the second electrode layer 10a and the second peripheral wire 10b at high temperature. Therefore, the drain 5b located in the first connection hole 9a and the first peripheral wire 2b located in the second connection hole 9b will not be affected by water vapor and oxygen molecules and corroded to form small black spots.

[0083] The method for manufacturing a thin-film transistor array substrate provided in an embodiment of the present invention effectively prevents water vapor and oxygen molecules in the environment from passing through the second electrode layer 10a and the second peripheral wire 10b at high temperature to corrode the drain 5b in the first connection hole 9a and the first peripheral wire 2b in the second connection hole 9b during the high-temperature annealing process by providing an isolation layer 50 on the second electrode layer 10a and the second peripheral wire 10b before performing high-temperature annealing on the second electrode layer 10a and the second peripheral wire 10b, thereby improving the product yield.

[0084] The above is a detailed introduction to the method for manufacturing the thin film transistor array substrate provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, based on the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for manufacturing a thin film transistor array substrate, characterized in that: include: A prefabricated substrate (100) is provided, and a transparent conductive layer (40) is formed on the prefabricated substrate (100); the prefabricated substrate (100) comprises an opaque conductive layer (20) and a spacer layer (30) which are stacked, the spacer layer (30) being arranged on the opaque conductive layer (20), a connection hole (31) being provided on the spacer layer (30), and the transparent conductive layer (40) being filled in the connection hole (31) and in contact with and connected to the opaque conductive layer (20); Patterning the transparent conductive layer (40) using a yellow light process; forming an isolation layer (50) on the patterned transparent conductive layer (40); Performing high-temperature annealing on the patterned transparent conductive layer (40) provided with the isolation layer (50); and The isolation layer (50) is removed.

2. The method for manufacturing a thin film transistor array substrate according to claim 1, wherein: The opaque conductive layer (20) is a single-layer or multi-layer structure made of copper or copper alloy, and the material of the transparent conductive layer (40) is indium tin oxide.

3. The method for manufacturing a thin film transistor array substrate according to claim 2, wherein: The prefabricated substrate (100) further comprises a barrier layer (10), wherein the barrier layer (10) is arranged below the opaque conductive layer (20).

4. The method for manufacturing a thin film transistor array substrate according to claim 2, wherein: The opaque conductive layer (20) is a scanning line, a source / drain, a data line or a peripheral connection line on the thin film transistor array substrate.

5. The method for manufacturing a thin film transistor array substrate according to claim 2, wherein: The patterned transparent conductive layer (40) is a pixel electrode, a common electrode or a peripheral connection line on the thin film transistor array substrate.

6. The method for manufacturing a thin film transistor array substrate according to claim 2, wherein: The material of the isolation layer (50) is molybdenum.

7. The method for manufacturing a thin film transistor array substrate according to claim 6, wherein: The method for removing the isolation layer (50) comprises: removing the isolation layer (50) by wet etching using an aluminate etching solution.

8. A method for manufacturing a thin film transistor array substrate, wherein the thin film transistor array substrate has a display area, characterized in that: include: providing a substrate (1); forming a gate electrode (2a) on the substrate (1), wherein the gate electrode (2a) is located in a display area; forming a gate insulating layer (3) covering the gate (2a) on the substrate (1); forming a semiconductor layer (4) on the gate insulating layer (3), wherein the semiconductor layer (4) is located above the gate (2a); A source electrode (5a) and a drain electrode (5b) are formed on the gate insulating layer (3), wherein the source electrode (5a) and the drain electrode (5b) are spaced apart from each other and cover a portion of the semiconductor layer (4), and the remaining portion of the semiconductor layer (4) is exposed between the source electrode (5a) and the drain electrode (5b); forming a first passivation layer (6) on the gate insulating layer (3), wherein the first passivation layer (6) covers the source electrode (5a), the drain electrode (5b), and the portion of the semiconductor layer (4) exposed between the source electrode (5a) and the drain electrode (5b); forming a flat layer (7) on the first passivation layer (6); forming a first electrode layer (8) on the flat layer (7); forming a second passivation layer (9) on the flat layer (7), wherein the second passivation layer (9) covers the first electrode layer (8); forming a first connection hole (9a) at a position corresponding to the drain electrode (5b) in the second passivation layer (9), the flat layer (7) and the first passivation layer (6) to expose the drain electrode (5b); forming an indium tin oxide thin film on the second passivation layer (9); The indium tin oxide thin film is patterned using a yellow light process to form a second electrode layer (10a), and the second electrode layer (10a) is filled into the first connection hole (9a) and is in contact with and connected to the drain electrode (5b); forming an isolation layer (50) on the second passivation layer (9), wherein the isolation layer (50) covers the second electrode layer (10a); annealing the prefabricated substrate formed in the above steps at a high temperature; and The isolation layer (50) is removed.

9. The method for manufacturing a thin film transistor array substrate according to claim 8, wherein: The thin film transistor array substrate has a non-display area arranged around the display area, the second passivation layer (9), the flat layer (7), the first passivation layer (6), and the gate insulating layer (3) all cover the display area and the non-display area, and the manufacturing method further includes: When forming the gate electrode (2a), a first peripheral conductive line (2b) is simultaneously formed in the non-display area; When forming the first connection hole (9a), a second connection hole (9b) is simultaneously formed at a position corresponding to the first peripheral wire (2b) in the second passivation layer (9), the flat layer (7), the first passivation layer (6) and the gate insulating layer (3) to expose the first peripheral wire (2b); When forming the second electrode layer (10a), a second peripheral wire (10b) is simultaneously formed in the non-display area. The second peripheral wire (10b) is filled into the second connection hole (9b) and is in contact with and connected to the first peripheral wire (2b).

10. The method for manufacturing a thin film transistor array substrate according to claim 9, wherein: The first peripheral wire (2b) and / or the drain electrode (5b) are a single-layer or multi-layer structure made of copper or a copper alloy.

Images