3D memory device, manufacturing method thereof, storage system, and electronic device

Abstract

The application discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a chip storage area, the chip storage area comprises: a stack structure on a semiconductor substrate; a plurality of gate line gaps penetrating through the stack structure, part of the gate line gaps divide the chip storage area into a plurality of block storage areas, the plurality of gate line gaps are arranged along a first direction, and a plurality of channel columns penetrating through the stack structure are arranged between adjacent gate line gaps, the chip storage area comprises a central area and at least one edge area arranged along the first direction, and the minimum distance between at least one gate line gap and its adjacent channel column in the at least one edge area is greater than the minimum distance between at least one gate line gap and its adjacent channel column in the central area. By increasing the minimum distance between the gate line gap and its adjacent channel column in the edge area, the influence of stress and load effect on the 3D NAND device is avoided, and the low reliability and low yield of the 3D NAND device are avoided.

Description

Technical Field

[0001] This invention relates to memory technology, and more specifically, to 3D memory devices, methods of manufacturing the same, memory systems, and electronic devices. Background Technology

[0002] The increase in storage density of memory devices is closely related to advancements in semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes shrinks, the storage density of memory devices increases. To further improve storage density, three-dimensional memory devices (i.e., 3D memory devices) have been developed. 3D memory devices can significantly increase integration density per unit area of ​​wafer while reducing costs.

[0003] In the fabrication of 3D memory devices, the initial stacked structure formed on the substrate includes alternating stacked interlayer insulating layers and sacrificial layers. Then, the sacrificial layers in the stacked structure are replaced with gate conductors through gate line slits (GLS) that penetrate the stacked structure. These gate line slits further divide each plane of memory into multiple blocks of memory.

[0004] In NAND-structured 3D memory devices, significant stress and load effects exist when etching gate gaps at the edges of the chip storage area (e.g., macroscopic load effects, where the overall etching rate decreases due to the increase in the total etched area, making it very difficult to control the etching rate). This can lead to the formation of tilted gate gaps or gate gaps formed by self-stopping etching at the edges of the chip storage area. Tilted gate gaps may also come into contact with adjacent channel pillars, thereby reducing the reliability of NAND-structured 3D memory devices and even affecting product yield.

[0005] The goal is to further improve the structure and manufacturing methods of 3D memory devices, so as to ensure the reliability and product yield of 3D memory devices while pursuing higher storage density. Summary of the Invention

[0006] The purpose of this invention is to provide an improved 3D memory device and its manufacturing method, storage system, and electronic device, thereby improving the reliability and product yield of the 3D memory device.

[0007] According to one aspect of the present invention, a 3D storage device is provided, comprising a chip storage region, the chip storage region comprising:

[0008] Layered structure;

[0009] Multiple gate line gaps penetrate the stacked structure, and some of the gate line gaps divide the chip storage area into multiple block storage areas. The multiple gate line gaps are arranged along a first direction, and multiple channel posts penetrating the stacked structure are provided between adjacent gate line gaps.

[0010] The chip storage area includes a central area and at least one edge area arranged along the first direction. The minimum distance between at least one of the grid gaps in the at least one edge area and its adjacent channel post is greater than the minimum distance between any one of the grid gaps in the central area and its adjacent channel post.

[0011] Optionally, the chip storage area includes a first edge area and a second edge area located on both sides of the central area, wherein the minimum distance between any one of the gate gaps in the first edge area and / or the second edge area and its adjacent channel post is greater than the minimum distance between any one of the gate gaps in the central area and its adjacent channel post.

[0012] Optionally, the minimum distance between the grid line gap in the first edge region and its adjacent channel post increases along the direction extending from the center region to the first edge region, and / or the minimum distance between the grid line gap in the second edge region and its adjacent channel post increases along the direction extending from the center region to the second edge region.

[0013] Optionally, the spacing of at least one group of adjacent gate line gaps in the at least one edge region is greater than the spacing of any group of adjacent gate line gaps in the center region.

[0014] Optionally, the number of channel posts and the arrangement of channel posts are the same between each group of adjacent grid gaps.

[0015] Optionally, the chip storage area includes a first edge area and a second edge area located on both sides of the central area, wherein the spacing between any group of adjacent gate line gaps in the first edge area and / or the second edge area is greater than the spacing between any group of adjacent gate line gaps in the central area.

[0016] Optionally, the spacing between adjacent gate line gaps in the first edge region increases along the direction extending from the center region to the first edge region, and / or the spacing between adjacent gate line gaps in the second edge region increases along the direction extending from the center region to the second edge region.

[0017] Optionally, the spacing between adjacent gate line gaps in the central region is equal.

[0018] Optionally, the width of any one of the gate gaps located in at least one of the edge regions along the first direction is greater than or equal to the width of any one of the gate gaps located in the center region along the first direction.

[0019] Optionally, the chip storage area includes a first edge area and a second edge area located on both sides of the central area, wherein the width of the gate line gap in the first edge area increases along the direction of the central area toward the first edge area, and / or the width of the gate line gap in the second edge area increases along the direction of the central area toward the second edge area.

[0020] Optionally, the spacing between adjacent gate line gaps in the at least one edge region is equal to the spacing between adjacent gate line gaps in the central region, and the spacing between adjacent gate line gaps in the central region is equal.

[0021] Optionally, the number of channel posts between adjacent grid gaps in the at least one edge region decreases along the direction extending from the center region to the edge region.

[0022] Optionally, the plurality of gate line gaps includes a plurality of first gate line gaps and a plurality of second gate line gaps. The plurality of first gate line gaps divide the chip storage area into a plurality of block storage areas. There are a plurality of second gate line gaps between adjacent first gate line gaps. Each second gate line gap has a notch spaced apart along a second direction. The notch breaks the second gate line gap. The first direction and the second direction intersect.

[0023] Wherein, the minimum distance between the first grid line gap in the at least one edge region and its adjacent channel post is greater than the minimum distance between the first grid line gap in the center region and its adjacent channel post; or / and, the minimum distance between the second grid line gap in the at least one edge region and its adjacent channel post is greater than the minimum distance between the second grid line gap in the center region and its adjacent channel post.

[0024] According to another aspect of the present invention, a method for manufacturing a 3D storage device is provided, comprising:

[0025] Forming a layered structure;

[0026] Forming channel columns that penetrate the stacked structure;

[0027] Multiple trenches are formed that penetrate the grid stack structure, and multiple channel posts are provided between adjacent trenches. The multiple trenches are arranged along a first direction.

[0028] The chip storage area includes a central area and at least one edge area arranged along the first direction. The minimum distance between at least one trench in the at least one edge area and its adjacent trench post is greater than the minimum distance between any trench in the central area and its adjacent trench post.

[0029] Optionally, the chip storage area includes a first edge area and a second edge area located on both sides of the central area, wherein the minimum distance between any one of the trenches in the first edge area and / or the second edge area and its adjacent trench post is greater than the minimum distance between any one of the trenches in the central area and its adjacent trench post.

[0030] Optionally, the minimum distance between the trench in the first edge region and its adjacent trench post increases along the direction of the central region toward the first edge region, and / or the minimum distance between the trench in the second edge region and its adjacent trench post increases along the direction of the central region toward the second edge region.

[0031] Optionally, the spacing between at least one group of adjacent trenches in the at least one edge region is greater than the spacing between any group of adjacent trenches in the central region.

[0032] Optionally, the chip storage area includes a first edge area and a second edge area located on both sides of the central area, wherein the spacing between any group of adjacent trenches in the first edge area and / or the second edge area is greater than the spacing between any group of adjacent trenches in the central area.

[0033] Optionally, the spacing between adjacent grooves in the first edge region increases along the direction of extension from the center region to the first edge region, and / or the spacing between adjacent grooves in the second edge region increases along the direction of extension from the center region to the second edge region.

[0034] Optionally, the width of any one of the grooves located in at least one of the edge regions along the first direction is greater than or equal to the width of any one of the grooves located in the center region along the first direction.

[0035] According to another aspect of the present invention, a storage system is provided, comprising: a 3D storage device as described above; and

[0036] A controller is used to control the storage of data in storage devices.

[0037] According to another aspect of the present invention, an electronic device is provided, comprising: a storage system as described above.

[0038] According to embodiments of the 3D memory device and its manufacturing method, the chip memory region includes a central region and at least one edge region disposed along a first direction. The minimum distance between at least one gate gap in the at least one edge region and its adjacent channel pillar is set to be greater than the minimum distance between at least one gate gap in the central region and its adjacent channel pillar. This increases the distance between at least one gate gap in the edge region and its adjacent channel pillar, thereby avoiding low reliability and low yield of the 3D NAND device due to stress and load effects.

[0039] Furthermore, this application increases the size of at least one block memory region (along the first direction) in the edge region of the chip memory region by setting the spacing of at least one set of gate line gaps in the edge region of the chip memory region to be greater than the distance between adjacent gate line gaps in the center region. This increases the process window size for forming gate line gaps in the edge region of the chip memory region, thereby avoiding the situation of low reliability and low yield of 3D NAND devices due to stress and load effects.

[0040] In other embodiments, the chip storage region includes a first edge region and a second edge region located on both sides of the central region. The spacing between any group of adjacent gate line gaps in the first edge region is greater than the spacing between at least one group of adjacent gate line gaps in the central region, and / or the spacing between any group of adjacent gate line gaps in the second edge region is greater than the spacing between at least one group of adjacent gate line gaps in the central region. This avoids the situation where the gate line gaps in the edge regions of each chip storage region of the 3D NAND device are affected by stress and load effects, resulting in low reliability and low yield of the 3D NAND device.

[0041] In other embodiments, the width of the gate gap (dimensional features along the first direction) located in the first edge region and / or the second edge region is increased to further increase the process window and improve the reliability and product yield of the 3D NAND device. Attached Figure Description

[0042] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0043] Figure 1 A schematic diagram of gate gaps and channel pillars in the edge portion of a chip storage area in a 3D memory device is shown.

[0044] Figure 2 A schematic diagram of a 3D storage device provided according to an embodiment of the present invention is shown.

[0045] Figure 3 A schematic diagram of a chip storage area of ​​a 3D memory device according to an embodiment of the present invention is shown.

[0046] Figure 4A schematic diagram of a chip storage area of ​​another 3D memory device provided according to an embodiment of the present invention is shown.

[0047] Figure 5 A schematic diagram of a storage system provided according to an embodiment of the present invention is shown. Detailed Implementation

[0048] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0049] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0050] 3D NAND storage devices include several memory areas, each of which is further divided into several block memory areas. The block memory areas are isolated from each other by gate gaps that run through the stacked structure.

[0051] Figure 1 A schematic diagram of gate gaps and channel pillars in the edge portion of a chip storage area in a 3D memory device is shown. The following description of 3D memory devices uses a 3D NAND device as an example.

[0052] In the fabrication of 3D NAND devices, several channel pillars 110 and multiple gate line gaps 120 are typically formed throughout the stacked structure of the substrate. The gate line gaps 120 divide the channel pillars into different wafer memory regions or different block memory regions. For example... Figure 1 As shown, during the etching process to form gate gaps at the edge of the chip storage area, stress and load effects cause the gate gaps 120 formed in this region to tilt along the thickness direction of the stacked structure. In severe cases, they may come into contact with adjacent channel pillars 110. Even worse, this could cause the etching process to automatically stop in this region.

[0053] This application addresses the technical problem of low reliability and low yield of 3D NAND devices caused by stress and load effects in fabricating gate gaps in certain areas of the chip storage region by improving the minimum distance between the gate gaps and their adjacent channel pillars.

[0054] This application may be presented in various forms, some of which will be described below. Hereinafter, the second direction (X direction, horizontal direction in space) refers to a direction parallel to the semiconductor substrate, the first direction (Y direction, vertical direction in space) refers to a direction parallel to the semiconductor substrate and perpendicular to the second direction, and the third direction (Z direction) refers to a direction perpendicular to the semiconductor substrate, for example, perpendicular to the plane formed by the first and second directions.

[0055] Figure 2 A schematic diagram of a 3D storage device provided according to an embodiment of the present invention is shown.

[0056] like Figure 2 As shown, the 3D memory device includes at least one chip memory region. In this embodiment, the 3D memory device includes, for example, four chip memory regions (Plane 1, Plane 2, Plane 3, and Plane 4) arranged in an array along a first direction (Y direction) and a second direction (X direction). During fabrication, it was found that the gate gaps formed by etching in the edge region 200 of each chip memory region along the first direction are affected by stress and load effects. The 3D memory device provided in this application increases the etching process window for forming the gate gaps by adjusting the arrangement of the gate gaps in the edge region 200 of each chip memory region.

[0057] Furthermore, the following explanation will take a slice of memory in a 3D storage device as an example.

[0058] Figure 3 A schematic diagram of a chip storage area of ​​a 3D memory device according to an embodiment of the present invention is shown.

[0059] like Figure 3As shown, taking the chip memory region Plane1 as an example, the arrangement of the chip memory region along a first direction (Y direction) and a second direction (X direction) is illustrated. The chip memory region includes a central region and at least one edge region disposed along the first direction (Y direction). For example, it includes a first edge region 102, a central region 101, and a second edge region 103, with the first edge region 102 and the second edge region 103 located on both sides of the central region 101. Further, the chip memory region is stacked along a third direction (Z direction) with a semiconductor substrate, a stacked structure on the semiconductor substrate, a plurality of channel pillars 110 penetrating the stacked structure, and a plurality of gate line gaps penetrating the stacked structure and arranged along the first direction. Some of the gate line gaps divide the chip memory region into multiple block memory regions. A channel pillar 110 arranged along the first direction (Y direction) and the second direction (X direction) is disposed between two adjacent gate line gaps. Multiple channel posts 110 are provided between adjacent grid line gaps 121 in the first edge region 102 (the illustration is for illustrative purposes only and does not limit the arrangement or number of channel posts); multiple channel posts 110 are provided between adjacent grid line gaps 123 in the second edge region 103 (the illustration is for illustrative purposes only and does not limit the arrangement or number of channel posts); and multiple channel posts 110 are provided between adjacent grid line gaps 122 in the central region 102 (the illustration is for illustrative purposes only and does not limit the arrangement or number of channel posts). The minimum distance between at least one grid line gap in at least one edge region and its adjacent channel post is greater than the minimum distance between any grid line gap in the central region 101 and its adjacent channel post. Furthermore, the minimum distance between any grid gap in the first edge region 102 and / or the second edge region 103 and its adjacent channel post 110 is greater than the minimum distance between any grid gap in the central region 101 and its adjacent channel post 110. The minimum distance between a grid gap and its adjacent channel post 110 refers to the distance between the grid gap and its nearest channel post 110 along a first direction. For example, the minimum distance between grid gap 121 in the first edge region 102 and its adjacent channel post 110 increases along the direction extending from the central region 101 to the first edge region 102, and / or the minimum distance between grid gap 123 in the second edge region 103 and its adjacent channel post 110 increases along the direction extending from the central region 101 to the second edge region 103.

[0060] This application increases the area of ​​the 3D memory device, thereby increasing the area of ​​each chip memory region (increasing the width of each chip memory region along the first direction). This increases the spacing between the gate line gaps in the first edge region 102 and / or the second edge region 103 while keeping the gate line gap spacing 122 in the central region 101 unchanged. The number and arrangement of the channel posts 110 between adjacent gate line gaps in the two edge regions are, for example, the same as the number and arrangement of the channel posts 110 between adjacent gate line gaps in the central region 101. Further, the spacing of at least one group of adjacent gate line gaps in at least one edge region is greater than the spacing of any group of adjacent gate line gaps 122 in the central region 101. Further, the spacing of at least one group of adjacent gate line gaps 121 in the first edge region 102 is greater than the spacing of any group of adjacent gate line gaps 122 in the central region 101, and / or the spacing of at least one group of adjacent gate line gaps 123 in the second edge region 103 is greater than the spacing of any group of adjacent gate line gaps 122 in the central region 101.

[0061] In other embodiments, the spacing of any group of adjacent gate line gaps 121 in the first edge region 102 is greater than the spacing of any group of adjacent gate line gaps 122 in the central region 101, and / or the spacing of any group of adjacent gate line gaps 123 in the second edge region 103 is greater than the spacing of any group of adjacent gate line gaps 122 in the central region 101.

[0062] In other embodiments, the spacing of the gate line gaps 121 in the first edge region 102 increases, for example, along the direction extending from the center region 101 to the first edge region 102, and / or the spacing of the gate line gaps 123 in the second edge region 103 increases along the direction extending from the center region 101 to the second edge region 103. Further, in other embodiments, the gate line gaps in the first edge region 102 and the second edge region 103 are mirrored based on the center region 101.

[0063] In other embodiments, the spacing between the gate line gaps 122 in the central region 101 is equal. That is, the gate line gaps 122 in the central region 101 are uniformly distributed along the first direction (Y direction).

[0064] For example, the number and arrangement of the channel posts 110 between each group of adjacent grid line gaps are the same. That is, the number and arrangement of the channel posts 110 between adjacent grid line gaps 122 in the central region 101, between adjacent grid line gaps 121 in the first edge region 102, and between adjacent grid line gaps 123 in the second edge region 103 are, for example, the same. Further, the channel posts 110 between adjacent grid line gaps 123 are all located at the center of the area enclosed by the adjacent grid line gaps 123 (along the first direction).

[0065] In the above embodiments, by setting the spacing of at least one set of gate line gaps in the first edge region and / or the second edge region to be greater than the distance between any set of gate line gaps in the central region, the size of the block storage region in the edge region of the chip storage region is increased, thereby increasing the process window size for forming gate line gaps in this region, thereby avoiding the situation of low reliability and low yield of 3D NAND devices due to stress and load effects.

[0066] Alternatively, this application can increase the minimum distance between a gate gap and its adjacent channel pillars in the edge region by proportionally reducing the number of channel pillars 110 in the edge region without increasing the area of ​​the 3D memory device and without changing the relative positions of the gate gaps (the spacing between adjacent gate gaps in the edge region and the center region of each memory block is equal). Specifically, the number of channel pillars between adjacent gate gaps in the edge region decreases, for example, along the direction extending from the center region to the edge region.

[0067] Further, in other embodiments, the width (dimensional feature along the first direction) of any gate line gap 121 located in the first edge region 102 is greater than or equal to the width (dimensional feature along the first direction) of any gate line gap 122 located in the central region 101, and / or the width (dimensional feature along the first direction) of any gate line gap 123 located in the second edge region 103 is greater than or equal to the width (dimensional feature along the first direction) of any gate line gap 122 located in the central region 101. Further, the width of the gate line gap 121 in the first edge region 102 increases, for example, along the direction extending from the central region 101 to the first edge region 102, and / or the width of the gate line gap 123 located in the second edge region 103 increases, for example, along the direction extending from the central region 101 to the second edge region 103. Further, the width of the gate line gaps 122 in the central region 101 is, for example, all equal. In cases where the minimum distance between at least one gate gap in the first edge region and / or the second edge region and its adjacent channel post 110 is greater than the minimum distance between any gate gap 122 in the central region 101 and its adjacent channel post 110, the width of the gate gap located in the first edge region and / or the second edge region will be increased to further increase the process window and improve the reliability and product yield of the 3D NAND device.

[0068] It should be noted that the stacked structure, before and during the process of forming the gate gap, includes, for example, multiple sacrificial layers and multiple interlayer insulating layers stacked alternately. After forming the gate gap, the sacrificial layers are replaced with gate conductor layers through processes such as etching and deposition. The interlayer insulating layer includes, for example, oxide, and the sacrificial layer includes, for example, nitride. The material of the gate conductor layer includes, for example, tungsten. The semiconductor substrate is, for example, silicon.

[0069] It should be noted that the specific value of the minimum distance between the grid line gaps in the edge region and their adjacent channel posts, increasing along the direction from the center region to the edge region, is determined based on the actual process flow requirements. The specific value of the spacing between adjacent grid line gaps in the edge region, increasing along the direction from the center region to the edge region, is determined based on the actual process flow requirements. The specific value of the width of the grid line gaps in the edge region (the dimensional feature along the first direction), increasing along the direction from the center region to the edge region, is determined based on the actual process flow requirements.

[0070] Figure 4 A schematic diagram of a chip storage area of ​​another 3D memory device provided according to an embodiment of the present invention is shown.

[0071] like Figure 4 As shown, the chip memory region includes a central region and at least one edge region disposed along a first direction (Y direction). For example, it includes a first edge region 202, a central region 201, and a second edge region 203 disposed along the first direction (Y direction), with the first edge region 202 and the second edge region 203 located on either side of the central region 201. Further, the chip memory region is stacked along a third direction (Z direction) with a semiconductor substrate, a stacked structure on the semiconductor substrate, a plurality of channel pillars 210 penetrating the stacked structure, and a plurality of gate line gaps arranged along the first direction. Some of the gate line gaps divide the chip memory region into multiple block memory regions. Channel pillars arranged along the first direction (Y direction) and the second direction (X direction) are disposed between two adjacent gate line gaps. The first edge region 202 includes a plurality of gate line gaps 221, the second edge region 203 includes a plurality of gate line gaps 223, and the central region 102 includes a plurality of gate line gaps 222. Specifically, the minimum distance between at least one grid gap in at least one edge region and its adjacent channel post is greater than the minimum distance between any grid gap 222 in the central region 201 and its adjacent channel post 210. Further, the minimum distance between any grid gap in the first edge region 202 and / or the second edge region 203 and its adjacent channel post 210 is greater than the minimum distance between any grid gap 222 in the central region 201 and its adjacent channel post 210. The minimum distance between a grid gap and its adjacent channel post 210 refers to the distance between the grid gap and its nearest channel post 210 along a first direction. For example, the minimum distance between a grid gap 221 in the first edge region 202 and its adjacent channel post 210 increases along the direction extending from the central region 201 to the first edge region 202, and / or the minimum distance between a grid gap 223 in the second edge region 203 and its adjacent channel post 210 increases along the direction extending from the central region 201 to the second edge region 203.

[0072] Based on the aforementioned 3D storage device, multiple gate line gaps include multiple first gate line gaps and multiple second gate line gaps. The multiple first gate line gaps divide the chip storage area into multiple block storage areas. Several second gate line gaps are located between adjacent first gate line gaps. Each second gate line gap has a notch 230 (H-cut) spaced apart along a second direction, which breaks the second gate line gap. The first and second directions intersect. The depth of the notch 230 (dimensional feature along a third direction) is equal to the depth of the gate line gap (dimensional feature along a third direction) to completely break the gate line gap along the second direction, thereby dividing the block storage area into memory storage areas. The minimum distance between a first gate line gap in at least one edge region and its adjacent channel post is greater than the minimum distance between a first gate line gap in the center region and its adjacent channel post; or / and, the minimum distance between a second gate line gap in at least one edge region and its adjacent channel post is greater than the minimum distance between a second gate line gap in the center region and its adjacent channel post.

[0073] This application also provides a method for manufacturing a 3D memory device, used to prepare the aforementioned 3D memory device. The method includes forming a stacked structure on a semiconductor substrate, including multiple sacrificial layers and multiple interlayer insulating layers stacked alternately; forming multiple channel pillars penetrating the stacked structure; forming multiple trenches penetrating the gate stacked structure, wherein some trenches divide a chip memory region into multiple block memory regions, the multiple trenches are arranged along a first direction, and multiple channel pillars are provided between adjacent trenches, wherein the chip memory region includes a central region and at least one edge region disposed along the first direction, and the minimum distance between at least one trench in the at least one edge region and its adjacent channel pillar is greater than the minimum distance between any trench in the central region and its adjacent channel pillar. Subsequently, a gate gap is formed in the structure by filling the trenches with material.

[0074] Furthermore, the chip storage area includes a first edge area and a second edge area located on both sides of the central area. The minimum distance between any trench in the first edge area and / or the second edge area and its adjacent trench post is greater than the minimum distance between any trench in the central area and its adjacent trench post.

[0075] Furthermore, the minimum distance between the trench in the first edge region and its adjacent trench post increases along the direction of extension from the central region to the first edge region, and / or the minimum distance between the trench in the second edge region and its adjacent trench post increases along the direction of extension from the central region to the second edge region.

[0076] Furthermore, the spacing between at least one set of adjacent trenches in at least one edge region is greater than the spacing between any set of adjacent trenches in the central region.

[0077] Furthermore, the number of channel columns and the arrangement of channel columns are the same between each group of adjacent trenches.

[0078] Furthermore, the spacing between any pair of adjacent trenches in the first edge region and / or the second edge region is greater than the spacing between any pair of adjacent trenches in the central region.

[0079] Furthermore, the spacing between adjacent trenches in the first edge region increases along the direction of extension from the central region to the first edge region, and / or the spacing between trenches in the second edge region increases along the direction of extension from the central region to the second edge region.

[0080] Furthermore, the spacing between adjacent trenches in the central area is equal.

[0081] Furthermore, the width of any trench located in at least one edge region along the first direction is greater than or equal to the width of any trench located in the central region along the first direction.

[0082] Furthermore, the width of the groove in the first edge region increases along the first direction in the direction extending from the center region to the first edge region, and / or the width of the groove in the second edge region increases along the first direction in the direction extending from the center region to the second edge region.

[0083] like Figure 5 As shown, this application also provides a storage system 1000. The storage system 1000 includes a controller 1200 and a 3D storage device 1100 as described in any of the above embodiments. The controller 1200 is coupled to the 3D storage device 1100 and is used to control the storage of data in the storage device 1100. The 3D storage device 1100 may also include, for example, peripheral circuitry electrically connected to the device structure described in some of the above embodiments.

[0084] For example, the storage system 1000 can be integrated into various types of storage devices, such as being included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones, computers (including but not limited to desktop computers, laptop computers, tablet computers, vehicle computers, etc.), televisions, set-top boxes, game consoles, printers, positioning devices, in-vehicle devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein.

[0085] Optionally, the storage system 1000 can be integrated into a memory card. The memory card includes any of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0086] Optionally, the storage system 1000 can also be integrated into a solid state drive (SSD).

[0087] This application also provides an electronic device. The electronic device includes a storage system 1000 as described in some of the above embodiments. In some embodiments, the electronic device includes at least one of the following: a mobile phone, a computer (including but not limited to desktop computers, laptop computers, tablet computers, vehicle computers, etc.), a server, an in-vehicle device, a wearable device, and a power bank.

[0088] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0089] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A 3D storage device, wherein, Includes a slice storage area, the slice storage area comprising: Layered structure; Multiple grid line gaps penetrate the stacked structure, the multiple grid line gaps are arranged along a first direction, and multiple channel posts penetrating the stacked structure are provided between adjacent grid line gaps. The chip storage area includes a central area and at least one edge area arranged along the first direction. The minimum distance between at least one of the grid line gaps in the at least one edge area and its adjacent channel post is greater than the minimum distance between any one of the grid line gaps in the central area and its adjacent channel post. The minimum distance between the grid line gap and its adjacent channel post refers to the distance between the grid line gap and its nearest channel post along the first direction. 2.The 3D memory device of claim 1, wherein, The chip storage area includes a first edge area and a second edge area located on both sides of the central area. The minimum distance between any one of the gate gaps in the first edge area and / or the second edge area and its adjacent channel post is greater than the minimum distance between any one of the gate gaps in the central area and its adjacent channel post. 3.The 3D memory device of claim 2, wherein, The minimum distance between the grid line gap in the first edge region and its adjacent channel post increases along the direction extending from the center region to the first edge region, and / or the minimum distance between the grid line gap in the second edge region and its adjacent channel post increases along the direction extending from the center region to the second edge region. 4.The 3D memory device of claim 1, wherein, The spacing of at least one group of adjacent gate line gaps in the at least one edge region is greater than the spacing of any group of adjacent gate line gaps in the center region. 5.The 3D memory device of claim 4, wherein, The number of channel posts and the arrangement of channel posts are the same between each group of adjacent grid gaps. 6.The 3D memory device of claim 4, wherein, The chip storage area includes a first edge area and a second edge area located on both sides of the central area. The spacing between any group of adjacent gate line gaps in the first edge area and / or the second edge area is greater than the spacing between any group of adjacent gate line gaps in the central area. 7.The 3D memory device of claim 6, wherein, The spacing between adjacent gate line gaps in the first edge region increases along the direction extending from the center region to the first edge region, and / or the spacing between adjacent gate line gaps in the second edge region increases along the direction extending from the center region to the second edge region. 8.The 3D memory device of claim 4, wherein, The spacing between adjacent grid lines in the central region is equal. 9.The 3D memory device of claim 1, wherein, The width of any one of the gate line gaps located in at least one of the edge regions along the first direction is greater than or equal to the width of any one of the gate line gaps located in the center region along the first direction. 10.The 3D memory device of claim 9, wherein, The chip storage area includes a first edge area and a second edge area located on both sides of the central area. The width of the gate line gap in the first edge area increases along the first direction from the central area to the first edge area, and / or the width of the gate line gap in the second edge area increases along the first direction from the central area to the second edge area. 11.The 3D memory device of claim 1, wherein, The spacing between adjacent gate line gaps in at least one edge region is equal to the spacing between adjacent gate line gaps in the central region, and the spacing between adjacent gate line gaps in the central region is equal. 12.The 3D memory device of claim 11, wherein, The number of channel posts between adjacent grid gaps in at least one edge region decreases along the direction extending from the center region to the edge region. 13.The 3D memory device of claim 1, wherein, The plurality of gate line gaps includes a plurality of first gate line gaps and a plurality of second gate line gaps. The plurality of first gate line gaps divide the chip storage area into a plurality of block storage areas. There are a plurality of second gate line gaps between adjacent first gate line gaps. Each second gate line gap has a notch spaced apart along a second direction. The notch breaks the second gate line gap. The first direction and the second direction intersect. Wherein, the minimum distance between the first grid line gap in the at least one edge region and its adjacent channel post is greater than the minimum distance between the first grid line gap in the center region and its adjacent channel post; or / and, the minimum distance between the second grid line gap in the at least one edge region and its adjacent channel post is greater than the minimum distance between the second grid line gap in the center region and its adjacent channel post.

14. A method of manufacturing a 3D memory device, wherein, include: Forming a layered structure; Forming channel columns that penetrate the stacked structure; Multiple trenches are formed that penetrate the stacked structure, and multiple channel columns are provided between adjacent trenches, the multiple trenches being arranged along a first direction; Multiple grid line gaps throughout the stacked structure are prepared by filling the trenches with material. The chip storage area includes a central area and at least one edge area arranged along the first direction. The minimum distance between at least one trench in the at least one edge area and its adjacent trench post is greater than the minimum distance between any trench in the central area and its adjacent trench post. The minimum distance between a trench and its adjacent trench post refers to the distance between the trench and its nearest trench post along the first direction.

15. The method of claim 14, wherein, The chip storage area includes a first edge area and a second edge area located on both sides of the central area. The minimum distance between any one of the trenches in the first edge area and / or the second edge area and its adjacent trench post is greater than the minimum distance between any one of the trenches in the central area and its adjacent trench post.

16. The method of claim 15, wherein, The minimum distance between the groove in the first edge region and its adjacent groove post increases along the direction of the central region toward the first edge region, and / or the minimum distance between the groove in the second edge region and its adjacent groove post increases along the direction of the central region toward the second edge region.

17. The method of claim 14, wherein, The spacing between at least one group of adjacent trenches in the at least one edge region is greater than the spacing between any group of adjacent trenches in the center region.

18. The method of claim 17, wherein, The chip storage area includes a first edge area and a second edge area located on both sides of the central area. The spacing between any group of adjacent trenches in the first edge area and / or the second edge area is greater than the spacing between any group of adjacent trenches in the central area.

19. The method of claim 18, wherein, The spacing between adjacent grooves in the first edge region increases along the direction of extension from the center region to the first edge region, and / or the spacing between adjacent grooves in the second edge region increases along the direction of extension from the center region to the second edge region.

20. The method of claim 14, wherein, The width of any one of the grooves located in at least one of the edge regions along the first direction is greater than or equal to the width of any one of the grooves located in the center region along the first direction.

21. A storage system, wherein, include: The 3D memory device of any one of claims 1-13; And A controller configured to control the memory device to store data.

22. An electronic device, comprising: A memory system comprising the memory system of claim 21.

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