Semiconductor device and method of manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a metal oxide semiconductor layer, a first gate dielectric layer, a gate, an interlayer dielectric layer, a first conductive oxide layer, a first electrode, and a second electrode. The first gate dielectric layer is located above the metal oxide semiconductor layer. The gate is located above the first gate dielectric layer and overlaps the metal oxide semiconductor layer. The interlayer dielectric layer is located above the gate. The interlayer dielectric layer has a first contact hole. The first contact hole is laterally separated from the metal oxide semiconductor layer. The first conductive oxide layer is located below the first contact hole. The first electrode fills the first contact hole and is electrically connected to the metal oxide semiconductor layer through the first conductive oxide layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Currently, common thin-film transistors usually use amorphous silicon semiconductors as channels. Since amorphous silicon semiconductors have simple manufacturing processes and low costs, they have been widely used in various thin-film transistors.

[0003] With the progress of display technology, the resolution of display panels has been increasing year by year. In order to reduce the size of thin-film transistors in pixel circuits, many manufacturers are committed to researching and developing new semiconductor materials, such as metal oxide semiconductor materials. Metal oxide semiconductor materials have the advantage of high carrier mobility, so they are beneficial to reducing the size of semiconductor devices. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, which can improve the problem of poor contact between electrodes and a metal oxide semiconductor layer.

[0005] At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a metal oxide semiconductor layer, a first gate dielectric layer, a gate, an interlayer dielectric layer, a first conductive oxide layer, a first electrode, and a second electrode. The metal oxide semiconductor layer is located on the substrate. The first gate dielectric layer is located on the metal oxide semiconductor layer. The gate is located on the first gate dielectric layer and overlaps the metal oxide semiconductor layer in the normal direction of the upper surface of the substrate. The interlayer dielectric layer is located on the gate. The interlayer dielectric layer has a first contact hole and a second contact hole. The first contact hole is laterally separated from the metal oxide semiconductor layer. The first conductive oxide layer is located below the first contact hole and is connected to the metal oxide semiconductor layer. The first electrode fills the first contact hole and is electrically connected to the metal oxide semiconductor layer through the first conductive oxide layer. The second electrode fills the second contact hole and is electrically connected to the metal oxide semiconductor layer.

[0006] At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a metal oxide semiconductor layer, a first conductive oxide layer, and a first gate dielectric layer on a substrate, wherein the first conductive oxide layer is connected to the metal oxide semiconductor layer, and the first gate dielectric layer is located on the metal oxide semiconductor layer; forming a gate on the first gate dielectric layer, and the gate overlaps the metal oxide semiconductor layer in the normal direction of the upper surface of the substrate; forming an interlayer dielectric layer on the gate; forming a first contact hole and a second contact hole in the interlayer dielectric layer, and the first conductive oxide layer is located below the first contact hole, wherein the first contact hole is laterally separated from the metal oxide semiconductor layer; forming a first electrode in the first contact hole, and the first electrode is electrically connected to the metal oxide semiconductor layer through the first conductive oxide layer; forming a second electrode in the second contact hole, and the second electrode is electrically connected to the metal oxide semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0008] Figures 2A to 2E is Figure 1 a cross-sectional schematic diagram of the manufacturing method of the semiconductor device;

[0009] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0010] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0011] Figures 5A to 5D is Figure 4 a cross-sectional schematic diagram of the manufacturing method of the semiconductor device;

[0012] Figure 6 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0013] Figure 7 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0014] Figure 8 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0015] SYMBOL DESCRIPTION

[0016] 10A, 10B, 10C, 10E, 10F: Semiconductor device

[0017] 100: Substrate

[0018] 110: Buffer layer

[0019] 112: Silicon nitride layer

[0020] 114: Silicon oxide layer

[0021] 120: First gate dielectric layer

[0022] 130: Second gate dielectric layer

[0023] 140: Interlayer dielectric layer

[0024] D: Second electrode

[0025] G: Gate

[0026] GP1, GP2: Step difference

[0027] H1a, H2a, H1b, H2b: Horizontal distance

[0028] ND: Normal direction

[0029] O1: First opening

[0030] O2: Second opening

[0031] OS: Metal oxide semiconductor layer

[0032] S: First electrode

[0033] T1: First conductive oxide layer

[0034] T1a: First part

[0035] T2: Second conductive oxide layer

[0036] T2a: Second part

[0037] V1: First contact hole

[0038] V2: Second contact hole Detailed implementation manner

[0039] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0040] Please refer to Figure 1 , the semiconductor device 10A includes a substrate 100, a metal oxide semiconductor layer OS, a first gate dielectric layer 120, a gate G, an interlayer dielectric layer 140, a first conductive oxide layer T1, a first electrode S, and a second electrode D. In this embodiment, the semiconductor device 10A further includes a buffer layer 110, a second conductive oxide layer T2, and a second gate dielectric layer 130.

[0041] The material of the substrate 100 can be glass, quartz, organic polymer, or light-blocking / reflective material (e.g., conductive material, metal, wafer, ceramic, or other applicable materials), or other applicable materials. When using conductive material or metal, an insulating layer (not shown) is covered on the substrate 100 to avoid short-circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), or metal foil, or other flexible materials. The buffer layer 110 is located on the substrate 100. The buffer layer 110 is a single-layer or multi-layer structure, and the material of the buffer layer 110 can include silicon oxide, silicon oxynitride, or other suitable materials, or a stacked layer of the above materials. In this embodiment, the buffer layer 110 includes a stacked layer of a silicon nitride layer 112 and a silicon oxide layer 114.

[0042] The metal oxide semiconductor layer OS is located above the substrate 100. In this embodiment, the metal oxide semiconductor layer OS is directly formed on the buffer layer 110. The material of the metal oxide semiconductor layer OS includes quaternary metal compounds such as indium gallium tin zinc oxide (IGTZO) or indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), etc., or oxides composed of ternary metals including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), tungsten (W), or lanthanide rare earth-doped metal oxides (e.g., Ln-IZO).

[0043] The first gate dielectric layer 120 is located above the metal oxide semiconductor layer OS. In this embodiment, the first gate dielectric layer 120 is directly formed on the metal oxide semiconductor layer OS. The first gate dielectric layer 120 has a first opening O1 and a second opening O2 that overlap the metal oxide semiconductor layer OS. In some embodiments, the material of the first gate dielectric layer 120 includes silicon oxide, silicon oxynitride, hafnium oxide, or other suitable materials, or a stacked layer of the above materials.

[0044] The first conductive oxide layer T1 and the second conductive oxide layer T2 are located on the first gate dielectric layer 120 and are connected to the metal oxide semiconductor layer OS. The first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively filled into the first opening O1 and the second opening O2 and contact the upper surface of the metal oxide semiconductor layer OS. In some embodiments, the materials of the first conductive oxide layer T1 and the second conductive oxide layer T2 include transparent conductive oxides, such as indium tin oxide, indium zinc oxide, aluminum zinc oxide, or a stacked layer of at least two of the above.

[0045] In some embodiments, the work functions of the first conductive oxide layer T1 and the second conductive oxide layer T2 are close to the work function of the metal oxide semiconductor layer OS. For example, the energy barriers (potential barriers) between the first conductive oxide layer T1 and the metal oxide semiconductor layer OS and between the second conductive oxide layer T2 and the metal oxide semiconductor layer OS are lower than the energy barrier between a metal electrode (such as a copper electrode) and the metal oxide semiconductor layer OS. In some embodiments, there is an ohmic contact between the first conductive oxide layer T1 and the metal oxide semiconductor layer OS and between the second conductive oxide layer T2 and the metal oxide semiconductor layer OS.

[0046] The second gate dielectric layer 130 is located above the first gate dielectric layer 120 and covers the first conductive oxide layer T1 and the second conductive oxide layer T2. The first conductive oxide layer T1 and the second conductive oxide layer T2 are located between the second gate dielectric layer 130 and the first gate dielectric layer 110. In some embodiments, the material of the second gate dielectric layer 130 includes silicon oxide, silicon oxynitride, hafnium oxide, or other suitable materials or a stacked layer of the above materials.

[0047] The gate G is located above the first gate dielectric layer 120. In this embodiment, the gate G is located on the second gate dielectric layer 130. The gate G overlaps the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100. In some embodiments, the material of the gate G may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or an alloy of any combination of the above metals or a stacked layer of the above metals and / or alloys, but the present invention is not limited thereto. The gate G can also use other conductive materials, such as: nitrides of metals, oxides of metals, oxynitrides of metals, stacked layers of metals and other conductive materials, or other materials with conductive properties.

[0048] The interlayer dielectric layer 140 is located above the gate G and the second gate dielectric layer 130. In some embodiments, the material of the interlayer dielectric layer 140 includes silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, or other suitable materials or a stacked layer of the above materials.

[0049] The interlayer dielectric layer 140 has a first contact hole V1 and a second contact hole V2. In this embodiment, the first contact hole V1 and the second contact hole V2 penetrate through the interlayer dielectric layer 140 and the second gate dielectric layer 130. The first contact hole V1 and the second contact hole V2 are laterally separated from the metal oxide semiconductor layer OS. In other words, the first contact hole V1 and the second contact hole V2 do not overlap the metal oxide semiconductor layer OS in the normal direction ND. The first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located below the first contact hole V1 and the second contact hole V2. The first conductive oxide layer T1 extends from the first contact hole V1 to the first opening O1, and the second conductive oxide layer T2 extends from the second contact hole V2 to the second opening O2.

[0050] The first electrode S and the second electrode D are respectively filled into the first contact hole V1 and the second contact hole V2. The first electrode S is electrically connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1. The second electrode D is electrically connected to the metal oxide semiconductor layer OS through the second conductive oxide layer T2. One of the first electrode S and the second electrode D is the drain, and the other is the source.

[0051] In some embodiments, a first portion T1a of the first conductive oxide layer T1 extends from the first opening O1 towards the gate G, and a second portion T2a of the second conductive oxide layer T2 extends from the second opening O2 towards the gate G. The first portion T1a and the second portion T2a overlap the metal oxide semiconductor layer OS in the normal direction ND, thereby shielding the lateral electric field between the gate G and the first electrode S or between the gate G and the second electrode D, and further reducing the hot carrier effect of the semiconductor device 10A. In some embodiments, the horizontal distance H1a between the first conductive oxide layer T1 and the gate G is less than the horizontal distance H1b between the first opening O1 and the gate G. In some embodiments, the horizontal distance H2b between the second conductive oxide layer T1 and the gate G is less than the horizontal distance H2b between the second opening O2 and the gate G.

[0052] In some embodiments, the materials of the first electrode S and the second electrode D may include metals, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or alloys of any combination of the above metals, or laminates of the above metals and / or alloys. In this embodiment, compared with the metal oxide semiconductor layer OS, the first conductive oxide layer T1 and the second conductive oxide layer T2 are less likely to react with the first electrode S and the second electrode D, thereby avoiding the problem of poor electrical connection between the first electrode S and the metal oxide semiconductor layer OS and between the second electrode D and the metal oxide semiconductor layer OS. For example, if the first electrode S and the second electrode D directly contact the metal oxide semiconductor layer OS, oxygen elements in the metal oxide semiconductor layer OS may diffuse into the first electrode S and the second electrode D, causing oxidation of the first electrode S and the second electrode D; or metal elements in the first electrode S and the second electrode D may diffuse into the metal oxide semiconductor layer OS, creating voids at the interfaces between the first electrode S and the metal oxide semiconductor layer OS and between the second electrode D and the metal oxide semiconductor layer OS.

[0053] Based on the above, the first conductive oxide layer T1 and the second conductive oxide layer T2 can avoid the problem of poor electrical connection between the first electrode S and the metal oxide semiconductor layer OS and between the second electrode D and the metal oxide semiconductor layer OS.

[0054] Figures 2A to 2E is Figure 1 A cross-sectional schematic diagram of a manufacturing method of a semiconductor device.

[0055] Please refer to Figures 2A to 2C and form a metal oxide semiconductor layer OS, a first conductive oxide layer T1, and a second conductive oxide layer T2 on the substrate 100.

[0056] Please first refer to Figure 2A and form a metal oxide semiconductor layer OS on the substrate 100. In this embodiment, the metal oxide semiconductor layer OS is formed on the buffer layer 110.

[0057] Please refer to Figure 2B and form a first gate dielectric layer 120 on the metal oxide semiconductor layer OS. The first gate dielectric layer 120 has a first opening O1 and a second opening O2 that overlap and expose the metal oxide semiconductor layer OS. In some embodiments, the method of forming the first gate dielectric layer 120 includes a photolithography etching process.

[0058] Please refer to Figure 2C, a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on the first gate dielectric layer 120, and the first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located in the first opening O1 and the second opening O2 to connect to the upper surface of the metal oxide semiconductor layer OS. A part of the first conductive oxide layer T1 and a part of the second conductive oxide layer T2 overlap the metal oxide semiconductor layer OS, and another part of the first conductive oxide layer T1 and another part of the second conductive oxide layer T2 do not overlap the metal oxide semiconductor layer OS.

[0059] In some examples, the method of forming the first conductive oxide layer T1 and the second conductive oxide layer T2 includes: forming a conductive oxide layer (not shown) blanketed on the first gate dielectric layer 120; forming a patterned photoresist (not shown) on the conductive oxide layer; etching the conductive oxide layer using the patterned photoresist as a mask to form the mutually separated first conductive oxide layer T1 and second conductive oxide layer T2; and finally, removing the patterned photoresist. In other words, in some embodiments, the first conductive oxide layer T1 and the second conductive oxide layer T2 are the same patterned film layer, and the first conductive oxide layer T1 and the second conductive oxide layer T2 are formed simultaneously.

[0060] Please refer to Figure 2D , a second gate dielectric layer 130 is formed on the first conductive oxide layer T1 and the second conductive oxide layer T2. A gate G is formed on the first gate dielectric layer 120. In this embodiment, the gate G is directly formed on the second gate dielectric layer 130, and the gate G overlaps the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100.

[0061] In some embodiments, using the gate G as a mask, a doping process is performed on the metal oxide semiconductor layer OS to form a source region, a drain region, and a channel region located between the source region and the drain region in the metal oxide semiconductor layer OS, wherein the channel region overlaps the gate G, and the source region and the drain region are doped to have a resistivity lower than that of the channel region. In some embodiments, the doping process includes, for example, a hydrogen plasma process.

[0062] Please refer to Figure 2E, an interlayer dielectric layer 140 is formed on the gate G and the second gate dielectric layer 130. A first contact hole V1 and a second contact hole V2 are formed in the interlayer dielectric layer 140. In the present embodiment, the first contact hole V1 and the second contact hole V2 extend through the interlayer dielectric layer 140 and the second gate dielectric layer 130, and expose the upper surface of the first conductive oxide layer T1 and the upper surface of the second conductive oxide layer T2, respectively. In other words, the first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located below the first contact hole V1 and the second contact hole V2. In some embodiments, the method of forming the first contact hole V1 and the second contact hole V2 includes: forming a patterned photoresist (not shown) on the interlayer dielectric layer 140; etching the interlayer dielectric layer 140 and the second gate dielectric layer 130 using the patterned photoresist as a mask; and finally, removing the patterned photoresist. Since the first contact hole V1 and the second contact hole V2 are laterally separated from the metal oxide semiconductor layer OS, the etching process when etching the interlayer dielectric layer 140 and the second gate dielectric layer 130 will not damage the metal oxide semiconductor layer OS, thereby improving the manufacturing process yield of the semiconductor device.

[0063] Finally, please return Figure 1 A first electrode S is formed in the first contact hole V1, and the first electrode S is electrically connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1. A second electrode D is formed in the second contact hole V2, and the second electrode D is electrically connected to the metal oxide semiconductor layer OS through the second conductive oxide layer T2. At this point, the semiconductor device 10A is substantially completed.

[0064] In some embodiments, the method for forming the first electrode S and the second electrode D includes: forming a conductive layer (not shown) blanketing the interlayer dielectric layer 140; forming a patterned photoresist (not shown) on the conductive layer; etching the conductive layer using the patterned photoresist as a mask to form the first electrode S and the second electrode D separated from each other; and finally, removing the patterned photoresist. In other words, in some embodiments, the first electrode S and the second electrode D are the same patterned film layer and are formed simultaneously.

[0065] Figure 3 FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted that Figure 3 The implementation examples follow Figure 1 The component numbers and partial contents of the embodiments are the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments and will not be repeated here.

[0066] Figure 3The main difference between the semiconductor device 10B and Figure 1 the semiconductor device 10A is that: the semiconductor device 10B further includes an auxiliary conductive oxide layer T3.

[0067] Please refer to Figure 3 , the auxiliary conductive oxide layer T3 is located between the metal oxide semiconductor layer OS and the substrate 100. The resistivity of the auxiliary conductive oxide layer T3 is lower than that of the metal oxide semiconductor layer OS. By providing the auxiliary conductive oxide layer T3, the current magnitude of the semiconductor device 10B can be increased.

[0068] In some embodiments, the material of the auxiliary conductive oxide layer T3 includes a transparent conductive oxide, such as indium tin oxide, indium zinc oxide, aluminum zinc oxide, or a stacked layer of at least two of the above.

[0069] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It should be noted here that Figure 4 the embodiments of Figure 1 adopt the component numbers and partial contents of the embodiments of

[0070] Figure 4 The main difference between the semiconductor device 10C and Figure 1 the semiconductor device 10A is that: the metal oxide semiconductor layer OS of the semiconductor device 10C contacts the upper surface of the first conductive oxide layer T1 and the upper surface of the second conductive oxide layer T2.

[0071] Please refer to Figure 4 , the first conductive oxide layer T1 and the second conductive oxide layer T2 are located on the buffer layer 110. The metal oxide semiconductor layer OS is located on the first conductive oxide layer T1 and the second conductive oxide layer T2. In some embodiments, the first conductive oxide layer T1 and the second conductive oxide layer T2 extend under the gate G. In other words, in the normal direction ND, part of the first conductive oxide layer T1 and part of the second conductive oxide layer T2 are located between the substrate 100 and the gate G.

[0072] The metal oxide semiconductor layer OS extends along the side surface of the first conductive oxide layer T1 to the upper surface of the first conductive oxide layer T1, and the metal oxide semiconductor layer OS has a step GP1 at the side surface of the first conductive oxide layer T1. The gate G overlaps the step GP1 of the metal oxide semiconductor layer OS in the normal direction ND on the upper surface of the substrate 100, thereby reducing the influence of the lateral electric field between the gate G and the first electrode S on the metal oxide semiconductor layer OS.

[0073] The metal oxide semiconductor layer OS extends along the side surface of the second conductive oxide layer T2 to the upper surface of the second conductive oxide layer T2, and the metal oxide semiconductor layer OS has a step GP2 at the side surface of the second conductive oxide layer T2. The gate G overlaps the step GP2 of the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100, thereby reducing the influence of the lateral electric field between the gate G and the second electrode D on the metal oxide semiconductor layer OS.

[0074] In this embodiment, the gate G is formed on the first gate dielectric layer 120, and the first contact hole V1 and the second contact hole V2 penetrate the interlayer dielectric layer 140 and the first gate dielectric layer 120. The first contact hole V1 and the second contact hole V2 are laterally separated from the metal oxide semiconductor layer OS. In other words, the first contact hole V1 and the second contact hole V2 do not overlap the metal oxide semiconductor layer OS in the normal direction ND.

[0075] Figures 5A to 5D Yes Figure 4 A cross-sectional schematic diagram of a manufacturing method of a semiconductor device.

[0076] Please refer to Figure 5A And Figure 5B Form the metal oxide semiconductor layer OS, the first conductive oxide layer T1, and the second conductive oxide layer T2 on the substrate 100.

[0077] Please first refer to Figure 5A Form the first conductive oxide layer T1 and the second conductive oxide layer T2 on the substrate 100. In this embodiment, the first conductive oxide layer T1 and the second conductive oxide layer T2 are formed on the buffer layer 110.

[0078] In some examples, the method of forming the first conductive oxide layer T1 and the second conductive oxide layer T2 includes: forming a conductive oxide layer (not shown) blanketed on the buffer layer 110; forming a patterned photoresist (not shown) on the conductive oxide layer; etching the conductive oxide layer using the patterned photoresist as a mask to form the mutually separated first conductive oxide layer T1 and second conductive oxide layer T2; and finally, removing the patterned photoresist. In other words, in some embodiments, the first conductive oxide layer T1 and the second conductive oxide layer T2 are the same patterned film layer, and the first conductive oxide layer T1 and the second conductive oxide layer T2 are formed simultaneously.

[0079] Please refer to Figure 5B, a metal oxide semiconductor layer OS is formed over the buffer layer 110, the first conductive oxide layer T1, and the second conductive oxide layer T2. In this embodiment, the metal oxide semiconductor layer OS fills the voids between the first conductive oxide layer T1 and the second conductive oxide layer T2. The metal oxide semiconductor layer OS contacts the upper surfaces of the first conductive oxide layer T1 and the second conductive oxide layer T2. A portion of the first conductive oxide layer T1 and a portion of the second conductive oxide layer T2 overlap the metal oxide semiconductor layer OS, and another portion of the first conductive oxide layer T1 and another portion of the second conductive oxide layer T2 do not overlap the metal oxide semiconductor layer OS.

[0080] Please refer to Figure 5C , a first gate dielectric layer 120 is formed over the metal oxide semiconductor layer OS. A gate G is formed over the first gate dielectric layer 120, and the gate G overlaps the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100.

[0081] In some embodiments, using the gate G as a mask, a doping process is performed on the metal oxide semiconductor layer OS to form a source region, a drain region, and a channel region located between the source region and the drain region in the metal oxide semiconductor layer OS, wherein the channel region overlaps the gate G, and the source region and the drain region are doped to have a resistivity lower than that of the channel region. In some embodiments, the doping process includes, for example, a hydrogen plasma process.

[0082] Please refer to Figure 5D , an interlayer dielectric layer 140 is formed over the gate G. A first contact hole V1 and a second contact hole V2 are formed in the interlayer dielectric layer 140. In this embodiment, the first contact hole V1 and the second contact hole V2 extend through the interlayer dielectric layer 140 and the first gate dielectric layer 120 and expose the upper surfaces of the first conductive oxide layer T1 and the second conductive oxide layer T2, respectively. In other words, the first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located below the first contact hole V1 and the second contact hole V2. In some embodiments, the method of forming the first contact hole V1 and the second contact hole V2 includes: forming a patterned photoresist (not shown) over the interlayer dielectric layer 140; etching the interlayer dielectric layer 140 and the first gate dielectric layer 120 using the patterned photoresist as a mask; and finally, removing the patterned photoresist. Since the first contact hole V1 and the second contact hole V2 are laterally separated from the metal oxide semiconductor layer OS, the etching process during the etching of the interlayer dielectric layer 140 and the first gate dielectric layer 120 does not damage the metal oxide semiconductor layer OS, thereby improving the manufacturing yield of the semiconductor device.

[0083] Finally, please go back to Figure 4, a first electrode S is formed in the first contact hole V1, and the first electrode S is electrically connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1. A second electrode D is formed in the second contact hole V2, and the second electrode D is electrically connected to the metal oxide semiconductor layer OS through the second conductive oxide layer T2. Thus, the semiconductor device 10C is substantially completed.

[0084] In some examples, the method of forming the first electrode S and the second electrode D includes: forming a conductive layer (not shown) covering the interlayer dielectric layer 140; forming a patterned photoresist (not shown) on the conductive layer; etching the conductive layer using the patterned photoresist as a mask to form the mutually separated first electrode S and second electrode D; and finally, removing the patterned photoresist. In other words, in some embodiments, the first electrode S and the second electrode D are the same patterned film layer, and the first electrode S and the second electrode D are formed simultaneously.

[0085] Figure 6 is a cross-sectional schematic view of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 6 The embodiments of Figure 4 adopt the component numbers and some contents of the embodiments of

[0086] Figure 6 The main difference between the semiconductor device 10D of Figure 4 and the semiconductor device 10C of

[0087] Please refer to Figure 6 , the auxiliary conductive oxide layer T3 is located between the gate G and the metal oxide semiconductor layer OS. The resistivity of the auxiliary conductive oxide layer T3 is lower than that of the metal oxide semiconductor layer OS. By providing the auxiliary conductive oxide layer T3, the current magnitude of the semiconductor device 10D can be increased.

[0088] In some embodiments, the material of the auxiliary conductive oxide layer T3 includes a transparent conductive oxide, such as indium tin oxide, indium zinc oxide, aluminum zinc oxide, or a stacked layer of at least two of the above.

[0089] Figure 7 is a cross-sectional schematic view of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 7 The embodiments of Figure 1The component numbers and partial contents of the embodiments are the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments and will not be repeated here.

[0090] Figure 7 The semiconductor device 10E and Figure 1 The main difference between the semiconductor device 10A and the semiconductor device 10E is that the metal oxide semiconductor layer OS of the semiconductor device 10E contacts the upper surface of the second conductive oxide layer T2.

[0091] Please refer to Figure 7 The first conductive oxide layer T1 and the second conductive oxide layer T2 are different film layers. The first conductive oxide layer T1 is located between the first gate dielectric layer 120 and the second gate dielectric layer 130, while the second conductive oxide layer T2 is located between the buffer layer 110 and the first gate dielectric layer 120. The first contact hole V1 penetrates the interlayer dielectric layer 140 and the second gate dielectric layer 130, while the second contact hole V2 penetrates the interlayer dielectric layer 140, the second gate dielectric layer 130, and the first gate dielectric layer 120.

[0092] The metal oxide semiconductor layer OS extends along the side surfaces of the second conductive oxide layer T2 to the upper surface of the second conductive oxide layer T2, and the metal oxide semiconductor layer OS has a step GP2 at the side surfaces of the second conductive oxide layer T2. The gate G overlaps the step GP2 of the metal oxide semiconductor layer OS in the normal direction ND to the upper surface of the substrate 100, thereby reducing the effect of the lateral electric field between the gate G and the second electrode D on the metal oxide semiconductor layer OS.

[0093] Figure 8 FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted that Figure 8 The implementation examples follow Figure 1 The component numbers and partial contents of the embodiments are the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments and will not be repeated here.

[0094] Figure 8 The semiconductor device 10F and Figure 1 The main difference between the semiconductor device 10A and the semiconductor device 10F is that the second electrode D of the semiconductor device 10F directly contacts the upper surface of the metal oxide semiconductor layer OS.

[0095] Please refer to Figure 8 In this embodiment, the first electrode S is connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1, and the second electrode D is directly connected to the metal oxide semiconductor layer OS.

Claims

1. A semiconductor device, comprising: a substrate; a metal oxide semiconductor layer located above the substrate; a first gate dielectric layer located above the metal oxide semiconductor layer; a second gate dielectric layer located above the first gate dielectric layer and in direct contact with the first gate dielectric layer; a gate located above the first gate dielectric layer and the second gate dielectric layer and in direct contact with the second gate dielectric layer, and overlapping the metal oxide semiconductor layer in the normal direction of the upper surface of the substrate; an interlayer dielectric layer located above the gate, wherein the interlayer dielectric layer has a first contact hole and a second contact hole, and wherein the first contact hole is laterally separated from the metal oxide semiconductor layer; a first conductive oxide layer located below the first contact hole and connecting the metal oxide semiconductor layer; a first electrode filling the first contact hole and electrically connected to the metal oxide semiconductor layer through the first conductive oxide layer; a second electrode filling the second contact hole and electrically connected to the metal oxide semiconductor layer; a second conductive oxide layer located below the second contact hole and connecting the metal oxide semiconductor layer, wherein the second electrode is electrically connected to the metal oxide semiconductor layer through the second conductive oxide layer; wherein the first gate dielectric layer has a first opening overlapping the metal oxide semiconductor layer, the first conductive oxide layer fills the first opening to contact the upper surface of the metal oxide semiconductor layer, wherein the first gate dielectric layer has a second opening overlapping the metal oxide semiconductor layer, the second conductive oxide layer fills the second opening to contact the upper surface of the metal oxide semiconductor layer; wherein the first conductive oxide layer is located between the second gate dielectric layer and the first gate dielectric layer, the horizontal distance between the first conductive oxide layer and the gate is less than the horizontal distance between the first opening and the gate, a first portion of the first conductive oxide layer extends from the first opening towards the gate and overlaps the metal oxide semiconductor layer in the normal direction, thereby shielding the lateral electric field between the gate and the first electrode; wherein the second conductive oxide layer is located between the second gate dielectric layer and the first gate dielectric layer, the horizontal distance between the second conductive oxide layer and the gate is less than the horizontal distance between the second opening and the gate, a second portion of the second conductive oxide layer extends from the second opening towards the gate and overlaps the metal oxide semiconductor layer in the normal direction, thereby shielding the lateral electric field between the gate and the second electrode; and an auxiliary conductive oxide layer located between the gate and the metal oxide semiconductor layer and in direct contact with the upper surface of the metal oxide semiconductor layer or located between the metal oxide semiconductor layer and the substrate and in direct contact with the lower surface of the metal oxide semiconductor layer, wherein the auxiliary conductive oxide layer and the first conductive oxide layer are located on opposite sides of the metal oxide semiconductor layer, the first gate dielectric layer is located between the gate and the auxiliary conductive oxide layer, and the resistivity of the auxiliary conductive oxide layer is lower than the resistivity of the metal oxide semiconductor layer.

2. A method of manufacturing a semiconductor device, comprising: Form a metal oxide semiconductor layer, a first conductive oxide layer, a second conductive oxide layer, a first gate dielectric layer, and a second gate dielectric layer on a substrate, wherein the first conductive oxide layer and the second conductive oxide layer are connected to the metal oxide semiconductor layer, and the first gate dielectric layer is located on the metal oxide semiconductor layer, and the second gate dielectric layer is located on the first gate dielectric layer and directly contacts the first gate dielectric layer; Form a gate on the first gate dielectric layer and the second gate dielectric layer and directly contact the second gate dielectric layer, and the gate overlaps the metal oxide semiconductor layer in the normal direction of the upper surface of the substrate; Form an interlayer dielectric layer on the gate; Form a first contact hole and a second contact hole in the interlayer dielectric layer, and the first conductive oxide layer is located below the first contact hole, and the second conductive oxide layer is located below the second contact hole, wherein the first contact hole is laterally separated from the metal oxide semiconductor layer; Form a first electrode in the first contact hole, and the first electrode is electrically connected to the metal oxide semiconductor layer through the first conductive oxide layer; and Form a second electrode in the second contact hole, and the second electrode is electrically connected to the metal oxide semiconductor layer through the second conductive oxide layer; Wherein the first gate dielectric layer has a first opening overlapping the metal oxide semiconductor layer, and the first conductive oxide layer fills the first opening to contact the upper surface of the metal oxide semiconductor layer, wherein the first gate dielectric layer has a second opening overlapping the metal oxide semiconductor layer, and the second conductive oxide layer fills the second opening to contact the upper surface of the metal oxide semiconductor layer; Wherein the first conductive oxide layer is located between the second gate dielectric layer and the first gate dielectric layer, and the horizontal distance between the first conductive oxide layer and the gate is less than the horizontal distance between the first opening and the gate, and a first portion of the first conductive oxide layer extends from the first opening toward the gate and overlaps the metal oxide semiconductor layer in the normal direction, thereby shielding the lateral electric field between the gate and the first electrode; Wherein the second conductive oxide layer is located between the second gate dielectric layer and the first gate dielectric layer, and the horizontal distance between the second conductive oxide layer and the gate is less than the horizontal distance between the second opening and the gate, and a second portion of the second conductive oxide layer extends from the second opening toward the gate and overlaps the metal oxide semiconductor layer in the normal direction, thereby shielding the lateral electric field between the gate and the second electrode; And Form an auxiliary conductive oxide layer, wherein the auxiliary conductive oxide layer is located between the gate and the metal oxide semiconductor layer and is in direct contact with the upper surface of the metal oxide semiconductor layer, or is located between the metal oxide semiconductor layer and the substrate and is in direct contact with the lower surface of the metal oxide semiconductor layer. The auxiliary conductive oxide layer and the first conductive oxide layer are located on opposite sides of the metal oxide semiconductor layer. The first gate dielectric layer is located between the gate and the auxiliary conductive oxide layer. The resistivity of the auxiliary conductive oxide layer is lower than the resistivity of the metal oxide semiconductor layer.

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