LDMOS device and method of manufacturing the same

Abstract

The application provides an LDMOS device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, the semiconductor substrate is formed with a first well region and a second well region arranged adjacent to the first well region, a body region is formed in the first well region; forming a source region in the body region; forming a drain region in the second well region, and forming at least one trench type Schottky diode in the drain region; forming a gate structure on the surface of the semiconductor substrate, one side of the gate structure extends to the surface of part of the body region and is arranged adjacent to the source region, and the other side of the gate structure extends to the surface of part of the second well region and has a preset distance from the drain region. The application solves the problem of poor ESD capability of the existing LDMOS device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, in particular to an LDMOS device and a preparation method thereof. BACKGROUND

[0002] High-voltage LDMOS devices are widely used in integrated circuit field as power devices due to their low on-resistance, high operating voltage and low process cost, such as power electronics, LED drivers and automotive electronics. Moreover, high-voltage LDMOS devices are considered to be suitable for protection devices against electrostatic discharge (ESD) phenomenon due to their high breakdown voltage characteristics. However, the existing high-voltage LDMOS devices have poor ESD current capacity and are prone to latch-up effect. SUMMARY

[0003] In view of the above-mentioned shortcomings of the prior art, the present application aims to provide an LDMOS device and a preparation method thereof, which can solve the problem of poor ESD capacity of the existing LDMOS devices.

[0004] To achieve the above-mentioned objects and other related objects, the present application provides a preparation method of an LDMOS device, which comprises the following steps:

[0005] providing a semiconductor substrate, wherein the semiconductor substrate is formed with a first well region and a second well region arranged adjacent to the first well region, and a body region is formed in the first well region;

[0006] forming a source region in the body region;

[0007] forming a drain region in the second well region, and forming at least one trench-type Schottky diode in the drain region;

[0008] forming a gate structure on the surface of the semiconductor substrate, wherein one side of the gate structure extends to the surface of part of the body region and is arranged in close contact with the source region, and the other side of the gate structure extends to the surface of part of the second well region and has a predetermined distance from the drain region.

[0009] Optionally, the method for forming the drain region in the second well region and forming at least one trench-type Schottky diode in the drain region comprises the following steps:

[0010] performing ion implantation in the second well region by using an ion implantation process to form the drain region;

[0011] etching the semiconductor substrate corresponding to the drain region by using an etching process to form at least one trench;

[0012] forming a barrier metal layer on the bottom and sidewall of the trench;

[0013] forming a filling metal layer in the trench.

[0014] Optionally, after the ion implantation is performed in the second well region by using an ion implantation process to form the drain region, and before the semiconductor substrate corresponding to the drain region is etched by using an etching process to form at least one of the trenches, the method further comprises a step of performing a first rapid thermal anneal.

[0015] Optionally, after the barrier metal layer is formed on the bottom and sidewall of the trench, and before the filling metal layer is formed in the trench, the method further comprises a step of performing a second rapid thermal anneal.

[0016] Optionally, the method further comprises a step of forming a buffer region in the second well region, wherein the drain region and the trench-type Schottky diode are formed in the buffer region.

[0017] Optionally, the junction depth of the drain region is less than the depth of the trench.

[0018] Optionally, the method further comprises a step of forming a body region extraction region in the body region, and the body region extraction region is formed on the side of the body region away from the source region.

[0019] Correspondingly, the present application further provides an LDMOS device, which comprises:

[0020] a semiconductor substrate;

[0021] a first well region and a second well region formed in the semiconductor substrate and arranged adjacently;

[0022] a body region formed in the first well region;

[0023] a source region formed in the body region;

[0024] a drain region formed in the second well region;

[0025] at least one Schottky diode formed in the drain region;

[0026] a gate structure formed on the surface of the semiconductor substrate.

[0027] Optionally, the device further comprises a buffer region formed in the second well region, wherein the drain region and the trench-type Schottky diode are arranged in the buffer region.

[0028] Optionally, when the number of the Schottky diodes is multiple, the multiple Schottky diodes are arranged at intervals.

[0029] Optionally, the device further comprises a body region extraction region formed in the body region.

[0030] As described above, the LDMOS device and the preparation method thereof have the following advantages: the LDMOS device has a trench-type Schottky diode formed in the drain region, so that the area of the ion-doped region of the drain region is larger than that of the conventional planar-type drain region, thereby reducing the on-resistance; the partial heavily doped region of the drain region is replaced by the spaced trench-type Schottky diode, so that the ESD self-protection capability of the LDMOS device is improved, and the secondary breakdown current is increased; the introduced Schottky diode can quickly extract the electrons in the well region through the Schottky junction, so that the reverse recovery time is short, the turn-off speed of the device is obviously improved, and the device meets the high-frequency application.

[0031] Element number explanation

[0032] 1, 10 semiconductor substrate

[0033] 2 high-voltage P well region

[0034] 21, 111 body region

[0035] 22, 112 source region

[0036] 3 first high-voltage N well region

[0037] 31 first buffer region

[0038] 32, 121 drain region

[0039] 4 second high-voltage N well region

[0040] 5, 20 gate structure

[0041] 11 first well region

[0042] 111a body region lead-out region

[0043] 12 second well region

[0044] 122 Schottky diode

[0045] 122a trench

[0046] 122b potential barrier metal layer

[0047] 122c filling metal layer

[0048] 123 buffer region

[0049] 30 shallow trench isolation structure

[0050] 40 guard ring

[0051] 41 first guard ring

[0052] 411 first drift region

[0053] 412 first doped region

[0054] 42 second guard ring

[0055] 421 second drift region

[0056] 422 buffer guard region

[0057] 423 second doped region BRIEF DESCRIPTION OF DRAWINGS

[0058] Figure 1 Fig. 1 shows a schematic diagram of a prior art LDMOS device structure.

[0059] Figures 2 to 4 Fig. 3 shows a schematic diagram of a cross-sectional structure of a fabrication process of the LDMOS device of the present application.

[0060] Figure 5 Fig. 4 shows a layout of the LDMOS device of the present application.

[0061] Figure 6 Fig. 5 shows a flow chart of a fabrication method of the LDMOS device of the present application. DETAILED DESCRIPTION

[0062] The present application is herein described, by way of example only, with reference to the accompanying drawings, Details of the application can be seen in the embodiments which follow. The application can be implemented or applied in other different embodiments, and the details in the present description can be modified or changed based on different views and applications, without departing from the spirit of the present application.

[0063] Reference will now be made to the drawings, wherein: Figures 1 to 6 It is to be understood that the above-mentioned arrangements are merely meant to illustrate the present application and are not intended to limit the scope of the present application. Although only the components related to the present application are shown in the drawings, the actual implementation of the present application can include more components, shapes and sizes. The actual implementation of the present application can include more components, shapes and sizes. The layout of the components of the present application can be more complicated.

[0064] Figure 1An LDMOS device structure is provided. The LDMOS device comprises: a semiconductor substrate 1; a high-voltage P-well region 2, a first high-voltage N-well region 3 and a second high-voltage N-well region 4, wherein the high-voltage P-well region 2 is arranged between the first high-voltage N-well region 3 and the second high-voltage N-well region 4, and all of them are formed in the semiconductor substrate 1; a gate structure 5 formed on the surface of the semiconductor substrate 1; a body region 21 formed in the high-voltage P-well region 2; a source region 22 formed in the body region 21; a first buffer region 31 formed in the first high-voltage N-well region 3; and a drain region 32 formed in the first buffer region 31.

[0065] However, the drain region formed by the ion implantation process is a planar structure, the area of the ion doped region is small, and the on-resistance is large, so that the ESD current capacity of the above LDMOS device structure is poor, and the latch-up effect is easy to occur.

[0066] The embodiment provides a preparation method of an LDMOS device, and the method comprises the following steps:

[0067] A semiconductor substrate 10 is provided, the semiconductor substrate 10 is formed with a first well region 11 and a second well region 12 arranged adjacent to the first well region 11, and a body region 111 is formed in the first well region 11.

[0068] A source region 112 is formed in the body region 111.

[0069] A drain region 121 is formed in the second well region 12, and at least one trench type Schottky diode 122 is formed in the drain region 121.

[0070] A gate structure 20 is formed on the surface of the semiconductor substrate 10, one side of the gate structure 20 extends to the surface of part of the body region 111 and is arranged in close contact with the source region 112, and the other side of the gate structure 20 extends to the surface of part of the second well region 12 and has a predetermined distance from the drain region 121.

[0071] The following will be described in combination with Figures 2 to 5 The preparation method of the LDMOS device provided by the embodiment is described.

[0072] As Figure 2 shown, a semiconductor substrate 10 is provided, the semiconductor substrate 10 is formed with a first well region 11 and a second well region 12 arranged adjacent to the first well region 11, and a body region 111 is formed in the first well region 11.

[0073] In this embodiment, the first well region 11 is a high-voltage P-well, formed by implanting P-type ions for doping. The ion doping type of the body region 111 is the same as that of the first well region 11, which is also P-type ion doping. The second well region 12 is a high-voltage N-well, formed by implanting N-type ions for doping. The semiconductor substrate 10 includes, but is not limited to, a silicon substrate.

[0074] like Figure 2 As shown, a source region 112 is formed within the body region 111. In this embodiment, the source region 112 is formed by N-type ion implantation doping.

[0075] like Figures 2 to 4 As shown, a drain region 121 is formed in the second well region 12, and at least one trench-type Schottky diode 122 is formed in the drain region 121.

[0076] Specifically, the method for forming the drain region 121 in the second well region 12 and forming at least one trench-type Schottky diode 122 in the drain region 121 includes: performing ion implantation in the second well region 12 using an ion implantation process to form the drain region 121; etching the semiconductor substrate 10 corresponding to the drain region 121 using an etching process to form at least one trench 122a; forming a barrier metal layer 122b at the bottom and sidewalls of the trench 122a; and forming a filling metal layer 122c in the trench 122a.

[0077] As an example, after ion implantation is performed in the second well region 12 to form the drain region 121, and before etching the semiconductor substrate 10 corresponding to the drain region 121 to form at least one trench 122a, the method includes performing a first rapid thermal annealing step. In this embodiment, after ion implantation, a rapid thermal annealing (RTA) process is used to restore the amorphous structure caused by ion implantation to a complete lattice structure.

[0078] As an example, after forming the barrier metal layer 122b at the bottom and sidewalls of the trench 122a and before forming the fill metal layer 122c within the trench 122a, the method includes performing a second rapid thermal annealing step. In this embodiment, performing a second rapid thermal annealing after forming the barrier metal layer 122b at the bottom and sidewalls of the trench 122a allows for better contact between the barrier metal layer 122b and the semiconductor substrate 10 to form a metal / semiconductor silicon compound.

[0079] As an example, the method further comprises the step of forming a buffer region 123 in the second well region 12, at this time, the drain region 121 and the trench type Schottky diode 122 are formed in the buffer region 123.

[0080] In this embodiment, the buffer region 123 is formed in the second well region 12 by ion implantation process, and the ion doping type of the buffer region 123 is the same as that of the drain region 121, and the junction depth is greater than that of the drain region 121. Moreover, the buffer region 123 and the gate structure 20 have a certain distance therebetween, and a shallow trench isolation structure 30 is formed therebetween, wherein one side of the shallow trench isolation structure 30 extends to part of the lower side of the gate structure 20, and the other side extends into part of the buffer region 123.

[0081] As an example, the junction depth of the drain region 121 is less than the depth of the trench 122a.

[0082] As shown in Figure 2 In this embodiment, the depth of the trench 122a is greater than the junction depth of the drain region 121, and the depth of the trench 122a in this embodiment is greater than 0.3 μm. The barrier metal layer 122b formed at the bottom of the trench 122a forms a barrier contact between the second well region 12 (HVNW) or the buffer region 123 (NW), and the barrier metal layer 122b formed on the sidewall of the trench 122a forms an ohmic contact with the drain region 121 (N-type ion implantation region). Moreover, in the trench 122a, the ratio of the area of the barrier contact to the area of the ohmic contact can be adjusted to achieve the purpose of adjusting the equivalent on-resistance of the LDMOS device. In this embodiment, the area ratio of the two is 1:1. In this embodiment, the addition of the trench type Schottky diode 122 is equivalent to an increase in on-resistance, an improvement in self-protection ESD capability of the LDMOS device, and an increase in secondary breakdown current.

[0083] As shown in Figure 2 The gate structure 20 is formed on the surface of the semiconductor substrate 10, one side of the gate structure 20 extends to part of the surface of the body region 111 and is arranged in close contact with the source region 112, and the other side extends to part of the surface of the second well region 12 and has a predetermined distance from the drain region 121.

[0084] In this embodiment, the gate structure 20 and the drain region 121 are isolated by a shallow trench isolation structure 30, and one side of the shallow trench isolation structure 30 extends to part of the lower side of the gate structure 20. The gate structure 20 includes a gate dielectric layer and a polysilicon layer formed on the surface of the gate dielectric layer (not shown in the figure).

[0085] Specifically, the method further comprises a step of forming a body region lead-out region 111a in the body region 111, and the body region lead-out region 111a is formed on a side of the source region 112 away from the gate structure 20.

[0086] In this embodiment, the ion doping type of the body region lead-out region 111a is the same as that of the body region 111. In this embodiment, the ion doping type of the body region lead-out region 111a is P-type ion doping, and the body region lead-out region 111a is isolated from the source region 112 by a shallow trench isolation structure 30.

[0087] Specifically, the method provided in this embodiment further comprises a step of forming a guard ring 40 surrounding the first well region 11 and the second well region 12 in the semiconductor substrate 10. Specifically, the guard ring 40 comprises a first guard ring 41 and a second guard ring 42. The first guard ring 41 comprises a first drift region 411 and a first doped region 412 formed in the first drift region 411, and the first guard ring 41 is formed on the periphery of the first well region 11 and the second well region 12. The second guard ring 42 comprises a second drift region 421, a buffer protection region 422 formed in the second drift region 421, and a second doped region 423 formed in the buffer protection region 422, and the second guard ring 42 is formed on a side of the first guard ring 41 away from the first well region 11 and the second well region 12.

[0088] In this embodiment, the first drift region 411 and the first doped region 412 of the first guard ring 41 are formed by an ion implantation process, and the types of the doping ions implanted in the first drift region 411 and the first doped region 412 are the same, both being P-type ion doping. The second drift region 421, the buffer protection region 422, and the second doped region 423 of the second guard ring 42 are formed by an ion implantation process, and the ion doping types of the second drift region 421, the buffer protection region 422, and the second doped region 423 are the same, all being N-type ion doping. The first drift region 411 and the second drift region 421 are arranged adjacent to each other and are isolated by a shallow trench isolation structure 30. Moreover, in this embodiment, the ion doping type of the first drift region 411 is the same as that of the first well region 11, so that the first drift region 411 and the first well region 11 can be prepared synchronously in specific preparation. In this embodiment, the guard ring arranged on the periphery of the first well region 11 and the second well region 12 can reduce the latch-up effect.

[0089] Correspondingly, this embodiment further provides an LDMOS device, which comprises:

[0090] a semiconductor substrate 10;

[0091] a first well region 11 and a second well region 12 are formed in the semiconductor substrate 10 and are disposed adjacently;

[0092] a body region 111 is formed in the first well region 11;

[0093] a source region 112 is formed in the body region 111;

[0094] a drain region 121 is formed in the second well region 12;

[0095] at least one Schottky diode 122 is formed in the drain region 121;

[0096] a gate structure 20 is formed on a surface of the semiconductor substrate 10.

[0097] Specifically, the device comprises a buffer region 123 formed in the second well region 12, and the drain region 121 and the Schottky diode 122 are disposed in the buffer region 123.

[0098] Specifically, when the number of the Schottky diodes 122 is plural, the plural Schottky diodes 122 are arranged at intervals.

[0099] Specifically, the device comprises a body region extraction region 111a formed in the body region 111.

[0100] As an example, the device comprises a guard ring 40, which comprises a first guard ring 41 and a second guard ring 42, wherein the first guard ring 41 comprises a first drift region 411 and a first doped region 412 formed in the first drift region 411, and the second guard ring 42 comprises a second drift region 421, a buffer guard region 422 formed in the second drift region 421, and a second doped region 423 formed in the buffer guard region 422.

[0101] As an example, the device further comprises a shallow trench isolation structure 30, which is disposed between the source region 112 and the body region extraction region 111a, between the body region extraction region 111a and the first doped region 412, between the first doped region 412 and the second doped region 423, and between the gate structure 20 and the drain region 121.

[0102] In summary, the LDMOS device and the preparation method thereof have the following advantages: the trench type Schottky diode is formed in the drain region of the LDMOS device, so that the area of the ion doped region of the drain region is larger than that of the traditional planar type drain region, thereby facilitating the reduction of the on-resistance; the partial heavily doped region of the drain region is replaced by the interval trench type Schottky diode, so that the ESD self-protection capability of the LDMOS device is improved, and the secondary breakdown current is also increased; moreover, the introduced Schottky diode can make the electrons in the well region be quickly extracted through the Schottky junction, the reverse recovery time is short, the turn-off speed of the device is obviously improved, and the device meets the high frequency application. Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0103] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of fabricating an LDMOS device, characterized by, The device comprises: providing a semiconductor substrate, the semiconductor substrate being formed with a first well region and a second well region disposed adjacent to the first well region, a body region being formed in the first well region; forming a source region in the body region; forming a drain region in the second well region, and forming at least one trench-type Schottky diode in the drain region; wherein an ohmic contact is formed between a barrier metal layer of a trench sidewall and the drain region, and a barrier contact is formed between a barrier metal layer of a trench bottom and the second well region; or, forming a buffer region in the second well region, the drain region and the trench-type Schottky diode being disposed in the buffer region, an ohmic contact being formed between a barrier metal layer of a trench sidewall and the drain region, and a barrier contact being formed between a barrier metal layer of a trench bottom and the buffer region; forming a gate structure on a surface of the semiconductor substrate, one side of the gate structure extending to a surface of part of the body region and being disposed adjacent to the source region, and the other side of the gate structure extending to a surface of part of the second well region and having a predetermined distance from the drain region.

2. The method of claim 1, wherein, The method for forming the drain region in the second well region and forming at least one trench-type Schottky diode in the drain region comprises: performing ion implantation on the second well region by using an ion implantation process to form the drain region; etching the semiconductor substrate corresponding to the drain region by using an etching process to form at least one trench; forming a barrier metal layer on a bottom and a sidewall of the trench; forming a filling metal layer in the trench.

3. The method of claim 2, wherein the LDMOS device is formed by: After performing ion implantation on the second well region by using an ion implantation process to form the drain region, and before etching the semiconductor substrate corresponding to the drain region by using an etching process to form at least one trench, the method comprises a step of performing a first rapid thermal annealing.

4. The method of claim 3, wherein the LDMOS device is formed by: After forming the barrier metal layer on the bottom and the sidewall of the trench, and before forming the filling metal layer in the trench, the method comprises a step of performing a second rapid thermal annealing.

5. The method of claim 1 to 4, wherein The junction depth of the drain region is smaller than the depth of the trench.

6. The method of claim 1, wherein, The method further comprises a step of forming a body region lead-out region in the body region, and the body region lead-out region is formed on a side of the source region away from the gate structure.

7. An LDMOS device, characterized by, The device comprises: a semiconductor substrate; a first well region and a second well region formed in the semiconductor substrate and disposed adjacent to each other; a body region formed in the first well region; a source region formed in the body region; a drain region formed in the second well region; the drain region is formed with at least one trench-type Schottky diode; wherein an ohmic contact is formed between a barrier metal layer of a trench sidewall and the drain region, and a barrier contact is formed between a barrier metal layer of a trench bottom and the second well region; or, a buffer region is formed in the second well region, the drain region and the trench-type Schottky diode being disposed in the buffer region, an ohmic contact being formed between a barrier metal layer of a trench sidewall and the drain region, and a barrier contact being formed between a barrier metal layer of a trench bottom and the buffer region; a gate structure formed on a surface of the semiconductor substrate.

8. The LDMOS device of claim 7, wherein, When the number of the Schottky diodes is multiple, the multiple Schottky diodes are arranged at intervals.

9. The LDMOS device of claim 7, wherein, The device comprises a body region lead-out region formed in the body region.

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