Structure and method for improving the gidl effect of mv devices

Abstract

The application discloses a structure for improving GIDL effect of MV device, which comprises a first gate structure formed by stacking a first gate dielectric layer and a first gate conductive material layer. A first layer of side wall is formed on the side of the first gate conductive material layer. A source-drain recess is formed on the semiconductor substrate and self-aligned with the outer side of the first layer of side wall. A second layer of side wall is self-aligned formed on the outer side of the first layer of side wall and the inner side of the source-drain recess. A source-drain region is formed in the semiconductor substrate exposed on the bottom surface of the source-drain recess and self-aligned with the outer side of the second layer of side wall. The application also discloses a method for improving GIDL effect of MV device. The application can reduce GIDL leakage current of MV device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a structure for improving the gate-induced drain leakage (GIDL) effect of medium-voltage (MV) devices; this invention also relates to a method for improving the GIDL effect of MV devices. Background Technology

[0002] Gate-induced drain leakage current (GIDL) is the primary off-state leakage mechanism of MOSFETs. With the advancement of semiconductor technology, MOSFET dimensions are continuously shrinking, and the thickness of the polysilicon gate oxide layer is becoming increasingly thinner. This leads to an exponential increase in gate-to-drain leakage current, severely impacting device reliability.

[0003] When the MOSFET gate is off and the drain is connected to voltage, the energy band near the interface of the overlap between the drain impurity diffusion layer and the gate undergoes strong bending, forming an inversion layer on the surface. The depletion layer becomes particularly narrow, leading to band-to-band tunneling (BTBT) between conduction band electrons and valence band holes, resulting in drain leakage current. Solving the GIDL effect will contribute to the development and application of semiconductor input / output (I / O) devices.

[0004] The traditional approach to address the GIDL effect is to adjust the doping process to improve the interface morphology at the overlap between the drain and gate. However, existing process solutions are not yet mature, resulting in unstable device performance.

[0005] like Figures 1A-1C The diagram shows the device structure in each step of a conventional method for improving the GIDL effect of MV devices. Typically, in high-voltage (HV) products, low-voltage (LV), MV, and HV devices are integrated simultaneously. MV devices usually function as input / output (I / O) devices. The operating voltage and withstand voltage of the LV, MV, and HV devices increase sequentially. The existing manufacturing method for MV devices, when integrated with LV and HV devices, is explained below. The manufacturing process steps for MV devices in conventional methods for improving the GIDL effect include:

[0006] Step 1, such as Figure 1A As shown, a first gate structure is formed on a semiconductor substrate 101. The first gate structure is formed by stacking a first gate dielectric layer 103 and a first gate conductive material layer 104 formed on the surface of the semiconductor substrate 101.

[0007] Typically, the semiconductor substrate 101 includes a silicon substrate.

[0008] The material of the first gate dielectric layer 103 includes oxide.

[0009] The first gate conductive material layer 104 includes polysilicon gate.

[0010] A shallow trench isolation 102 is also formed on the semiconductor substrate 101.

[0011] The gate structure of the LV device and the gate structure of the HV device are also formed at the same time when the first gate structure of the MV device is formed.

[0012] Figure 1A In particular, the gate dielectric layer (not shown) of the gate structure of the LV device is thinner, such as thinner than the first gate dielectric layer 103, and the gate conductive material layer is polysilicon gate 104l.

[0013] The gate dielectric layer 103h of the gate structure of the HV device is thicker, such as thicker than the first gate dielectric layer 103, and the gate conductive material layer is polysilicon gate 104h. The polysilicon gate 104l is also denoted as LV, the polysilicon gate 104h is also denoted as HV, and the polysilicon gate 104 is also denoted as MV. The polysilicon gate 104l, 104, and 104h can be formed at the same time by using the same process, such as polysilicon deposition plus photolithography definition plus etching.

[0014] Step two, as shown in FIG. 1C, a first layer of side wall (SPA1) 1051 is formed on the side of the first gate conductive material layer 104. Figure 1A

[0015] The material of the first layer of side wall 1051 includes silicon nitride. Typically, the thickness of the first layer of side wall 1051 is thin, and a layer of silicon nitride can be deposited by using ALD process, and then the layer of silicon nitride is etched to form the first layer of side wall 1051.

[0016] Step three, as shown in FIG. 1D, a second layer of side wall (SPA2) 1052 is formed on the outer side of the first layer of side wall 1051 and the inner side of the source / drain recess 301 self-aligned. Figure 1B

[0017] Typically, the second layer of side wall 1052 is formed by stacking an oxide layer 1052a and a silicon nitride layer 1052b. The whole side wall is formed by stacking the first layer of side wall 1051 and the second layer of side wall 1052.

[0018] Step four, as shown in FIG. 1E, a gate dielectric layer 103g is formed on the second layer of side wall 1052. Figure 1C ​​As shown, the photoresist 106 pattern formed by photolithography opens the formation area of ​​the MV device, and the first gate dielectric layer 103 outside the second sidewall 1052 is removed by an etching process with the outer surface of the second sidewall 1052 as the self-alignment condition, as indicated by mark 107.

[0019] Typically, an IOR mask is used to define the 106 pattern of the photoresist.

[0020] Step 5, as follows Figure 2 As shown, source / drain injection is performed in the semiconductor substrate 101 to form source / drain regions 109 with the outer surface of the second layer sidewall 1052 as the self-alignment condition.

[0021] Typically, the region corresponding to the formation of the MV device, such as Figure 2 As shown, after step two is completed and before step three is performed, the following steps are also included:

[0022] Lightly doped drain regions 108 are formed in the semiconductor substrate 101 outside the first layer sidewall 1051 by performing lightly doped drain implantation with the outer surface of the first layer sidewall 1051 as the self-alignment condition.

[0023] The lightly doped drain region 108 is formed by annealing and diffusion of the implantation region. After annealing and diffusion, the lightly doped drain region 108 extends laterally to the bottom of the first gate conductive material layer 104 and overlaps with it.

[0024] The junction depth of the lightly doped drain region 108 is greater than the junction depth of the source / drain region 109, so the source / drain region 109 is located in the lightly doped drain region 108.

[0025] In the formation region of the LV device, the LV device also forms a lightly doped drain region and a source / drain region. Typically, the junction depth of the source / drain region of the LV device is greater than the junction depth of the lightly doped drain region.

[0026] In the formation region of the HV device, the polysilicon gate 104h also extends to the surface of the shallow trench isolation 102 on both sides, and a drift region is also formed between the source / drain region and the channel region. The junction depth of the drift region is greater than the depth of the shallow trench isolation 102. The combination of the drift region and the shallow trench isolation 102 results in a larger withstand voltage, thereby enabling high-voltage operation.

[0027] Formed by existing methods Figure 2 The MV device shown is prone to generating large GIDL leakage current.

[0028] like Figure 3 As shown, is Figure 2 The diagram shows a simulation of the impact ionization of an existing MV device. Figure 3In the figure, the first gate dielectric layer is indicated by reference numeral 103a alone, the side wall is indicated by reference numeral 105a alone, and the region shown by the dashed circle 401 is the region of maximum collision ionization and also the region of maximum electric field intensity. It can be seen that the dashed circle 401 is located at the interface between the first gate dielectric layer 103a and the semiconductor substrate at the bottom, and thus GIDL leakage is easily generated. SUMMARY

[0029] The technical problem to be solved by the present application is to provide a structure for improving the GIDL effect of an MV device, so as to reduce the GIDL leakage current of the MV device. To this end, the present application also provides a method for improving the GIDL effect of an MV device.

[0030] To solve the above technical problem, the present application provides a structure for improving the GIDL effect of an MV device, wherein the MV device comprises:

[0031] A first gate structure is formed by stacking a first gate dielectric layer and a first gate conductive material layer on the surface of a semiconductor substrate.

[0032] A first layer of side walls is formed on the side of the first gate conductive material layer.

[0033] In the formation region of the MV device, a source-drain recess is formed on the semiconductor substrate, the inner side of the source-drain recess is self-aligned with the outer side of the first layer of side walls, and the source-drain recess is formed by removing the first gate dielectric layer and the semiconductor substrate in the source-drain recess formation region.

[0034] A second layer of side walls is self-aligned to the outer side of the first layer of side walls and the inner side of the source-drain recess.

[0035] A source-drain region is formed in the semiconductor substrate exposed on the bottom surface of the source-drain recess, and the source-drain region is self-aligned to the outer side of the second layer of side walls.

[0036] The depth of the source-drain recess is used to set the spacing between the source-drain region and the first gate conductive material layer, and by increasing the depth of the source-drain recess, the spacing between the source-drain region and the first gate conductive material layer is increased, thereby reducing GIDL leakage.

[0037] Further improvement is that the semiconductor substrate comprises a silicon substrate.

[0038] Further improvement is that the material of the first gate dielectric layer comprises an oxide layer.

[0039] Further improvement is that the first gate conductive material layer comprises a polysilicon gate.

[0040] A further improvement is that the material of the first layer of side wall comprises silicon nitride.

[0041] A further improvement is that a lightly doped drain region is further formed on the semiconductor substrate; the lightly doped drain region is formed by annealing and diffusion of an implantation region of the lightly doped drain region, the implantation region of the lightly doped drain region is self-aligned to the semiconductor substrate at the side of the first layer of side wall; the annealing and diffusion of the lightly doped drain region laterally extends to the bottom of the first gate conductive material layer and overlaps.

[0042] A further improvement is that the junction depth of the lightly doped drain region is greater than the depth of the source-drain recess, and the source-drain region formed at the bottom of the source-drain recess is still located in the lightly doped drain region.

[0043] A further improvement is that the depth of the source-drain recess in the semiconductor substrate is

[0044] To solve the above technical problems, the method for improving the GIDL effect of the MV device provided by the application comprises the following steps:

[0045] Step one, forming a first gate structure on a semiconductor substrate, the first gate structure is formed by stacking a first gate dielectric layer and a first gate conductive material layer on the surface of the semiconductor substrate.

[0046] Step two, forming a first layer of side wall on the side of the first gate conductive material layer.

[0047] Step three, opening the formation area of the MV device, and sequentially etching the first gate dielectric layer and the semiconductor substrate by using an etching process with the first layer of side wall as a self-alignment condition to form a source-drain recess, the inner side of the source-drain recess and the outer side of the first layer of side wall are self-aligned.

[0048] Step four, forming a second layer of side wall on the outer side of the first layer of side wall and the inner side of the source-drain recess.

[0049] Step five, performing source-drain implantation with the outer side of the second layer of side wall as a self-alignment condition to form a source-drain region in the semiconductor substrate exposed on the bottom surface of the source-drain recess; the depth of the source-drain recess is used to set the spacing between the source-drain region and the first gate conductive material layer, and the spacing between the source-drain region and the first gate conductive material layer is increased by increasing the depth of the source-drain recess, so as to reduce the GIDL leakage.

[0050] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0051] A further improvement is that the material of the first gate dielectric layer comprises an oxide layer.

[0052] A further improvement is that the first gate conductive material layer comprises polysilicon gate.

[0053] A further improvement is that the material of the first layer of side wall comprises silicon nitride.

[0054] A further improvement is that after the completion of step two and before step three, the method further comprises:

[0055] performing a lightly doped drain implant to form an implant region of a lightly doped drain region in the semiconductor substrate outside the first layer of side wall with the outer side of the first layer of side wall as a self-alignment condition.

[0056] performing annealing diffusion on the implant region of the lightly doped drain region to form the lightly doped drain region, and the lightly doped drain region after annealing diffusion laterally extends to the bottom of the first gate conductive material layer and overlaps.

[0057] A further improvement is that the junction depth of the lightly doped drain region is greater than the depth of the source / drain recess, and the source / drain region formed at the bottom of the source / drain recess is still located in the lightly doped drain region.

[0058] A further improvement is that the depth of the source / drain recess in the semiconductor substrate is

[0059] The present application forms a source / drain recess self-aligned with the first layer of side wall, so that the source / drain region is formed in the semiconductor substrate exposed at the bottom surface of the source / drain recess, which increases the distance between the source / drain region and the first gate conductive material layer of the MV device, thereby reducing the GIDL leakage.

[0060] In addition, in the method of the present application, the source / drain recess of the MV device can be defined by the mask used to remove the first gate dielectric layer in the existing method, so that the process cost is not increased. BRIEF DESCRIPTION OF DRAWINGS

[0061] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0062] Figures 1A-1C is a schematic diagram of the structure of the device in each step of the manufacturing method of the existing high-voltage (HV) product simultaneously integrating LV, MV and HV devices;

[0063] Figure 2 is a schematic diagram of the structure of the existing MV device formed by the manufacturing method of the existing HV product simultaneously integrating LV, MV and HV devices;

[0064] Figure 3 is Figure 2 is a simulation schematic diagram of the impact ionization of the existing MV device shown in

[0065] Figure 4 This is a schematic diagram of the structure for improving the GIDL effect of the MV device according to an embodiment of the present invention;

[0066] Figures 5A-5C This is a schematic diagram of the device structure in each step of the method for improving the GIDL effect of MV devices according to an embodiment of the present invention;

[0067] Figure 6A In the structure of the embodiment of the present invention that improves the GIDL effect of MV devices, the depth of the source / drain trench in the semiconductor substrate is [insert depth here]. A simulation diagram of device collision ionization during the event;

[0068] Figure 6B In the structure of the embodiment of the present invention that improves the GIDL effect of MV devices, the depth of the source / drain trench in the semiconductor substrate is [insert depth here]. A simulation diagram of device collision ionization during the event;

[0069] Figure 7 In the structure of the embodiment of the present invention that improves the GIDL effect of MV devices, the depth of the source / drain trench in the semiconductor substrate is [insert depth here]. GIDL leakage current curves for 400 and existing MV devices. Detailed Implementation

[0070] like Figure 4 The diagram shown is a schematic representation of a structure for improving the GIDL effect of an MV device according to an embodiment of the present invention. In the structure for improving the GIDL effect of an MV device according to an embodiment of the present invention, the MV device includes:

[0071] The first gate structure is formed by stacking a first gate dielectric layer 203 and a first gate conductive material layer 204 formed on the surface of a semiconductor substrate 201.

[0072] In this embodiment of the invention, the semiconductor substrate 201 includes a silicon substrate.

[0073] The material of the first gate dielectric layer 203 includes an oxide layer.

[0074] The first gate conductive material layer 204 includes a polysilicon gate.

[0075] A first sidewall 2051 is formed on the side of the first gate conductive material layer 204.

[0076] In this embodiment of the invention, the material of the first sidewall 2051 includes silicon nitride.

[0077] In the formation region of the MV device, a source-drain recess 301 is formed in the semiconductor substrate 201, the inner side of the source-drain recess 301 is self-aligned with the outer side of the first layer side wall 2051, and the source-drain recess 301 is formed by removing the first gate dielectric layer 203 and the semiconductor substrate 201 in the source-drain recess 301 formation region.

[0078] A second layer side wall 2052 is self-aligned formed on the outer side of the first layer side wall 2051 and the inner side of the source-drain recess 301. The side wall 205 is formed by the first layer side wall 2051 and the second layer side wall 2052.

[0079] A source-drain region 209 is formed in the semiconductor substrate 201 exposed by the bottom surface of the source-drain recess 301, and the source-drain region 209 is self-aligned with the outer side of the second layer side wall 2052. In the embodiment of the present application, the source-drain region 209 is a symmetrical structure, and the source region and the drain region are determined according to the connection relationship in actual use.

[0080] The depth of the source-drain recess 301 is used to set the distance between the source-drain region 209 and the first gate conductive material layer 204, and the distance between the source-drain region 209 and the first gate conductive material layer 204 is increased by increasing the depth of the source-drain recess 301, thereby reducing the GIDL leakage.

[0081] In the embodiment of the present application, a lightly doped drain region 208 is further formed on the semiconductor substrate 201; the lightly doped drain region 208 is formed by annealing and diffusion of the implantation region of the lightly doped drain region 208, the implantation region of the lightly doped drain region 208 is self-aligned formed in the semiconductor substrate 201 at the side of the first layer side wall 2051, and the annealing and diffusion of the lightly doped drain region 208 laterally extends to the bottom of the first gate conductive material layer 204 and overlaps.

[0082] The junction depth of the lightly doped drain region 208 is greater than the depth of the source-drain recess 301, and the source-drain region 209 formed at the bottom of the source-drain recess 301 is still located in the lightly doped drain region 208.

[0083] The depth of the source-drain recess 301 in the semiconductor substrate 201 is

[0084] In the embodiment of the present application, the source-drain recess 301 self-aligned with the first layer side wall 2051 is formed, the source-drain region 209 is formed in the semiconductor substrate 201 exposed by the bottom surface of the source-drain recess 301, so that the distance between the source-drain region 209 and the first gate conductive material layer 204 of the MV device is increased, thereby reducing the GIDL leakage.

[0085] AsFigures 5A-5C As shown in the figure, it is the device structure in each step of the method for improving the GIDL effect of the MV device; generally, in the HV product, the LV device, the MV device and the HV device are integrated at the same time, the MV device is used as the input and output (IO) device, the working voltage and the voltage resistance of the LV device, the MV device and the HV device are increased in turn, and the manufacturing method of the MV device of the embodiment of the application is described in combination with the LV device and the HV device, in the method for improving the GIDL effect of the MV device, the manufacturing process steps of the MV device include:

[0086] Step one, as shown in the figure, a first gate structure is formed on the semiconductor substrate 201, and the first gate structure is formed by stacking the first gate dielectric layer 203 and the first gate conductive material layer 204 formed on the surface of the semiconductor substrate 201. Figure 5A

[0087] In the method of the embodiment of the application, the semiconductor substrate 201 includes a silicon substrate.

[0088] The material of the first gate dielectric layer 203 includes an oxide layer.

[0089] The first gate conductive material layer 204 includes a polysilicon gate.

[0090] The shallow trench isolation 202 is also formed on the semiconductor substrate 201.

[0091] At the same time of forming the first gate structure of the MV device, the gate structure of the LV device and the gate structure of the HV device are also formed.

[0092] Figure 5A In the method, the gate dielectric layer (not shown) of the gate structure of the LV device is relatively thin, and the gate conductive material layer adopts the polysilicon gate 204l.

[0093] The gate dielectric layer 203h of the gate structure of the HV device is relatively thick, and the gate conductive material layer adopts the polysilicon gate 204h. The polysilicon gate 204l also adopts LV, the polysilicon gate 204h also adopts HV, and the polysilicon gate 204 also adopts MV. The polysilicon gates 204l, 204 and 204h can be formed at the same time by using the same process, such as polysilicon deposition, photolithography definition and etching.

[0094] Step two, as shown in the figure, a first layer of side wall 2051 is formed on the side of the first gate conductive material layer 204. The step of forming the first layer of side wall 2051 is also represented by SPA1. Figure 5A

[0095] ​​The material of the first layer of side wall 2051 includes silicon nitride. Generally, the thickness of the first layer of side wall 2051 is thin, and a layer of silicon nitride can be deposited by ALD process, and then etched to form the first layer of side wall 2051.

[0096] Step three, as shown in the figure, a photoresist 206 pattern is formed by photolithography process to open the forming area of the MV device, and the first gate dielectric layer 203 and the semiconductor substrate 201 are etched in sequence by an etching process with the first layer of side wall 2051 as a self-alignment condition, to form a source-drain recess 301, and the inner side of the source-drain recess 301 is self-aligned with the outer side of the first layer of side wall 2051. Figure 5B

[0097] In the method of the embodiment of the present application, the mask for defining the photoresist 206 pattern is the IOR mask for removing the first gate dielectric layer of the MV device in the prior art. Figure 5B In the figure, IOR for Si recess also represents the step of forming the source-drain recess 301, wherein Si recess represents the silicon recess, i.e. the source-drain recess 301.

[0098] Comparing with Figure 1C and Figure 5B As shown in the figure, in the method of the embodiment of the present application, the source-drain recess 301 of the MV device can be defined by the IOR mask in the prior art for removing the first gate dielectric layer of the MV device, so that the process cost is not increased. Figure 1C

[0099] Step four, as shown in the figure, a second layer of side wall 2052 is formed on the outer side of the first layer of side wall 2051 and the inner side of the source-drain recess 301. Figure 5C

[0100] In the method of the embodiment of the present application, the second layer of side wall 2052 is generally formed by stacking an oxide layer 2052a and a silicon nitride layer 2052b. The whole side wall is formed by stacking the first layer of side wall 2051 and the second layer of side wall 2052.

[0101] Step five, as shown in the figure, source-drain implantation is performed with the outer side of the second layer of side wall 2052 as a self-alignment condition, to form a source-drain region 209 in the semiconductor substrate 201 exposed on the bottom surface of the source-drain recess 301; the depth of the source-drain recess 301 is used to set the spacing between the source-drain region 209 and the first gate conductive material layer 204, and the spacing between the source-drain region 209 and the first gate conductive material layer 204 is increased by increasing the depth of the source-drain recess 301, so as to reduce the GIDL leakage. Figure 4 ​​​​

[0102] In the method of the embodiment of the present application, the formation region of the MV device is, as shown in the figure, after the completion of step two and before step three, further comprising: Figure 4

[0103] The light-doped drain region 208 is formed by performing a light-doped drain implantation in the semiconductor substrate 201 outside the first layer of sidewall 2051, with the outer side of the first layer of sidewall 2051 as a self-alignment condition.

[0104] The light-doped drain region 208 is formed by annealing and diffusion of the implantation region of the light-doped drain region 208, and the light-doped drain region 208 after annealing and diffusion will laterally extend to the bottom of the first gate conductive material layer 204 and overlap.

[0105] The junction depth of the light-doped drain region 208 is greater than the depth of the source / drain recess 301, and the source / drain region 209 formed at the bottom of the source / drain recess 301 is still located in the light-doped drain region 208.

[0106] The depth of the source / drain recess 301 in the semiconductor substrate 201 is

[0107] In the formation region of the LV device, the LV device also forms a light-doped drain region and a source / drain region, and generally, the junction depth of the source / drain region of the LV device is greater than the junction depth of the light-doped drain region.

[0108] In the formation region of the HV device, the polysilicon gate 204h also extends to the surface of the shallow trench isolation 202 on both sides, and a drift region is formed between the source / drain region and the channel region, the junction depth of the drift region is greater than the depth of the shallow trench isolation 202, and a larger withstand voltage is obtained by combining the drift region and the shallow trench isolation 202, thereby enabling high-voltage operation.

[0109] As shown in the figure, the depth of the source / drain recess in the semiconductor substrate in the structure for improving the GIDL effect of the MV device of the embodiment of the present application is Figure 6A When the device collision ionization simulation diagram is as shown in the figure. In the structure for improving the GIDL effect of the MV device of the embodiment of the present application, the first gate dielectric layer is separately denoted by reference numeral 203a, the sidewall is separately denoted by reference numeral 205a, the source / drain recess is separately denoted by reference numeral 301a, and the region shown by the dashed circle 402 is the maximum collision ionization, which also corresponds to the region with the maximum electric field intensity. Figure 6A Compared with the region shown by the dashed circle 401, the dashed circle 402 is away from the junction between the first gate dielectric layer 203a and the bottom semiconductor substrate, and the GIDL leakage through the first gate dielectric layer 203a to the polysilicon gate will inevitably be reduced. Figure 3 ​​

[0110] Figure 6B is the depth of the source-drain recess in the semiconductor substrate in the structure of the embodiment of the present application for improving the GIDL effect of the MV device is a simulation diagram of the device impact ionization when the depth of the source-drain recess in the semiconductor substrate is Figure 6B In the figure, the first gate dielectric layer is individually indicated by a label 203b, the sidewall is individually indicated by a label 205b, the source-drain recess is individually indicated by a label 301b, and the area shown by a dashed circle 403 is the maximum impact ionization and also corresponds to the area with the maximum electric field intensity. Figure 3 Compared with the area shown by the dashed circle 401, the area of the dashed circle 403 does not overlap the first gate dielectric layer 203a, and the leakage through the first gate dielectric layer 203b to the poly-silicon gate, i.e. the GIDL leakage, will inevitably be reduced.

[0111] As shown in Figure 7 is the depth of the source-drain recess in the semiconductor substrate in the structure of the embodiment of the present application for improving the GIDL effect of the MV device and the GIDL leakage current curve of the existing MV device; Figure 7 In the figure, the curve 501 corresponds to the GIDL leakage current curve of the existing MV device, the curve 502 corresponds to the GIDL leakage current curve of the MV device when the depth of the source-drain recess in the semiconductor substrate is Figure 6A as shown in the figure , and the curve 503 corresponds to the GIDL leakage current curve of the MV device when the depth of the source-drain recess in the semiconductor substrate is Figure 6B as shown in the figure , and the GIDL leakage current is the current when the device is turned off, i.e. Ioff. It can be seen that the take off point of the Ioff of the MV device is improved by nearly 1V, and the source-drain recess can effectively reduce the electric field between the gate and the drain region.

[0112] The present application has been described in detail by specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can make many modifications and improvements without departing from the principles of the present application, and these should also be considered as falling within the scope of protection of the present application.

Claims

1. A structure for improving the GIDL effect of an MV device, characterized in that, MV devices include: The first gate structure is formed by stacking a first gate dielectric layer and a first gate conductive material layer formed on the surface of a semiconductor substrate. A first sidewall is formed on the side of the first gate conductive material layer; In the formation region of the MV device, a source / drain groove is formed on the semiconductor substrate. The inner side surface of the source / drain groove and the outer side surface of the first layer sidewall are self-aligned. The source / drain groove is formed by removing the first gate dielectric layer and the semiconductor substrate in the formation region of the source / drain groove. The second layer of sidewalls is self-aligned and formed on the outer surface of the first layer of sidewalls and the inner surface of the source / drain groove; The source / drain regions are formed in the semiconductor substrate exposed on the bottom surface of the source / drain recess, and the source / drain regions and the outer surfaces of the second layer sidewalls are self-aligned; The depth of the source / drain groove is used to set the spacing between the source / drain region and the first gate conductive material layer. Increasing the depth of the source / drain groove increases the spacing between the source / drain region and the first gate conductive material layer, thereby reducing GIDL leakage.

2. The structure for improving the GIDL effect of an MV device as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

3. The structure for improving the GIDL effect of an MV device as described in claim 2, characterized in that: The material of the first gate dielectric layer includes an oxide layer.

4. The structure for improving the GIDL effect of an MV device as described in claim 3, characterized in that: The first gate conductive material layer includes a polysilicon gate.

5. The structure for improving the GIDL effect of an MV device as described in claim 4, characterized in that: The material of the first layer of sidewalls includes silicon nitride.

6. The structure for improving the GIDL effect of an MV device as described in claim 5, characterized in that: A lightly doped drain region is also formed on the semiconductor substrate; the lightly doped drain region is formed by annealing and diffusion of the implantation region of the lightly doped drain region, the implantation region of the lightly doped drain region is aligned with the sidewall of the first layer of the semiconductor substrate, and the lightly doped drain region after annealing and diffusion will extend laterally to the bottom of the first gate conductive material layer and overlap.

7. The structure for improving the GIDL effect of an MV device as described in claim 6, characterized in that: The junction depth of the lightly doped drain region is greater than the depth of the source / drain groove, and the source / drain region formed at the bottom of the source / drain groove is still located in the lightly doped drain region.

8. The structure for improving the GIDL effect of an MV device as described in claim 1 or 7, characterized in that: The depth of the source / drain trench in the semiconductor substrate is:

9. A method for improving the GIDL effect of an MV device, characterized in that, The manufacturing process steps for MV devices include: Step 1: Form a first gate structure on a semiconductor substrate. The first gate structure is formed by stacking a first gate dielectric layer and a first gate conductive material layer formed on the surface of the semiconductor substrate. Step 2: Form a first sidewall on the side of the first gate conductive material layer; Step 3: Open the formation area of ​​the MV device, and use an etching process with the first layer sidewall as the self-alignment condition to etch the first gate dielectric layer and the semiconductor substrate in sequence to form source and drain grooves. The inner side surface of the source and drain grooves and the outer side surface of the first layer sidewall are self-aligned. Step 4: Form a second sidewall by self-aligning the outer side of the first sidewall and the inner side of the source / drain groove; Step 5: Perform source / drain injection with the outer surface of the second sidewall as the self-alignment condition in the semiconductor substrate exposed at the bottom surface of the source / drain groove to form a source / drain region; the depth of the source / drain groove is used to set the spacing between the source / drain region and the first gate conductive material layer. By increasing the depth of the source / drain groove, the spacing between the source / drain region and the first gate conductive material layer is increased, thereby reducing GIDL leakage.

10. The method for improving the GIDL effect of an MV device as described in claim 9, characterized in that: The semiconductor substrate includes a silicon substrate.

11. The method for improving the GIDL effect of an MV device as described in claim 10, characterized in that: The material of the first gate dielectric layer includes an oxide layer.

12. The method for improving the GIDL effect of an MV device as described in claim 11, characterized in that: The first gate conductive material layer includes a polysilicon gate.

13. The method for improving the GIDL effect of an MV device as described in claim 12, characterized in that: The material of the first layer of sidewalls includes silicon nitride.

14. The method for improving the GIDL effect of an MV device as described in claim 13, characterized in that: After step two is completed and before step three is performed, the following is also included: A lightly doped drain region is formed in the semiconductor substrate outside the first layer sidewall by performing lightly doped drain implantation with the outer surface of the first layer sidewall as the self-alignment condition; The lightly doped drain region is formed by annealing and diffusion of the implantation region. After annealing and diffusion, the lightly doped drain region extends laterally to the bottom of the first gate conductive material layer and overlaps with it.

15. The method for improving the GIDL effect of an MV device as described in claim 14, characterized in that: The junction depth of the lightly doped drain region is greater than the depth of the source / drain groove, and the source / drain region formed at the bottom of the source / drain groove is still located in the lightly doped drain region.

16. The method for improving the GIDL effect of an MV device as described in claim 9 or 15, characterized in that: The depth of the source / drain trench in the semiconductor substrate is:

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